1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Invensense, Inc. 4 */ 5 6 #ifndef INV_MPU_IIO_H_ 7 #define INV_MPU_IIO_H_ 8 9 #include <linux/i2c.h> 10 #include <linux/i2c-mux.h> 11 #include <linux/mutex.h> 12 #include <linux/iio/iio.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/regmap.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/kfifo_buf.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/platform_data/invensense_mpu6050.h> 21 22 /** 23 * struct inv_mpu6050_reg_map - Notable registers. 24 * @sample_rate_div: Divider applied to gyro output rate. 25 * @lpf: Configures internal low pass filter. 26 * @accel_lpf: Configures accelerometer low pass filter. 27 * @user_ctrl: Enables/resets the FIFO. 28 * @fifo_en: Determines which data will appear in FIFO. 29 * @gyro_config: gyro config register. 30 * @accl_config: accel config register 31 * @fifo_count_h: Upper byte of FIFO count. 32 * @fifo_r_w: FIFO register. 33 * @raw_gyro: Address of first gyro register. 34 * @raw_accl: Address of first accel register. 35 * @temperature: temperature register 36 * @int_enable: Interrupt enable register. 37 * @int_status: Interrupt status register. 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 39 * @pwr_mgmt_2: Controls power state of individual sensors. 40 * @int_pin_cfg; Controls interrupt pin configuration. 41 * @accl_offset: Controls the accelerometer calibration offset. 42 * @gyro_offset: Controls the gyroscope calibration offset. 43 * @i2c_if: Controls the i2c interface 44 */ 45 struct inv_mpu6050_reg_map { 46 u8 sample_rate_div; 47 u8 lpf; 48 u8 accel_lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 int_status; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 u8 i2c_if; 66 }; 67 68 /*device enum */ 69 enum inv_devices { 70 INV_MPU6050, 71 INV_MPU6500, 72 INV_MPU6515, 73 INV_MPU6000, 74 INV_MPU9150, 75 INV_MPU9250, 76 INV_MPU9255, 77 INV_ICM20608, 78 INV_ICM20609, 79 INV_ICM20689, 80 INV_ICM20602, 81 INV_ICM20690, 82 INV_IAM20680, 83 INV_NUM_PARTS 84 }; 85 86 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */ 87 #define INV_MPU6050_SENSOR_ACCL BIT(0) 88 #define INV_MPU6050_SENSOR_GYRO BIT(1) 89 #define INV_MPU6050_SENSOR_TEMP BIT(2) 90 #define INV_MPU6050_SENSOR_MAGN BIT(3) 91 92 /** 93 * struct inv_mpu6050_chip_config - Cached chip configuration data. 94 * @clk: selected chip clock 95 * @fsr: Full scale range. 96 * @lpf: Digital low pass filter frequency. 97 * @accl_fs: accel full scale range. 98 * @accl_en: accel engine enabled 99 * @gyro_en: gyro engine enabled 100 * @temp_en: temperature sensor enabled 101 * @magn_en: magn engine (i2c master) enabled 102 * @accl_fifo_enable: enable accel data output 103 * @gyro_fifo_enable: enable gyro data output 104 * @temp_fifo_enable: enable temp data output 105 * @magn_fifo_enable: enable magn data output 106 * @divider: chip sample rate divider (sample rate divider - 1) 107 */ 108 struct inv_mpu6050_chip_config { 109 unsigned int clk:3; 110 unsigned int fsr:2; 111 unsigned int lpf:3; 112 unsigned int accl_fs:2; 113 unsigned int accl_en:1; 114 unsigned int gyro_en:1; 115 unsigned int temp_en:1; 116 unsigned int magn_en:1; 117 unsigned int accl_fifo_enable:1; 118 unsigned int gyro_fifo_enable:1; 119 unsigned int temp_fifo_enable:1; 120 unsigned int magn_fifo_enable:1; 121 u8 divider; 122 u8 user_ctrl; 123 }; 124 125 /** 126 * struct inv_mpu6050_hw - Other important hardware information. 127 * @whoami: Self identification byte from WHO_AM_I register 128 * @name: name of the chip. 129 * @reg: register map of the chip. 130 * @config: configuration of the chip. 131 * @fifo_size: size of the FIFO in bytes. 132 * @temp: offset and scale to apply to raw temperature. 133 */ 134 struct inv_mpu6050_hw { 135 u8 whoami; 136 u8 *name; 137 const struct inv_mpu6050_reg_map *reg; 138 const struct inv_mpu6050_chip_config *config; 139 size_t fifo_size; 140 struct { 141 int offset; 142 int scale; 143 } temp; 144 }; 145 146 /* 147 * struct inv_mpu6050_state - Driver state variables. 148 * @lock: Chip access lock. 149 * @trig: IIO trigger. 150 * @chip_config: Cached attribute information. 151 * @reg: Map of important registers. 152 * @hw: Other hardware-specific information. 153 * @chip_type: chip type. 154 * @plat_data: platform data (deprecated in favor of @orientation). 155 * @orientation: sensor chip orientation relative to main hardware. 156 * @map regmap pointer. 157 * @irq interrupt number. 158 * @irq_mask the int_pin_cfg mask to configure interrupt type. 159 * @chip_period: chip internal period estimation (~1kHz). 160 * @it_timestamp: timestamp from previous interrupt. 161 * @data_timestamp: timestamp for next data sample. 162 * @vdd_supply: VDD voltage regulator for the chip. 163 * @vddio_supply I/O voltage regulator for the chip. 164 * @magn_disabled: magnetometer disabled for backward compatibility reason. 165 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. 166 * @magn_orient: magnetometer sensor chip orientation if available. 167 * @suspended_sensors: sensors mask of sensors turned off for suspend 168 */ 169 struct inv_mpu6050_state { 170 struct mutex lock; 171 struct iio_trigger *trig; 172 struct inv_mpu6050_chip_config chip_config; 173 const struct inv_mpu6050_reg_map *reg; 174 const struct inv_mpu6050_hw *hw; 175 enum inv_devices chip_type; 176 struct i2c_mux_core *muxc; 177 struct i2c_client *mux_client; 178 struct inv_mpu6050_platform_data plat_data; 179 struct iio_mount_matrix orientation; 180 struct regmap *map; 181 int irq; 182 u8 irq_mask; 183 unsigned skip_samples; 184 s64 chip_period; 185 s64 it_timestamp; 186 s64 data_timestamp; 187 struct regulator *vdd_supply; 188 struct regulator *vddio_supply; 189 bool magn_disabled; 190 s32 magn_raw_to_gauss[3]; 191 struct iio_mount_matrix magn_orient; 192 unsigned int suspended_sensors; 193 }; 194 195 /*register and associated bit definition*/ 196 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 197 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 198 199 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 200 #define INV_MPU6050_REG_CONFIG 0x1A 201 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 202 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 203 204 #define INV_MPU6050_REG_FIFO_EN 0x23 205 #define INV_MPU6050_BIT_SLAVE_0 0x01 206 #define INV_MPU6050_BIT_SLAVE_1 0x02 207 #define INV_MPU6050_BIT_SLAVE_2 0x04 208 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 209 #define INV_MPU6050_BITS_GYRO_OUT 0x70 210 #define INV_MPU6050_BIT_TEMP_OUT 0x80 211 212 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24 213 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D 214 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 215 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 216 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 217 #define INV_MPU6050_BIT_MULT_MST_EN 0x80 218 219 /* control I2C slaves from 0 to 3 */ 220 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) 221 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 222 223 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) 224 225 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) 226 #define INV_MPU6050_BIT_SLV_GRP 0x10 227 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20 228 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 229 #define INV_MPU6050_BIT_SLV_EN 0x80 230 231 /* I2C master delay register */ 232 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 233 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) 234 235 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36 236 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 237 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 238 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 239 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 240 241 #define INV_MPU6050_REG_INT_ENABLE 0x38 242 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 243 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 244 245 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 246 #define INV_MPU6050_REG_TEMPERATURE 0x41 247 #define INV_MPU6050_REG_RAW_GYRO 0x43 248 249 #define INV_MPU6050_REG_INT_STATUS 0x3A 250 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 251 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 252 253 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49 254 255 /* I2C slaves data output from 0 to 3 */ 256 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) 257 258 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 259 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 260 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 261 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 262 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 263 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 264 265 #define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68 266 #define INV_MPU6050_BIT_TEMP_RST BIT(0) 267 #define INV_MPU6050_BIT_ACCEL_RST BIT(1) 268 #define INV_MPU6050_BIT_GYRO_RST BIT(2) 269 270 #define INV_MPU6050_REG_USER_CTRL 0x6A 271 #define INV_MPU6050_BIT_SIG_COND_RST 0x01 272 #define INV_MPU6050_BIT_FIFO_RST 0x04 273 #define INV_MPU6050_BIT_DMP_RST 0x08 274 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 275 #define INV_MPU6050_BIT_FIFO_EN 0x40 276 #define INV_MPU6050_BIT_DMP_EN 0x80 277 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 278 279 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 280 #define INV_MPU6050_BIT_H_RESET 0x80 281 #define INV_MPU6050_BIT_SLEEP 0x40 282 #define INV_MPU6050_BIT_TEMP_DIS 0x08 283 #define INV_MPU6050_BIT_CLK_MASK 0x7 284 285 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 286 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 287 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 288 289 /* ICM20602 register */ 290 #define INV_ICM20602_REG_I2C_IF 0x70 291 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 292 293 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 294 #define INV_MPU6050_REG_FIFO_R_W 0x74 295 296 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 297 #define INV_MPU6050_FIFO_COUNT_BYTE 2 298 299 /* MPU9X50 9-axis magnetometer */ 300 #define INV_MPU9X50_BYTES_MAGN 7 301 302 /* FIFO temperature sample size */ 303 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2 304 305 /* mpu6500 registers */ 306 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 307 #define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0 308 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 309 310 /* delay time in milliseconds */ 311 #define INV_MPU6050_POWER_UP_TIME 100 312 #define INV_MPU6050_TEMP_UP_TIME 100 313 #define INV_MPU6050_ACCEL_UP_TIME 20 314 #define INV_MPU6050_GYRO_UP_TIME 35 315 #define INV_MPU6050_GYRO_DOWN_TIME 150 316 #define INV_MPU6050_SUSPEND_DELAY_MS 2000 317 318 /* delay time in microseconds */ 319 #define INV_MPU6050_REG_UP_TIME_MIN 5000 320 #define INV_MPU6050_REG_UP_TIME_MAX 10000 321 322 #define INV_MPU6050_TEMP_OFFSET 12420 323 #define INV_MPU6050_TEMP_SCALE 2941176 324 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 325 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 326 #define INV_MPU6050_THREE_AXIS 3 327 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 328 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2 329 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 330 331 #define INV_MPU6500_TEMP_OFFSET 7011 332 #define INV_MPU6500_TEMP_SCALE 2995178 333 334 #define INV_ICM20608_TEMP_OFFSET 8170 335 #define INV_ICM20608_TEMP_SCALE 3059976 336 337 /* 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8 */ 338 #define INV_MPU6050_OUTPUT_DATA_SIZE 32 339 340 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 341 #define INV_MPU6050_ACTIVE_HIGH 0x00 342 #define INV_MPU6050_ACTIVE_LOW 0x80 343 /* enable level triggering */ 344 #define INV_MPU6050_LATCH_INT_EN 0x20 345 #define INV_MPU6050_BIT_BYPASS_EN 0x2 346 347 /* Allowed timestamp period jitter in percent */ 348 #define INV_MPU6050_TS_PERIOD_JITTER 4 349 350 /* init parameters */ 351 #define INV_MPU6050_MAX_FIFO_RATE 1000 352 #define INV_MPU6050_MIN_FIFO_RATE 4 353 354 /* chip internal frequency: 1KHz */ 355 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 356 /* return the frequency divider (chip sample rate divider + 1) */ 357 #define INV_MPU6050_FREQ_DIVIDER(st) \ 358 ((st)->chip_config.divider + 1) 359 /* chip sample rate divider to fifo rate */ 360 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 361 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 362 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 363 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 364 365 #define INV_MPU6050_REG_WHOAMI 117 366 367 #define INV_MPU6000_WHOAMI_VALUE 0x68 368 #define INV_MPU6050_WHOAMI_VALUE 0x68 369 #define INV_MPU6500_WHOAMI_VALUE 0x70 370 #define INV_MPU9150_WHOAMI_VALUE 0x68 371 #define INV_MPU9250_WHOAMI_VALUE 0x71 372 #define INV_MPU9255_WHOAMI_VALUE 0x73 373 #define INV_MPU6515_WHOAMI_VALUE 0x74 374 #define INV_ICM20608_WHOAMI_VALUE 0xAF 375 #define INV_ICM20609_WHOAMI_VALUE 0xA6 376 #define INV_ICM20689_WHOAMI_VALUE 0x98 377 #define INV_ICM20602_WHOAMI_VALUE 0x12 378 #define INV_ICM20690_WHOAMI_VALUE 0x20 379 #define INV_IAM20680_WHOAMI_VALUE 0xA9 380 381 /* scan element definition for generic MPU6xxx devices */ 382 enum inv_mpu6050_scan { 383 INV_MPU6050_SCAN_ACCL_X, 384 INV_MPU6050_SCAN_ACCL_Y, 385 INV_MPU6050_SCAN_ACCL_Z, 386 INV_MPU6050_SCAN_TEMP, 387 INV_MPU6050_SCAN_GYRO_X, 388 INV_MPU6050_SCAN_GYRO_Y, 389 INV_MPU6050_SCAN_GYRO_Z, 390 INV_MPU6050_SCAN_TIMESTAMP, 391 392 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, 393 INV_MPU9X50_SCAN_MAGN_Y, 394 INV_MPU9X50_SCAN_MAGN_Z, 395 INV_MPU9X50_SCAN_TIMESTAMP, 396 }; 397 398 enum inv_mpu6050_filter_e { 399 INV_MPU6050_FILTER_NOLPF2 = 0, 400 INV_MPU6050_FILTER_200HZ, 401 INV_MPU6050_FILTER_100HZ, 402 INV_MPU6050_FILTER_45HZ, 403 INV_MPU6050_FILTER_20HZ, 404 INV_MPU6050_FILTER_10HZ, 405 INV_MPU6050_FILTER_5HZ, 406 INV_MPU6050_FILTER_NOLPF, 407 NUM_MPU6050_FILTER 408 }; 409 410 /* IIO attribute address */ 411 enum INV_MPU6050_IIO_ATTR_ADDR { 412 ATTR_GYRO_MATRIX, 413 ATTR_ACCL_MATRIX, 414 }; 415 416 enum inv_mpu6050_accl_fs_e { 417 INV_MPU6050_FS_02G = 0, 418 INV_MPU6050_FS_04G, 419 INV_MPU6050_FS_08G, 420 INV_MPU6050_FS_16G, 421 NUM_ACCL_FSR 422 }; 423 424 enum inv_mpu6050_fsr_e { 425 INV_MPU6050_FSR_250DPS = 0, 426 INV_MPU6050_FSR_500DPS, 427 INV_MPU6050_FSR_1000DPS, 428 INV_MPU6050_FSR_2000DPS, 429 NUM_MPU6050_FSR 430 }; 431 432 enum inv_mpu6050_clock_sel_e { 433 INV_CLK_INTERNAL = 0, 434 INV_CLK_PLL, 435 NUM_CLK 436 }; 437 438 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 439 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 440 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); 441 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, 442 unsigned int mask); 443 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 444 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 445 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 446 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 447 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 448 extern const struct dev_pm_ops inv_mpu_pmops; 449 450 #endif 451