1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 Invensense, Inc.
4 */
5 
6 #ifndef INV_MPU_IIO_H_
7 #define INV_MPU_IIO_H_
8 
9 #include <linux/i2c.h>
10 #include <linux/i2c-mux.h>
11 #include <linux/mutex.h>
12 #include <linux/iio/iio.h>
13 #include <linux/iio/buffer.h>
14 #include <linux/regmap.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/kfifo_buf.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/triggered_buffer.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/platform_data/invensense_mpu6050.h>
21 
22 /**
23  *  struct inv_mpu6050_reg_map - Notable registers.
24  *  @sample_rate_div:	Divider applied to gyro output rate.
25  *  @lpf:		Configures internal low pass filter.
26  *  @accel_lpf:		Configures accelerometer low pass filter.
27  *  @user_ctrl:		Enables/resets the FIFO.
28  *  @fifo_en:		Determines which data will appear in FIFO.
29  *  @gyro_config:	gyro config register.
30  *  @accl_config:	accel config register
31  *  @fifo_count_h:	Upper byte of FIFO count.
32  *  @fifo_r_w:		FIFO register.
33  *  @raw_gyro:		Address of first gyro register.
34  *  @raw_accl:		Address of first accel register.
35  *  @temperature:	temperature register
36  *  @int_enable:	Interrupt enable register.
37  *  @int_status:	Interrupt status register.
38  *  @pwr_mgmt_1:	Controls chip's power state and clock source.
39  *  @pwr_mgmt_2:	Controls power state of individual sensors.
40  *  @int_pin_cfg;	Controls interrupt pin configuration.
41  *  @accl_offset:	Controls the accelerometer calibration offset.
42  *  @gyro_offset:	Controls the gyroscope calibration offset.
43  *  @i2c_if:		Controls the i2c interface
44  */
45 struct inv_mpu6050_reg_map {
46 	u8 sample_rate_div;
47 	u8 lpf;
48 	u8 accel_lpf;
49 	u8 user_ctrl;
50 	u8 fifo_en;
51 	u8 gyro_config;
52 	u8 accl_config;
53 	u8 fifo_count_h;
54 	u8 fifo_r_w;
55 	u8 raw_gyro;
56 	u8 raw_accl;
57 	u8 temperature;
58 	u8 int_enable;
59 	u8 int_status;
60 	u8 pwr_mgmt_1;
61 	u8 pwr_mgmt_2;
62 	u8 int_pin_cfg;
63 	u8 accl_offset;
64 	u8 gyro_offset;
65 	u8 i2c_if;
66 };
67 
68 /*device enum */
69 enum inv_devices {
70 	INV_MPU6050,
71 	INV_MPU6500,
72 	INV_MPU6515,
73 	INV_MPU6880,
74 	INV_MPU6000,
75 	INV_MPU9150,
76 	INV_MPU9250,
77 	INV_MPU9255,
78 	INV_ICM20608,
79 	INV_ICM20608D,
80 	INV_ICM20609,
81 	INV_ICM20689,
82 	INV_ICM20602,
83 	INV_ICM20690,
84 	INV_IAM20680,
85 	INV_NUM_PARTS
86 };
87 
88 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */
89 #define INV_MPU6050_SENSOR_ACCL		BIT(0)
90 #define INV_MPU6050_SENSOR_GYRO		BIT(1)
91 #define INV_MPU6050_SENSOR_TEMP		BIT(2)
92 #define INV_MPU6050_SENSOR_MAGN		BIT(3)
93 
94 /**
95  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
96  *  @clk:		selected chip clock
97  *  @fsr:		Full scale range.
98  *  @lpf:		Digital low pass filter frequency.
99  *  @accl_fs:		accel full scale range.
100  *  @accl_en:		accel engine enabled
101  *  @gyro_en:		gyro engine enabled
102  *  @temp_en:		temperature sensor enabled
103  *  @magn_en:		magn engine (i2c master) enabled
104  *  @accl_fifo_enable:	enable accel data output
105  *  @gyro_fifo_enable:	enable gyro data output
106  *  @temp_fifo_enable:	enable temp data output
107  *  @magn_fifo_enable:	enable magn data output
108  *  @divider:		chip sample rate divider (sample rate divider - 1)
109  */
110 struct inv_mpu6050_chip_config {
111 	unsigned int clk:3;
112 	unsigned int fsr:2;
113 	unsigned int lpf:3;
114 	unsigned int accl_fs:2;
115 	unsigned int accl_en:1;
116 	unsigned int gyro_en:1;
117 	unsigned int temp_en:1;
118 	unsigned int magn_en:1;
119 	unsigned int accl_fifo_enable:1;
120 	unsigned int gyro_fifo_enable:1;
121 	unsigned int temp_fifo_enable:1;
122 	unsigned int magn_fifo_enable:1;
123 	u8 divider;
124 	u8 user_ctrl;
125 };
126 
127 /*
128  * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
129  * May be less if fewer channels are enabled, as long as the timestamp
130  * remains 8 byte aligned
131  */
132 #define INV_MPU6050_OUTPUT_DATA_SIZE         32
133 
134 /**
135  *  struct inv_mpu6050_hw - Other important hardware information.
136  *  @whoami:	Self identification byte from WHO_AM_I register
137  *  @name:      name of the chip.
138  *  @reg:   register map of the chip.
139  *  @config:    configuration of the chip.
140  *  @fifo_size:	size of the FIFO in bytes.
141  *  @temp:	offset and scale to apply to raw temperature.
142  */
143 struct inv_mpu6050_hw {
144 	u8 whoami;
145 	u8 *name;
146 	const struct inv_mpu6050_reg_map *reg;
147 	const struct inv_mpu6050_chip_config *config;
148 	size_t fifo_size;
149 	struct {
150 		int offset;
151 		int scale;
152 	} temp;
153 	struct {
154 		unsigned int accel;
155 		unsigned int gyro;
156 	} startup_time;
157 };
158 
159 /*
160  *  struct inv_mpu6050_state - Driver state variables.
161  *  @lock:              Chip access lock.
162  *  @trig:              IIO trigger.
163  *  @chip_config:	Cached attribute information.
164  *  @reg:		Map of important registers.
165  *  @hw:		Other hardware-specific information.
166  *  @chip_type:		chip type.
167  *  @plat_data:		platform data (deprecated in favor of @orientation).
168  *  @orientation:	sensor chip orientation relative to main hardware.
169  *  @map		regmap pointer.
170  *  @irq		interrupt number.
171  *  @irq_mask		the int_pin_cfg mask to configure interrupt type.
172  *  @chip_period:	chip internal period estimation (~1kHz).
173  *  @it_timestamp:	timestamp from previous interrupt.
174  *  @data_timestamp:	timestamp for next data sample.
175  *  @vdd_supply:	VDD voltage regulator for the chip.
176  *  @vddio_supply	I/O voltage regulator for the chip.
177  *  @magn_disabled:     magnetometer disabled for backward compatibility reason.
178  *  @magn_raw_to_gauss:	coefficient to convert mag raw value to Gauss.
179  *  @magn_orient:       magnetometer sensor chip orientation if available.
180  *  @suspended_sensors:	sensors mask of sensors turned off for suspend
181  *  @data:		dma safe buffer used for bulk reads.
182  */
183 struct inv_mpu6050_state {
184 	struct mutex lock;
185 	struct iio_trigger  *trig;
186 	struct inv_mpu6050_chip_config chip_config;
187 	const struct inv_mpu6050_reg_map *reg;
188 	const struct inv_mpu6050_hw *hw;
189 	enum   inv_devices chip_type;
190 	struct i2c_mux_core *muxc;
191 	struct i2c_client *mux_client;
192 	struct inv_mpu6050_platform_data plat_data;
193 	struct iio_mount_matrix orientation;
194 	struct regmap *map;
195 	int irq;
196 	u8 irq_mask;
197 	unsigned skip_samples;
198 	s64 chip_period;
199 	s64 it_timestamp;
200 	s64 data_timestamp;
201 	struct regulator *vdd_supply;
202 	struct regulator *vddio_supply;
203 	bool magn_disabled;
204 	s32 magn_raw_to_gauss[3];
205 	struct iio_mount_matrix magn_orient;
206 	unsigned int suspended_sensors;
207 	u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_DMA_MINALIGN);
208 };
209 
210 /*register and associated bit definition*/
211 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
212 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
213 
214 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
215 #define INV_MPU6050_REG_CONFIG              0x1A
216 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
217 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
218 
219 #define INV_MPU6050_REG_FIFO_EN             0x23
220 #define INV_MPU6050_BIT_SLAVE_0             0x01
221 #define INV_MPU6050_BIT_SLAVE_1             0x02
222 #define INV_MPU6050_BIT_SLAVE_2             0x04
223 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
224 #define INV_MPU6050_BITS_GYRO_OUT           0x70
225 #define INV_MPU6050_BIT_TEMP_OUT            0x80
226 
227 #define INV_MPU6050_REG_I2C_MST_CTRL        0x24
228 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
229 #define INV_MPU6050_BIT_I2C_MST_P_NSR       0x10
230 #define INV_MPU6050_BIT_SLV3_FIFO_EN        0x20
231 #define INV_MPU6050_BIT_WAIT_FOR_ES         0x40
232 #define INV_MPU6050_BIT_MULT_MST_EN         0x80
233 
234 /* control I2C slaves from 0 to 3 */
235 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x)    (0x25 + 3 * (_x))
236 #define INV_MPU6050_BIT_I2C_SLV_RNW         0x80
237 
238 #define INV_MPU6050_REG_I2C_SLV_REG(_x)     (0x26 + 3 * (_x))
239 
240 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x)    (0x27 + 3 * (_x))
241 #define INV_MPU6050_BIT_SLV_GRP             0x10
242 #define INV_MPU6050_BIT_SLV_REG_DIS         0x20
243 #define INV_MPU6050_BIT_SLV_BYTE_SW         0x40
244 #define INV_MPU6050_BIT_SLV_EN              0x80
245 
246 /* I2C master delay register */
247 #define INV_MPU6050_REG_I2C_SLV4_CTRL       0x34
248 #define INV_MPU6050_BITS_I2C_MST_DLY(_x)    ((_x) & 0x1F)
249 
250 #define INV_MPU6050_REG_I2C_MST_STATUS      0x36
251 #define INV_MPU6050_BIT_I2C_SLV0_NACK       0x01
252 #define INV_MPU6050_BIT_I2C_SLV1_NACK       0x02
253 #define INV_MPU6050_BIT_I2C_SLV2_NACK       0x04
254 #define INV_MPU6050_BIT_I2C_SLV3_NACK       0x08
255 
256 #define INV_MPU6050_REG_INT_ENABLE          0x38
257 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
258 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
259 
260 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
261 #define INV_MPU6050_REG_TEMPERATURE         0x41
262 #define INV_MPU6050_REG_RAW_GYRO            0x43
263 
264 #define INV_MPU6050_REG_INT_STATUS          0x3A
265 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
266 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
267 
268 #define INV_MPU6050_REG_EXT_SENS_DATA       0x49
269 
270 /* I2C slaves data output from 0 to 3 */
271 #define INV_MPU6050_REG_I2C_SLV_DO(_x)      (0x63 + (_x))
272 
273 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL  0x67
274 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN     0x01
275 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN     0x02
276 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN     0x04
277 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN     0x08
278 #define INV_MPU6050_BIT_DELAY_ES_SHADOW     0x80
279 
280 #define INV_MPU6050_REG_SIGNAL_PATH_RESET   0x68
281 #define INV_MPU6050_BIT_TEMP_RST            BIT(0)
282 #define INV_MPU6050_BIT_ACCEL_RST           BIT(1)
283 #define INV_MPU6050_BIT_GYRO_RST            BIT(2)
284 
285 #define INV_MPU6050_REG_USER_CTRL           0x6A
286 #define INV_MPU6050_BIT_SIG_COND_RST        0x01
287 #define INV_MPU6050_BIT_FIFO_RST            0x04
288 #define INV_MPU6050_BIT_DMP_RST             0x08
289 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
290 #define INV_MPU6050_BIT_FIFO_EN             0x40
291 #define INV_MPU6050_BIT_DMP_EN              0x80
292 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
293 
294 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
295 #define INV_MPU6050_BIT_H_RESET             0x80
296 #define INV_MPU6050_BIT_SLEEP               0x40
297 #define INV_MPU6050_BIT_TEMP_DIS            0x08
298 #define INV_MPU6050_BIT_CLK_MASK            0x7
299 
300 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
301 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
302 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
303 
304 /* ICM20602 register */
305 #define INV_ICM20602_REG_I2C_IF             0x70
306 #define INV_ICM20602_BIT_I2C_IF_DIS         0x40
307 
308 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
309 #define INV_MPU6050_REG_FIFO_R_W            0x74
310 
311 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
312 #define INV_MPU6050_FIFO_COUNT_BYTE          2
313 
314 /* MPU9X50 9-axis magnetometer */
315 #define INV_MPU9X50_BYTES_MAGN               7
316 
317 /* FIFO temperature sample size */
318 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR   2
319 
320 /* mpu6500 registers */
321 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
322 #define INV_ICM20689_BITS_FIFO_SIZE_MAX     0xC0
323 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
324 
325 /* delay time in milliseconds */
326 #define INV_MPU6050_POWER_UP_TIME            100
327 #define INV_MPU6050_TEMP_UP_TIME             100
328 #define INV_MPU6050_ACCEL_STARTUP_TIME       20
329 #define INV_MPU6050_GYRO_STARTUP_TIME        60
330 #define INV_MPU6050_GYRO_DOWN_TIME           150
331 #define INV_MPU6050_SUSPEND_DELAY_MS         2000
332 
333 #define INV_MPU6500_GYRO_STARTUP_TIME        70
334 #define INV_MPU6500_ACCEL_STARTUP_TIME       30
335 
336 #define INV_ICM20602_GYRO_STARTUP_TIME       100
337 #define INV_ICM20602_ACCEL_STARTUP_TIME      20
338 
339 #define INV_ICM20690_GYRO_STARTUP_TIME       80
340 #define INV_ICM20690_ACCEL_STARTUP_TIME      10
341 
342 
343 /* delay time in microseconds */
344 #define INV_MPU6050_REG_UP_TIME_MIN          5000
345 #define INV_MPU6050_REG_UP_TIME_MAX          10000
346 
347 #define INV_MPU6050_TEMP_OFFSET	             12420
348 #define INV_MPU6050_TEMP_SCALE               2941176
349 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
350 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
351 #define INV_MPU6050_THREE_AXIS               3
352 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
353 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT   2
354 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
355 
356 #define INV_MPU6500_TEMP_OFFSET              7011
357 #define INV_MPU6500_TEMP_SCALE               2995178
358 
359 #define INV_ICM20608_TEMP_OFFSET	     8170
360 #define INV_ICM20608_TEMP_SCALE		     3059976
361 
362 #define INV_MPU6050_REG_INT_PIN_CFG	0x37
363 #define INV_MPU6050_ACTIVE_HIGH		0x00
364 #define INV_MPU6050_ACTIVE_LOW		0x80
365 /* enable level triggering */
366 #define INV_MPU6050_LATCH_INT_EN	0x20
367 #define INV_MPU6050_BIT_BYPASS_EN	0x2
368 
369 /* Allowed timestamp period jitter in percent */
370 #define INV_MPU6050_TS_PERIOD_JITTER	4
371 
372 /* init parameters */
373 #define INV_MPU6050_MAX_FIFO_RATE            1000
374 #define INV_MPU6050_MIN_FIFO_RATE            4
375 
376 /* chip internal frequency: 1KHz */
377 #define INV_MPU6050_INTERNAL_FREQ_HZ		1000
378 /* return the frequency divider (chip sample rate divider + 1) */
379 #define INV_MPU6050_FREQ_DIVIDER(st)					\
380 	((st)->chip_config.divider + 1)
381 /* chip sample rate divider to fifo rate */
382 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)			\
383 	((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
384 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)			\
385 	(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
386 
387 #define INV_MPU6050_REG_WHOAMI			117
388 
389 #define INV_MPU6000_WHOAMI_VALUE		0x68
390 #define INV_MPU6050_WHOAMI_VALUE		0x68
391 #define INV_MPU6500_WHOAMI_VALUE		0x70
392 #define INV_MPU6880_WHOAMI_VALUE		0x78
393 #define INV_MPU9150_WHOAMI_VALUE		0x68
394 #define INV_MPU9250_WHOAMI_VALUE		0x71
395 #define INV_MPU9255_WHOAMI_VALUE		0x73
396 #define INV_MPU6515_WHOAMI_VALUE		0x74
397 #define INV_ICM20608_WHOAMI_VALUE		0xAF
398 #define INV_ICM20608D_WHOAMI_VALUE		0xAE
399 #define INV_ICM20609_WHOAMI_VALUE		0xA6
400 #define INV_ICM20689_WHOAMI_VALUE		0x98
401 #define INV_ICM20602_WHOAMI_VALUE		0x12
402 #define INV_ICM20690_WHOAMI_VALUE		0x20
403 #define INV_IAM20680_WHOAMI_VALUE		0xA9
404 
405 /* scan element definition for generic MPU6xxx devices */
406 enum inv_mpu6050_scan {
407 	INV_MPU6050_SCAN_ACCL_X,
408 	INV_MPU6050_SCAN_ACCL_Y,
409 	INV_MPU6050_SCAN_ACCL_Z,
410 	INV_MPU6050_SCAN_TEMP,
411 	INV_MPU6050_SCAN_GYRO_X,
412 	INV_MPU6050_SCAN_GYRO_Y,
413 	INV_MPU6050_SCAN_GYRO_Z,
414 	INV_MPU6050_SCAN_TIMESTAMP,
415 
416 	INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
417 	INV_MPU9X50_SCAN_MAGN_Y,
418 	INV_MPU9X50_SCAN_MAGN_Z,
419 	INV_MPU9X50_SCAN_TIMESTAMP,
420 };
421 
422 enum inv_mpu6050_filter_e {
423 	INV_MPU6050_FILTER_NOLPF2 = 0,
424 	INV_MPU6050_FILTER_200HZ,
425 	INV_MPU6050_FILTER_100HZ,
426 	INV_MPU6050_FILTER_45HZ,
427 	INV_MPU6050_FILTER_20HZ,
428 	INV_MPU6050_FILTER_10HZ,
429 	INV_MPU6050_FILTER_5HZ,
430 	INV_MPU6050_FILTER_NOLPF,
431 	NUM_MPU6050_FILTER
432 };
433 
434 /* IIO attribute address */
435 enum INV_MPU6050_IIO_ATTR_ADDR {
436 	ATTR_GYRO_MATRIX,
437 	ATTR_ACCL_MATRIX,
438 };
439 
440 enum inv_mpu6050_accl_fs_e {
441 	INV_MPU6050_FS_02G = 0,
442 	INV_MPU6050_FS_04G,
443 	INV_MPU6050_FS_08G,
444 	INV_MPU6050_FS_16G,
445 	NUM_ACCL_FSR
446 };
447 
448 enum inv_mpu6050_fsr_e {
449 	INV_MPU6050_FSR_250DPS = 0,
450 	INV_MPU6050_FSR_500DPS,
451 	INV_MPU6050_FSR_1000DPS,
452 	INV_MPU6050_FSR_2000DPS,
453 	NUM_MPU6050_FSR
454 };
455 
456 enum inv_mpu6050_clock_sel_e {
457 	INV_CLK_INTERNAL = 0,
458 	INV_CLK_PLL,
459 	NUM_CLK
460 };
461 
462 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
463 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
464 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
465 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
466 			      unsigned int mask);
467 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
468 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
469 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
470 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
471 		int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
472 extern const struct dev_pm_ops inv_mpu_pmops;
473 
474 #endif
475