1 /* 2 * Copyright (C) 2012 Invensense, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/i2c.h> 14 #include <linux/kfifo.h> 15 #include <linux/spinlock.h> 16 #include <linux/iio/iio.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/regmap.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/kfifo_buf.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/platform_data/invensense_mpu6050.h> 25 26 /** 27 * struct inv_mpu6050_reg_map - Notable registers. 28 * @sample_rate_div: Divider applied to gyro output rate. 29 * @lpf: Configures internal low pass filter. 30 * @user_ctrl: Enables/resets the FIFO. 31 * @fifo_en: Determines which data will appear in FIFO. 32 * @gyro_config: gyro config register. 33 * @accl_config: accel config register 34 * @fifo_count_h: Upper byte of FIFO count. 35 * @fifo_r_w: FIFO register. 36 * @raw_gyro: Address of first gyro register. 37 * @raw_accl: Address of first accel register. 38 * @temperature: temperature register 39 * @int_enable: Interrupt enable register. 40 * @pwr_mgmt_1: Controls chip's power state and clock source. 41 * @pwr_mgmt_2: Controls power state of individual sensors. 42 * @int_pin_cfg; Controls interrupt pin configuration. 43 * @accl_offset: Controls the accelerometer calibration offset. 44 * @gyro_offset: Controls the gyroscope calibration offset. 45 */ 46 struct inv_mpu6050_reg_map { 47 u8 sample_rate_div; 48 u8 lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 pwr_mgmt_1; 60 u8 pwr_mgmt_2; 61 u8 int_pin_cfg; 62 u8 accl_offset; 63 u8 gyro_offset; 64 }; 65 66 /*device enum */ 67 enum inv_devices { 68 INV_MPU6050, 69 INV_MPU6500, 70 INV_MPU6000, 71 INV_NUM_PARTS 72 }; 73 74 /** 75 * struct inv_mpu6050_chip_config - Cached chip configuration data. 76 * @fsr: Full scale range. 77 * @lpf: Digital low pass filter frequency. 78 * @accl_fs: accel full scale range. 79 * @enable: master enable state. 80 * @accl_fifo_enable: enable accel data output 81 * @gyro_fifo_enable: enable gyro data output 82 * @fifo_rate: FIFO update rate. 83 */ 84 struct inv_mpu6050_chip_config { 85 unsigned int fsr:2; 86 unsigned int lpf:3; 87 unsigned int accl_fs:2; 88 unsigned int enable:1; 89 unsigned int accl_fifo_enable:1; 90 unsigned int gyro_fifo_enable:1; 91 u16 fifo_rate; 92 }; 93 94 /** 95 * struct inv_mpu6050_hw - Other important hardware information. 96 * @num_reg: Number of registers on device. 97 * @name: name of the chip. 98 * @reg: register map of the chip. 99 * @config: configuration of the chip. 100 */ 101 struct inv_mpu6050_hw { 102 u8 num_reg; 103 u8 *name; 104 const struct inv_mpu6050_reg_map *reg; 105 const struct inv_mpu6050_chip_config *config; 106 }; 107 108 /* 109 * struct inv_mpu6050_state - Driver state variables. 110 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. 111 * @trig: IIO trigger. 112 * @chip_config: Cached attribute information. 113 * @reg: Map of important registers. 114 * @hw: Other hardware-specific information. 115 * @chip_type: chip type. 116 * @time_stamp_lock: spin lock to time stamp. 117 * @plat_data: platform data. 118 * @timestamps: kfifo queue to store time stamp. 119 * @map regmap pointer. 120 * @irq interrupt number. 121 */ 122 struct inv_mpu6050_state { 123 #define TIMESTAMP_FIFO_SIZE 16 124 struct iio_trigger *trig; 125 struct inv_mpu6050_chip_config chip_config; 126 const struct inv_mpu6050_reg_map *reg; 127 const struct inv_mpu6050_hw *hw; 128 enum inv_devices chip_type; 129 spinlock_t time_stamp_lock; 130 struct i2c_adapter *mux_adapter; 131 struct i2c_client *mux_client; 132 unsigned int powerup_count; 133 struct inv_mpu6050_platform_data plat_data; 134 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); 135 struct regmap *map; 136 int irq; 137 }; 138 139 /*register and associated bit definition*/ 140 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 141 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 142 143 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 144 #define INV_MPU6050_REG_CONFIG 0x1A 145 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 146 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 147 148 #define INV_MPU6050_REG_FIFO_EN 0x23 149 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 150 #define INV_MPU6050_BITS_GYRO_OUT 0x70 151 152 #define INV_MPU6050_REG_INT_ENABLE 0x38 153 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 154 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 155 156 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 157 #define INV_MPU6050_REG_TEMPERATURE 0x41 158 #define INV_MPU6050_REG_RAW_GYRO 0x43 159 160 #define INV_MPU6050_REG_USER_CTRL 0x6A 161 #define INV_MPU6050_BIT_FIFO_RST 0x04 162 #define INV_MPU6050_BIT_DMP_RST 0x08 163 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 164 #define INV_MPU6050_BIT_FIFO_EN 0x40 165 #define INV_MPU6050_BIT_DMP_EN 0x80 166 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 167 168 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 169 #define INV_MPU6050_BIT_H_RESET 0x80 170 #define INV_MPU6050_BIT_SLEEP 0x40 171 #define INV_MPU6050_BIT_CLK_MASK 0x7 172 173 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 174 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 175 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 176 177 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 178 #define INV_MPU6050_REG_FIFO_R_W 0x74 179 180 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 181 #define INV_MPU6050_FIFO_COUNT_BYTE 2 182 #define INV_MPU6050_FIFO_THRESHOLD 500 183 184 /* mpu6500 registers */ 185 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 186 187 /* delay time in milliseconds */ 188 #define INV_MPU6050_POWER_UP_TIME 100 189 #define INV_MPU6050_TEMP_UP_TIME 100 190 #define INV_MPU6050_SENSOR_UP_TIME 30 191 192 /* delay time in microseconds */ 193 #define INV_MPU6050_REG_UP_TIME_MIN 5000 194 #define INV_MPU6050_REG_UP_TIME_MAX 10000 195 196 #define INV_MPU6050_TEMP_OFFSET 12421 197 #define INV_MPU6050_TEMP_SCALE 2941 198 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 199 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 200 #define INV_MPU6050_THREE_AXIS 3 201 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 202 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 203 204 /* 6 + 6 round up and plus 8 */ 205 #define INV_MPU6050_OUTPUT_DATA_SIZE 24 206 207 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 208 #define INV_MPU6050_BIT_BYPASS_EN 0x2 209 #define INV_MPU6050_INT_PIN_CFG 0 210 211 /* init parameters */ 212 #define INV_MPU6050_INIT_FIFO_RATE 50 213 #define INV_MPU6050_TIME_STAMP_TOR 5 214 #define INV_MPU6050_MAX_FIFO_RATE 1000 215 #define INV_MPU6050_MIN_FIFO_RATE 4 216 #define INV_MPU6050_ONE_K_HZ 1000 217 218 /* scan element definition */ 219 enum inv_mpu6050_scan { 220 INV_MPU6050_SCAN_ACCL_X, 221 INV_MPU6050_SCAN_ACCL_Y, 222 INV_MPU6050_SCAN_ACCL_Z, 223 INV_MPU6050_SCAN_GYRO_X, 224 INV_MPU6050_SCAN_GYRO_Y, 225 INV_MPU6050_SCAN_GYRO_Z, 226 INV_MPU6050_SCAN_TIMESTAMP, 227 }; 228 229 enum inv_mpu6050_filter_e { 230 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 231 INV_MPU6050_FILTER_188HZ, 232 INV_MPU6050_FILTER_98HZ, 233 INV_MPU6050_FILTER_42HZ, 234 INV_MPU6050_FILTER_20HZ, 235 INV_MPU6050_FILTER_10HZ, 236 INV_MPU6050_FILTER_5HZ, 237 INV_MPU6050_FILTER_2100HZ_NOLPF, 238 NUM_MPU6050_FILTER 239 }; 240 241 /* IIO attribute address */ 242 enum INV_MPU6050_IIO_ATTR_ADDR { 243 ATTR_GYRO_MATRIX, 244 ATTR_ACCL_MATRIX, 245 }; 246 247 enum inv_mpu6050_accl_fs_e { 248 INV_MPU6050_FS_02G = 0, 249 INV_MPU6050_FS_04G, 250 INV_MPU6050_FS_08G, 251 INV_MPU6050_FS_16G, 252 NUM_ACCL_FSR 253 }; 254 255 enum inv_mpu6050_fsr_e { 256 INV_MPU6050_FSR_250DPS = 0, 257 INV_MPU6050_FSR_500DPS, 258 INV_MPU6050_FSR_1000DPS, 259 INV_MPU6050_FSR_2000DPS, 260 NUM_MPU6050_FSR 261 }; 262 263 enum inv_mpu6050_clock_sel_e { 264 INV_CLK_INTERNAL = 0, 265 INV_CLK_PLL, 266 NUM_CLK 267 }; 268 269 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); 270 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 271 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev); 272 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st); 273 int inv_reset_fifo(struct iio_dev *indio_dev); 274 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 275 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 276 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 277 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 278 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 279 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 280 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 281 int inv_mpu_core_remove(struct device *dev); 282 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 283 extern const struct dev_pm_ops inv_mpu_pmops; 284