1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2020 Invensense, Inc. 4 */ 5 6 #ifndef INV_ICM42600_H_ 7 #define INV_ICM42600_H_ 8 9 #include <linux/bits.h> 10 #include <linux/bitfield.h> 11 #include <linux/regmap.h> 12 #include <linux/mutex.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/pm.h> 15 #include <linux/iio/iio.h> 16 17 enum inv_icm42600_chip { 18 INV_CHIP_ICM42600, 19 INV_CHIP_ICM42602, 20 INV_CHIP_ICM42605, 21 INV_CHIP_ICM42622, 22 INV_CHIP_NB, 23 }; 24 25 /* serial bus slew rates */ 26 enum inv_icm42600_slew_rate { 27 INV_ICM42600_SLEW_RATE_20_60NS, 28 INV_ICM42600_SLEW_RATE_12_36NS, 29 INV_ICM42600_SLEW_RATE_6_18NS, 30 INV_ICM42600_SLEW_RATE_4_12NS, 31 INV_ICM42600_SLEW_RATE_2_6NS, 32 INV_ICM42600_SLEW_RATE_INF_2NS, 33 }; 34 35 enum inv_icm42600_sensor_mode { 36 INV_ICM42600_SENSOR_MODE_OFF, 37 INV_ICM42600_SENSOR_MODE_STANDBY, 38 INV_ICM42600_SENSOR_MODE_LOW_POWER, 39 INV_ICM42600_SENSOR_MODE_LOW_NOISE, 40 INV_ICM42600_SENSOR_MODE_NB, 41 }; 42 43 /* gyroscope fullscale values */ 44 enum inv_icm42600_gyro_fs { 45 INV_ICM42600_GYRO_FS_2000DPS, 46 INV_ICM42600_GYRO_FS_1000DPS, 47 INV_ICM42600_GYRO_FS_500DPS, 48 INV_ICM42600_GYRO_FS_250DPS, 49 INV_ICM42600_GYRO_FS_125DPS, 50 INV_ICM42600_GYRO_FS_62_5DPS, 51 INV_ICM42600_GYRO_FS_31_25DPS, 52 INV_ICM42600_GYRO_FS_15_625DPS, 53 INV_ICM42600_GYRO_FS_NB, 54 }; 55 56 /* accelerometer fullscale values */ 57 enum inv_icm42600_accel_fs { 58 INV_ICM42600_ACCEL_FS_16G, 59 INV_ICM42600_ACCEL_FS_8G, 60 INV_ICM42600_ACCEL_FS_4G, 61 INV_ICM42600_ACCEL_FS_2G, 62 INV_ICM42600_ACCEL_FS_NB, 63 }; 64 65 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ 66 enum inv_icm42600_odr { 67 INV_ICM42600_ODR_8KHZ_LN = 3, 68 INV_ICM42600_ODR_4KHZ_LN, 69 INV_ICM42600_ODR_2KHZ_LN, 70 INV_ICM42600_ODR_1KHZ_LN, 71 INV_ICM42600_ODR_200HZ, 72 INV_ICM42600_ODR_100HZ, 73 INV_ICM42600_ODR_50HZ, 74 INV_ICM42600_ODR_25HZ, 75 INV_ICM42600_ODR_12_5HZ, 76 INV_ICM42600_ODR_6_25HZ_LP, 77 INV_ICM42600_ODR_3_125HZ_LP, 78 INV_ICM42600_ODR_1_5625HZ_LP, 79 INV_ICM42600_ODR_500HZ, 80 INV_ICM42600_ODR_NB, 81 }; 82 83 enum inv_icm42600_filter { 84 /* Low-Noise mode sensor data filter (3rd order filter by default) */ 85 INV_ICM42600_FILTER_BW_ODR_DIV_2, 86 87 /* Low-Power mode sensor data filter (averaging) */ 88 INV_ICM42600_FILTER_AVG_1X = 1, 89 INV_ICM42600_FILTER_AVG_16X = 6, 90 }; 91 92 struct inv_icm42600_sensor_conf { 93 int mode; 94 int fs; 95 int odr; 96 int filter; 97 }; 98 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1} 99 100 struct inv_icm42600_conf { 101 struct inv_icm42600_sensor_conf gyro; 102 struct inv_icm42600_sensor_conf accel; 103 bool temp_en; 104 }; 105 106 struct inv_icm42600_suspended { 107 enum inv_icm42600_sensor_mode gyro; 108 enum inv_icm42600_sensor_mode accel; 109 bool temp; 110 }; 111 112 /** 113 * struct inv_icm42600_state - driver state variables 114 * @lock: lock for serializing multiple registers access. 115 * @chip: chip identifier. 116 * @name: chip name. 117 * @map: regmap pointer. 118 * @vdd_supply: VDD voltage regulator for the chip. 119 * @vddio_supply: I/O voltage regulator for the chip. 120 * @orientation: sensor chip orientation relative to main hardware. 121 * @conf: chip sensors configurations. 122 * @suspended: suspended sensors configuration. 123 * @indio_gyro: gyroscope IIO device. 124 * @indio_accel: accelerometer IIO device. 125 * @buffer: data transfer buffer aligned for DMA. 126 */ 127 struct inv_icm42600_state { 128 struct mutex lock; 129 enum inv_icm42600_chip chip; 130 const char *name; 131 struct regmap *map; 132 struct regulator *vdd_supply; 133 struct regulator *vddio_supply; 134 struct iio_mount_matrix orientation; 135 struct inv_icm42600_conf conf; 136 struct inv_icm42600_suspended suspended; 137 struct iio_dev *indio_gyro; 138 struct iio_dev *indio_accel; 139 uint8_t buffer[2] ____cacheline_aligned; 140 }; 141 142 /* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ 143 144 /* Bank selection register, available in all banks */ 145 #define INV_ICM42600_REG_BANK_SEL 0x76 146 #define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0) 147 148 /* User bank 0 (MSB 0x00) */ 149 #define INV_ICM42600_REG_DEVICE_CONFIG 0x0011 150 #define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0) 151 152 #define INV_ICM42600_REG_DRIVE_CONFIG 0x0013 153 #define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3) 154 #define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \ 155 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate)) 156 #define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0) 157 #define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \ 158 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate)) 159 160 #define INV_ICM42600_REG_INT_CONFIG 0x0014 161 #define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5) 162 #define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4) 163 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3) 164 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00 165 #define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2) 166 #define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1) 167 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0) 168 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00 169 170 #define INV_ICM42600_REG_FIFO_CONFIG 0x0016 171 #define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6) 172 #define INV_ICM42600_FIFO_CONFIG_BYPASS \ 173 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0) 174 #define INV_ICM42600_FIFO_CONFIG_STREAM \ 175 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1) 176 #define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \ 177 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2) 178 179 /* all sensor data are 16 bits (2 registers wide) in big-endian */ 180 #define INV_ICM42600_REG_TEMP_DATA 0x001D 181 #define INV_ICM42600_REG_ACCEL_DATA_X 0x001F 182 #define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021 183 #define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023 184 #define INV_ICM42600_REG_GYRO_DATA_X 0x0025 185 #define INV_ICM42600_REG_GYRO_DATA_Y 0x0027 186 #define INV_ICM42600_REG_GYRO_DATA_Z 0x0029 187 #define INV_ICM42600_DATA_INVALID -32768 188 189 #define INV_ICM42600_REG_INT_STATUS 0x002D 190 #define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6) 191 #define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5) 192 #define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4) 193 #define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3) 194 #define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2) 195 #define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1) 196 #define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0) 197 198 /* 199 * FIFO access registers 200 * FIFO count is 16 bits (2 registers) big-endian 201 * FIFO data is a continuous read register to read FIFO content 202 */ 203 #define INV_ICM42600_REG_FIFO_COUNT 0x002E 204 #define INV_ICM42600_REG_FIFO_DATA 0x0030 205 206 #define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B 207 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6) 208 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5) 209 #define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3) 210 #define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2) 211 #define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1) 212 213 /* default configuration: all data big-endian and fifo count in bytes */ 214 #define INV_ICM42600_REG_INTF_CONFIG0 0x004C 215 #define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7) 216 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6) 217 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5) 218 #define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4) 219 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0) 220 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \ 221 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2) 222 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \ 223 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3) 224 225 #define INV_ICM42600_REG_INTF_CONFIG1 0x004D 226 #define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3) 227 228 #define INV_ICM42600_REG_PWR_MGMT0 0x004E 229 #define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5) 230 #define INV_ICM42600_PWR_MGMT0_IDLE BIT(4) 231 #define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \ 232 FIELD_PREP(GENMASK(3, 2), (_mode)) 233 #define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \ 234 FIELD_PREP(GENMASK(1, 0), (_mode)) 235 236 #define INV_ICM42600_REG_GYRO_CONFIG0 0x004F 237 #define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \ 238 FIELD_PREP(GENMASK(7, 5), (_fs)) 239 #define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \ 240 FIELD_PREP(GENMASK(3, 0), (_odr)) 241 242 #define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050 243 #define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \ 244 FIELD_PREP(GENMASK(7, 5), (_fs)) 245 #define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \ 246 FIELD_PREP(GENMASK(3, 0), (_odr)) 247 248 #define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052 249 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \ 250 FIELD_PREP(GENMASK(7, 4), (_f)) 251 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \ 252 FIELD_PREP(GENMASK(3, 0), (_f)) 253 254 #define INV_ICM42600_REG_TMST_CONFIG 0x0054 255 #define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0) 256 #define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4) 257 #define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3) 258 #define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2) 259 #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1) 260 #define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0) 261 262 #define INV_ICM42600_REG_FIFO_CONFIG1 0x005F 263 #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6) 264 #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5) 265 #define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3) 266 #define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2) 267 #define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1) 268 #define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0) 269 270 /* FIFO watermark is 16 bits (2 registers wide) in little-endian */ 271 #define INV_ICM42600_REG_FIFO_WATERMARK 0x0060 272 #define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \ 273 cpu_to_le16((_wm) & GENMASK(11, 0)) 274 /* FIFO is 2048 bytes, let 12 samples for reading latency */ 275 #define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16) 276 277 #define INV_ICM42600_REG_INT_CONFIG1 0x0064 278 #define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6) 279 #define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5) 280 #define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4) 281 282 #define INV_ICM42600_REG_INT_SOURCE0 0x0065 283 #define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6) 284 #define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5) 285 #define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4) 286 #define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3) 287 #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2) 288 #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1) 289 #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0) 290 291 #define INV_ICM42600_REG_WHOAMI 0x0075 292 #define INV_ICM42600_WHOAMI_ICM42600 0x40 293 #define INV_ICM42600_WHOAMI_ICM42602 0x41 294 #define INV_ICM42600_WHOAMI_ICM42605 0x42 295 #define INV_ICM42600_WHOAMI_ICM42622 0x46 296 297 /* User bank 1 (MSB 0x10) */ 298 #define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003 299 #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5) 300 #define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4) 301 #define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3) 302 #define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2) 303 #define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1) 304 #define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0) 305 306 /* Timestamp value is 20 bits (3 registers) in little-endian */ 307 #define INV_ICM42600_REG_TMSTVAL 0x1062 308 #define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0) 309 310 #define INV_ICM42600_REG_INTF_CONFIG4 0x107A 311 #define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6) 312 #define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1) 313 314 #define INV_ICM42600_REG_INTF_CONFIG6 0x107C 315 #define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0) 316 #define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4) 317 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3) 318 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2) 319 #define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1) 320 #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0) 321 322 /* User bank 4 (MSB 0x40) */ 323 #define INV_ICM42600_REG_INT_SOURCE8 0x404F 324 #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5) 325 #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4) 326 #define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3) 327 #define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2) 328 #define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1) 329 #define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0) 330 331 #define INV_ICM42600_REG_OFFSET_USER0 0x4077 332 #define INV_ICM42600_REG_OFFSET_USER1 0x4078 333 #define INV_ICM42600_REG_OFFSET_USER2 0x4079 334 #define INV_ICM42600_REG_OFFSET_USER3 0x407A 335 #define INV_ICM42600_REG_OFFSET_USER4 0x407B 336 #define INV_ICM42600_REG_OFFSET_USER5 0x407C 337 #define INV_ICM42600_REG_OFFSET_USER6 0x407D 338 #define INV_ICM42600_REG_OFFSET_USER7 0x407E 339 #define INV_ICM42600_REG_OFFSET_USER8 0x407F 340 341 /* Sleep times required by the driver */ 342 #define INV_ICM42600_POWER_UP_TIME_MS 100 343 #define INV_ICM42600_RESET_TIME_MS 1 344 #define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20 345 #define INV_ICM42600_GYRO_STARTUP_TIME_MS 60 346 #define INV_ICM42600_GYRO_STOP_TIME_MS 150 347 #define INV_ICM42600_TEMP_STARTUP_TIME_MS 14 348 #define INV_ICM42600_SUSPEND_DELAY_MS 2000 349 350 typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *); 351 352 extern const struct regmap_config inv_icm42600_regmap_config; 353 extern const struct dev_pm_ops inv_icm42600_pm_ops; 354 355 const struct iio_mount_matrix * 356 inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev, 357 const struct iio_chan_spec *chan); 358 359 uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); 360 361 int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st, 362 struct inv_icm42600_sensor_conf *conf, 363 unsigned int *sleep_ms); 364 365 int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st, 366 struct inv_icm42600_sensor_conf *conf, 367 unsigned int *sleep_ms); 368 369 int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable, 370 unsigned int *sleep_ms); 371 372 int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 373 unsigned int writeval, unsigned int *readval); 374 375 int inv_icm42600_core_probe(struct regmap *regmap, int chip, 376 inv_icm42600_bus_setup bus_setup); 377 378 struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st); 379 380 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st); 381 382 #endif 383