1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/spi/spi.h> 17 #include <linux/slab.h> 18 #include <linux/sysfs.h> 19 #include <linux/module.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/imu/adis.h> 25 26 #include <linux/debugfs.h> 27 28 #define ADIS16480_PAGE_SIZE 0x80 29 30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99 /* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 105 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 106 107 /* Each filter coefficent bank spans two pages */ 108 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 109 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 110 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 111 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 112 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 113 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 114 115 /* ADIS16480_REG_FNCTIO_CTRL */ 116 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 117 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 118 #define ADIS16480_DRDY_POL_MSK BIT(2) 119 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 120 #define ADIS16480_DRDY_EN_MSK BIT(3) 121 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 122 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 123 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 124 #define ADIS16480_SYNC_EN_MSK BIT(7) 125 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 126 #define ADIS16480_SYNC_MODE_MSK BIT(8) 127 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 128 129 struct adis16480_chip_info { 130 unsigned int num_channels; 131 const struct iio_chan_spec *channels; 132 unsigned int gyro_max_val; 133 unsigned int gyro_max_scale; 134 unsigned int accel_max_val; 135 unsigned int accel_max_scale; 136 unsigned int temp_scale; 137 unsigned int int_clk; 138 unsigned int max_dec_rate; 139 const unsigned int *filter_freqs; 140 bool has_pps_clk_mode; 141 }; 142 143 enum adis16480_int_pin { 144 ADIS16480_PIN_DIO1, 145 ADIS16480_PIN_DIO2, 146 ADIS16480_PIN_DIO3, 147 ADIS16480_PIN_DIO4 148 }; 149 150 enum adis16480_clock_mode { 151 ADIS16480_CLK_SYNC, 152 ADIS16480_CLK_PPS, 153 ADIS16480_CLK_INT 154 }; 155 156 struct adis16480 { 157 const struct adis16480_chip_info *chip_info; 158 159 struct adis adis; 160 struct clk *ext_clk; 161 enum adis16480_clock_mode clk_mode; 162 unsigned int clk_freq; 163 }; 164 165 static const char * const adis16480_int_pin_names[4] = { 166 [ADIS16480_PIN_DIO1] = "DIO1", 167 [ADIS16480_PIN_DIO2] = "DIO2", 168 [ADIS16480_PIN_DIO3] = "DIO3", 169 [ADIS16480_PIN_DIO4] = "DIO4", 170 }; 171 172 #ifdef CONFIG_DEBUG_FS 173 174 static ssize_t adis16480_show_firmware_revision(struct file *file, 175 char __user *userbuf, size_t count, loff_t *ppos) 176 { 177 struct adis16480 *adis16480 = file->private_data; 178 char buf[7]; 179 size_t len; 180 u16 rev; 181 int ret; 182 183 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 184 if (ret < 0) 185 return ret; 186 187 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 188 189 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 190 } 191 192 static const struct file_operations adis16480_firmware_revision_fops = { 193 .open = simple_open, 194 .read = adis16480_show_firmware_revision, 195 .llseek = default_llseek, 196 .owner = THIS_MODULE, 197 }; 198 199 static ssize_t adis16480_show_firmware_date(struct file *file, 200 char __user *userbuf, size_t count, loff_t *ppos) 201 { 202 struct adis16480 *adis16480 = file->private_data; 203 u16 md, year; 204 char buf[12]; 205 size_t len; 206 int ret; 207 208 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 209 if (ret < 0) 210 return ret; 211 212 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 213 if (ret < 0) 214 return ret; 215 216 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 217 md >> 8, md & 0xff, year); 218 219 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 220 } 221 222 static const struct file_operations adis16480_firmware_date_fops = { 223 .open = simple_open, 224 .read = adis16480_show_firmware_date, 225 .llseek = default_llseek, 226 .owner = THIS_MODULE, 227 }; 228 229 static int adis16480_show_serial_number(void *arg, u64 *val) 230 { 231 struct adis16480 *adis16480 = arg; 232 u16 serial; 233 int ret; 234 235 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 236 &serial); 237 if (ret < 0) 238 return ret; 239 240 *val = serial; 241 242 return 0; 243 } 244 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 245 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 246 247 static int adis16480_show_product_id(void *arg, u64 *val) 248 { 249 struct adis16480 *adis16480 = arg; 250 u16 prod_id; 251 int ret; 252 253 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 254 &prod_id); 255 if (ret < 0) 256 return ret; 257 258 *val = prod_id; 259 260 return 0; 261 } 262 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 263 adis16480_show_product_id, NULL, "%llu\n"); 264 265 static int adis16480_show_flash_count(void *arg, u64 *val) 266 { 267 struct adis16480 *adis16480 = arg; 268 u32 flash_count; 269 int ret; 270 271 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 272 &flash_count); 273 if (ret < 0) 274 return ret; 275 276 *val = flash_count; 277 278 return 0; 279 } 280 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 281 adis16480_show_flash_count, NULL, "%lld\n"); 282 283 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 284 { 285 struct adis16480 *adis16480 = iio_priv(indio_dev); 286 287 debugfs_create_file_unsafe("firmware_revision", 0400, 288 indio_dev->debugfs_dentry, adis16480, 289 &adis16480_firmware_revision_fops); 290 debugfs_create_file_unsafe("firmware_date", 0400, 291 indio_dev->debugfs_dentry, adis16480, 292 &adis16480_firmware_date_fops); 293 debugfs_create_file_unsafe("serial_number", 0400, 294 indio_dev->debugfs_dentry, adis16480, 295 &adis16480_serial_number_fops); 296 debugfs_create_file_unsafe("product_id", 0400, 297 indio_dev->debugfs_dentry, adis16480, 298 &adis16480_product_id_fops); 299 debugfs_create_file_unsafe("flash_count", 0400, 300 indio_dev->debugfs_dentry, adis16480, 301 &adis16480_flash_count_fops); 302 303 return 0; 304 } 305 306 #else 307 308 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 309 { 310 return 0; 311 } 312 313 #endif 314 315 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 316 { 317 struct adis16480 *st = iio_priv(indio_dev); 318 unsigned int t, reg; 319 320 t = val * 1000 + val2 / 1000; 321 if (t <= 0) 322 return -EINVAL; 323 324 /* 325 * When using PPS mode, the rate of data collection is equal to the 326 * product of the external clock frequency and the scale factor in the 327 * SYNC_SCALE register. 328 * When using sync mode, or internal clock, the output data rate is 329 * equal with the clock frequency divided by DEC_RATE + 1. 330 */ 331 if (st->clk_mode == ADIS16480_CLK_PPS) { 332 t = t / st->clk_freq; 333 reg = ADIS16495_REG_SYNC_SCALE; 334 } else { 335 t = st->clk_freq / t; 336 reg = ADIS16480_REG_DEC_RATE; 337 } 338 339 if (t > st->chip_info->max_dec_rate) 340 t = st->chip_info->max_dec_rate; 341 342 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 343 t--; 344 345 return adis_write_reg_16(&st->adis, reg, t); 346 } 347 348 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 349 { 350 struct adis16480 *st = iio_priv(indio_dev); 351 uint16_t t; 352 int ret; 353 unsigned freq; 354 unsigned int reg; 355 356 if (st->clk_mode == ADIS16480_CLK_PPS) 357 reg = ADIS16495_REG_SYNC_SCALE; 358 else 359 reg = ADIS16480_REG_DEC_RATE; 360 361 ret = adis_read_reg_16(&st->adis, reg, &t); 362 if (ret < 0) 363 return ret; 364 365 /* 366 * When using PPS mode, the rate of data collection is equal to the 367 * product of the external clock frequency and the scale factor in the 368 * SYNC_SCALE register. 369 * When using sync mode, or internal clock, the output data rate is 370 * equal with the clock frequency divided by DEC_RATE + 1. 371 */ 372 if (st->clk_mode == ADIS16480_CLK_PPS) 373 freq = st->clk_freq * t; 374 else 375 freq = st->clk_freq / (t + 1); 376 377 *val = freq / 1000; 378 *val2 = (freq % 1000) * 1000; 379 380 return IIO_VAL_INT_PLUS_MICRO; 381 } 382 383 enum { 384 ADIS16480_SCAN_GYRO_X, 385 ADIS16480_SCAN_GYRO_Y, 386 ADIS16480_SCAN_GYRO_Z, 387 ADIS16480_SCAN_ACCEL_X, 388 ADIS16480_SCAN_ACCEL_Y, 389 ADIS16480_SCAN_ACCEL_Z, 390 ADIS16480_SCAN_MAGN_X, 391 ADIS16480_SCAN_MAGN_Y, 392 ADIS16480_SCAN_MAGN_Z, 393 ADIS16480_SCAN_BARO, 394 ADIS16480_SCAN_TEMP, 395 }; 396 397 static const unsigned int adis16480_calibbias_regs[] = { 398 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 399 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 400 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 401 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 402 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 403 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 404 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 405 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 406 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 407 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 408 }; 409 410 static const unsigned int adis16480_calibscale_regs[] = { 411 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 412 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 413 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 414 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 415 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 416 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 417 }; 418 419 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 420 const struct iio_chan_spec *chan, int bias) 421 { 422 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 423 struct adis16480 *st = iio_priv(indio_dev); 424 425 switch (chan->type) { 426 case IIO_MAGN: 427 case IIO_PRESSURE: 428 if (bias < -0x8000 || bias >= 0x8000) 429 return -EINVAL; 430 return adis_write_reg_16(&st->adis, reg, bias); 431 case IIO_ANGL_VEL: 432 case IIO_ACCEL: 433 return adis_write_reg_32(&st->adis, reg, bias); 434 default: 435 break; 436 } 437 438 return -EINVAL; 439 } 440 441 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 442 const struct iio_chan_spec *chan, int *bias) 443 { 444 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 445 struct adis16480 *st = iio_priv(indio_dev); 446 uint16_t val16; 447 uint32_t val32; 448 int ret; 449 450 switch (chan->type) { 451 case IIO_MAGN: 452 case IIO_PRESSURE: 453 ret = adis_read_reg_16(&st->adis, reg, &val16); 454 *bias = sign_extend32(val16, 15); 455 break; 456 case IIO_ANGL_VEL: 457 case IIO_ACCEL: 458 ret = adis_read_reg_32(&st->adis, reg, &val32); 459 *bias = sign_extend32(val32, 31); 460 break; 461 default: 462 ret = -EINVAL; 463 } 464 465 if (ret < 0) 466 return ret; 467 468 return IIO_VAL_INT; 469 } 470 471 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 472 const struct iio_chan_spec *chan, int scale) 473 { 474 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 475 struct adis16480 *st = iio_priv(indio_dev); 476 477 if (scale < -0x8000 || scale >= 0x8000) 478 return -EINVAL; 479 480 return adis_write_reg_16(&st->adis, reg, scale); 481 } 482 483 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 484 const struct iio_chan_spec *chan, int *scale) 485 { 486 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 487 struct adis16480 *st = iio_priv(indio_dev); 488 uint16_t val16; 489 int ret; 490 491 ret = adis_read_reg_16(&st->adis, reg, &val16); 492 if (ret < 0) 493 return ret; 494 495 *scale = sign_extend32(val16, 15); 496 return IIO_VAL_INT; 497 } 498 499 static const unsigned int adis16480_def_filter_freqs[] = { 500 310, 501 55, 502 275, 503 63, 504 }; 505 506 static const unsigned int adis16495_def_filter_freqs[] = { 507 300, 508 100, 509 300, 510 100, 511 }; 512 513 static const unsigned int ad16480_filter_data[][2] = { 514 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 515 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 516 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 517 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 518 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 519 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 520 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 521 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 522 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 523 }; 524 525 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 526 const struct iio_chan_spec *chan, int *freq) 527 { 528 struct adis16480 *st = iio_priv(indio_dev); 529 unsigned int enable_mask, offset, reg; 530 uint16_t val; 531 int ret; 532 533 reg = ad16480_filter_data[chan->scan_index][0]; 534 offset = ad16480_filter_data[chan->scan_index][1]; 535 enable_mask = BIT(offset + 2); 536 537 ret = adis_read_reg_16(&st->adis, reg, &val); 538 if (ret < 0) 539 return ret; 540 541 if (!(val & enable_mask)) 542 *freq = 0; 543 else 544 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 545 546 return IIO_VAL_INT; 547 } 548 549 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 550 const struct iio_chan_spec *chan, unsigned int freq) 551 { 552 struct adis16480 *st = iio_priv(indio_dev); 553 unsigned int enable_mask, offset, reg; 554 unsigned int diff, best_diff; 555 unsigned int i, best_freq; 556 uint16_t val; 557 int ret; 558 559 reg = ad16480_filter_data[chan->scan_index][0]; 560 offset = ad16480_filter_data[chan->scan_index][1]; 561 enable_mask = BIT(offset + 2); 562 563 ret = adis_read_reg_16(&st->adis, reg, &val); 564 if (ret < 0) 565 return ret; 566 567 if (freq == 0) { 568 val &= ~enable_mask; 569 } else { 570 best_freq = 0; 571 best_diff = st->chip_info->filter_freqs[0]; 572 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 573 if (st->chip_info->filter_freqs[i] >= freq) { 574 diff = st->chip_info->filter_freqs[i] - freq; 575 if (diff < best_diff) { 576 best_diff = diff; 577 best_freq = i; 578 } 579 } 580 } 581 582 val &= ~(0x3 << offset); 583 val |= best_freq << offset; 584 val |= enable_mask; 585 } 586 587 return adis_write_reg_16(&st->adis, reg, val); 588 } 589 590 static int adis16480_read_raw(struct iio_dev *indio_dev, 591 const struct iio_chan_spec *chan, int *val, int *val2, long info) 592 { 593 struct adis16480 *st = iio_priv(indio_dev); 594 unsigned int temp; 595 596 switch (info) { 597 case IIO_CHAN_INFO_RAW: 598 return adis_single_conversion(indio_dev, chan, 0, val); 599 case IIO_CHAN_INFO_SCALE: 600 switch (chan->type) { 601 case IIO_ANGL_VEL: 602 *val = st->chip_info->gyro_max_scale; 603 *val2 = st->chip_info->gyro_max_val; 604 return IIO_VAL_FRACTIONAL; 605 case IIO_ACCEL: 606 *val = st->chip_info->accel_max_scale; 607 *val2 = st->chip_info->accel_max_val; 608 return IIO_VAL_FRACTIONAL; 609 case IIO_MAGN: 610 *val = 0; 611 *val2 = 100; /* 0.0001 gauss */ 612 return IIO_VAL_INT_PLUS_MICRO; 613 case IIO_TEMP: 614 /* 615 * +85 degrees Celsius = temp_max_scale 616 * +25 degrees Celsius = 0 617 * LSB, 25 degrees Celsius = 60 / temp_max_scale 618 */ 619 *val = st->chip_info->temp_scale / 1000; 620 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 621 return IIO_VAL_INT_PLUS_MICRO; 622 case IIO_PRESSURE: 623 *val = 0; 624 *val2 = 4000; /* 40ubar = 0.004 kPa */ 625 return IIO_VAL_INT_PLUS_MICRO; 626 default: 627 return -EINVAL; 628 } 629 case IIO_CHAN_INFO_OFFSET: 630 /* Only the temperature channel has a offset */ 631 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 632 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 633 return IIO_VAL_INT; 634 case IIO_CHAN_INFO_CALIBBIAS: 635 return adis16480_get_calibbias(indio_dev, chan, val); 636 case IIO_CHAN_INFO_CALIBSCALE: 637 return adis16480_get_calibscale(indio_dev, chan, val); 638 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 639 return adis16480_get_filter_freq(indio_dev, chan, val); 640 case IIO_CHAN_INFO_SAMP_FREQ: 641 return adis16480_get_freq(indio_dev, val, val2); 642 default: 643 return -EINVAL; 644 } 645 } 646 647 static int adis16480_write_raw(struct iio_dev *indio_dev, 648 const struct iio_chan_spec *chan, int val, int val2, long info) 649 { 650 switch (info) { 651 case IIO_CHAN_INFO_CALIBBIAS: 652 return adis16480_set_calibbias(indio_dev, chan, val); 653 case IIO_CHAN_INFO_CALIBSCALE: 654 return adis16480_set_calibscale(indio_dev, chan, val); 655 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 656 return adis16480_set_filter_freq(indio_dev, chan, val); 657 case IIO_CHAN_INFO_SAMP_FREQ: 658 return adis16480_set_freq(indio_dev, val, val2); 659 660 default: 661 return -EINVAL; 662 } 663 } 664 665 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 666 { \ 667 .type = (_type), \ 668 .modified = 1, \ 669 .channel2 = (_mod), \ 670 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 671 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 672 _info_sep, \ 673 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 674 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 675 .address = (_address), \ 676 .scan_index = (_si), \ 677 .scan_type = { \ 678 .sign = 's', \ 679 .realbits = (_bits), \ 680 .storagebits = (_bits), \ 681 .endianness = IIO_BE, \ 682 }, \ 683 } 684 685 #define ADIS16480_GYRO_CHANNEL(_mod) \ 686 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 687 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 688 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 689 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 690 32) 691 692 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 693 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 694 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 695 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 696 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 697 32) 698 699 #define ADIS16480_MAGN_CHANNEL(_mod) \ 700 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 701 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 702 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 703 16) 704 705 #define ADIS16480_PRESSURE_CHANNEL() \ 706 { \ 707 .type = IIO_PRESSURE, \ 708 .indexed = 1, \ 709 .channel = 0, \ 710 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 711 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 712 BIT(IIO_CHAN_INFO_SCALE), \ 713 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 714 .address = ADIS16480_REG_BAROM_OUT, \ 715 .scan_index = ADIS16480_SCAN_BARO, \ 716 .scan_type = { \ 717 .sign = 's', \ 718 .realbits = 32, \ 719 .storagebits = 32, \ 720 .endianness = IIO_BE, \ 721 }, \ 722 } 723 724 #define ADIS16480_TEMP_CHANNEL() { \ 725 .type = IIO_TEMP, \ 726 .indexed = 1, \ 727 .channel = 0, \ 728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 729 BIT(IIO_CHAN_INFO_SCALE) | \ 730 BIT(IIO_CHAN_INFO_OFFSET), \ 731 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 732 .address = ADIS16480_REG_TEMP_OUT, \ 733 .scan_index = ADIS16480_SCAN_TEMP, \ 734 .scan_type = { \ 735 .sign = 's', \ 736 .realbits = 16, \ 737 .storagebits = 16, \ 738 .endianness = IIO_BE, \ 739 }, \ 740 } 741 742 static const struct iio_chan_spec adis16480_channels[] = { 743 ADIS16480_GYRO_CHANNEL(X), 744 ADIS16480_GYRO_CHANNEL(Y), 745 ADIS16480_GYRO_CHANNEL(Z), 746 ADIS16480_ACCEL_CHANNEL(X), 747 ADIS16480_ACCEL_CHANNEL(Y), 748 ADIS16480_ACCEL_CHANNEL(Z), 749 ADIS16480_MAGN_CHANNEL(X), 750 ADIS16480_MAGN_CHANNEL(Y), 751 ADIS16480_MAGN_CHANNEL(Z), 752 ADIS16480_PRESSURE_CHANNEL(), 753 ADIS16480_TEMP_CHANNEL(), 754 IIO_CHAN_SOFT_TIMESTAMP(11) 755 }; 756 757 static const struct iio_chan_spec adis16485_channels[] = { 758 ADIS16480_GYRO_CHANNEL(X), 759 ADIS16480_GYRO_CHANNEL(Y), 760 ADIS16480_GYRO_CHANNEL(Z), 761 ADIS16480_ACCEL_CHANNEL(X), 762 ADIS16480_ACCEL_CHANNEL(Y), 763 ADIS16480_ACCEL_CHANNEL(Z), 764 ADIS16480_TEMP_CHANNEL(), 765 IIO_CHAN_SOFT_TIMESTAMP(7) 766 }; 767 768 enum adis16480_variant { 769 ADIS16375, 770 ADIS16480, 771 ADIS16485, 772 ADIS16488, 773 ADIS16495_1, 774 ADIS16495_2, 775 ADIS16495_3, 776 ADIS16497_1, 777 ADIS16497_2, 778 ADIS16497_3, 779 }; 780 781 static const struct adis16480_chip_info adis16480_chip_info[] = { 782 [ADIS16375] = { 783 .channels = adis16485_channels, 784 .num_channels = ARRAY_SIZE(adis16485_channels), 785 /* 786 * storing the value in rad/degree and the scale in degree 787 * gives us the result in rad and better precession than 788 * storing the scale directly in rad. 789 */ 790 .gyro_max_val = IIO_RAD_TO_DEGREE(22887), 791 .gyro_max_scale = 300, 792 .accel_max_val = IIO_M_S_2_TO_G(21973), 793 .accel_max_scale = 18, 794 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 795 .int_clk = 2460000, 796 .max_dec_rate = 2048, 797 .filter_freqs = adis16480_def_filter_freqs, 798 }, 799 [ADIS16480] = { 800 .channels = adis16480_channels, 801 .num_channels = ARRAY_SIZE(adis16480_channels), 802 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 803 .gyro_max_scale = 450, 804 .accel_max_val = IIO_M_S_2_TO_G(12500), 805 .accel_max_scale = 10, 806 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 807 .int_clk = 2460000, 808 .max_dec_rate = 2048, 809 .filter_freqs = adis16480_def_filter_freqs, 810 }, 811 [ADIS16485] = { 812 .channels = adis16485_channels, 813 .num_channels = ARRAY_SIZE(adis16485_channels), 814 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 815 .gyro_max_scale = 450, 816 .accel_max_val = IIO_M_S_2_TO_G(20000), 817 .accel_max_scale = 5, 818 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 819 .int_clk = 2460000, 820 .max_dec_rate = 2048, 821 .filter_freqs = adis16480_def_filter_freqs, 822 }, 823 [ADIS16488] = { 824 .channels = adis16480_channels, 825 .num_channels = ARRAY_SIZE(adis16480_channels), 826 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 827 .gyro_max_scale = 450, 828 .accel_max_val = IIO_M_S_2_TO_G(22500), 829 .accel_max_scale = 18, 830 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 831 .int_clk = 2460000, 832 .max_dec_rate = 2048, 833 .filter_freqs = adis16480_def_filter_freqs, 834 }, 835 [ADIS16495_1] = { 836 .channels = adis16485_channels, 837 .num_channels = ARRAY_SIZE(adis16485_channels), 838 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 839 .gyro_max_scale = 125, 840 .accel_max_val = IIO_M_S_2_TO_G(32000), 841 .accel_max_scale = 8, 842 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 843 .int_clk = 4250000, 844 .max_dec_rate = 4250, 845 .filter_freqs = adis16495_def_filter_freqs, 846 .has_pps_clk_mode = true, 847 }, 848 [ADIS16495_2] = { 849 .channels = adis16485_channels, 850 .num_channels = ARRAY_SIZE(adis16485_channels), 851 .gyro_max_val = IIO_RAD_TO_DEGREE(18000), 852 .gyro_max_scale = 450, 853 .accel_max_val = IIO_M_S_2_TO_G(32000), 854 .accel_max_scale = 8, 855 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 856 .int_clk = 4250000, 857 .max_dec_rate = 4250, 858 .filter_freqs = adis16495_def_filter_freqs, 859 .has_pps_clk_mode = true, 860 }, 861 [ADIS16495_3] = { 862 .channels = adis16485_channels, 863 .num_channels = ARRAY_SIZE(adis16485_channels), 864 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 865 .gyro_max_scale = 2000, 866 .accel_max_val = IIO_M_S_2_TO_G(32000), 867 .accel_max_scale = 8, 868 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 869 .int_clk = 4250000, 870 .max_dec_rate = 4250, 871 .filter_freqs = adis16495_def_filter_freqs, 872 .has_pps_clk_mode = true, 873 }, 874 [ADIS16497_1] = { 875 .channels = adis16485_channels, 876 .num_channels = ARRAY_SIZE(adis16485_channels), 877 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 878 .gyro_max_scale = 125, 879 .accel_max_val = IIO_M_S_2_TO_G(32000), 880 .accel_max_scale = 40, 881 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 882 .int_clk = 4250000, 883 .max_dec_rate = 4250, 884 .filter_freqs = adis16495_def_filter_freqs, 885 .has_pps_clk_mode = true, 886 }, 887 [ADIS16497_2] = { 888 .channels = adis16485_channels, 889 .num_channels = ARRAY_SIZE(adis16485_channels), 890 .gyro_max_val = IIO_RAD_TO_DEGREE(18000), 891 .gyro_max_scale = 450, 892 .accel_max_val = IIO_M_S_2_TO_G(32000), 893 .accel_max_scale = 40, 894 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 895 .int_clk = 4250000, 896 .max_dec_rate = 4250, 897 .filter_freqs = adis16495_def_filter_freqs, 898 .has_pps_clk_mode = true, 899 }, 900 [ADIS16497_3] = { 901 .channels = adis16485_channels, 902 .num_channels = ARRAY_SIZE(adis16485_channels), 903 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 904 .gyro_max_scale = 2000, 905 .accel_max_val = IIO_M_S_2_TO_G(32000), 906 .accel_max_scale = 40, 907 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 908 .int_clk = 4250000, 909 .max_dec_rate = 4250, 910 .filter_freqs = adis16495_def_filter_freqs, 911 .has_pps_clk_mode = true, 912 }, 913 }; 914 915 static const struct iio_info adis16480_info = { 916 .read_raw = &adis16480_read_raw, 917 .write_raw = &adis16480_write_raw, 918 .update_scan_mode = adis_update_scan_mode, 919 }; 920 921 static int adis16480_stop_device(struct iio_dev *indio_dev) 922 { 923 struct adis16480 *st = iio_priv(indio_dev); 924 int ret; 925 926 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 927 if (ret) 928 dev_err(&indio_dev->dev, 929 "Could not power down device: %d\n", ret); 930 931 return ret; 932 } 933 934 static int adis16480_enable_irq(struct adis *adis, bool enable) 935 { 936 uint16_t val; 937 int ret; 938 939 ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 940 if (ret < 0) 941 return ret; 942 943 val &= ~ADIS16480_DRDY_EN_MSK; 944 val |= ADIS16480_DRDY_EN(enable); 945 946 return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 947 } 948 949 static int adis16480_initial_setup(struct iio_dev *indio_dev) 950 { 951 struct adis16480 *st = iio_priv(indio_dev); 952 uint16_t prod_id; 953 unsigned int device_id; 954 int ret; 955 956 adis_reset(&st->adis); 957 msleep(70); 958 959 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1)); 960 if (ret) 961 return ret; 962 msleep(30); 963 964 ret = adis_check_status(&st->adis); 965 if (ret) 966 return ret; 967 968 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id); 969 if (ret) 970 return ret; 971 972 ret = sscanf(indio_dev->name, "adis%u\n", &device_id); 973 if (ret != 1) 974 return -EINVAL; 975 976 if (prod_id != device_id) 977 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.", 978 device_id, prod_id); 979 980 return 0; 981 } 982 983 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 984 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 985 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 986 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 987 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 988 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 989 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 990 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 991 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 992 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 993 994 static const char * const adis16480_status_error_msgs[] = { 995 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 996 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 997 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 998 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 999 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 1000 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 1001 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 1002 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 1003 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 1004 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 1005 }; 1006 1007 static const struct adis_data adis16480_data = { 1008 .diag_stat_reg = ADIS16480_REG_DIAG_STS, 1009 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, 1010 .has_paging = true, 1011 1012 .read_delay = 5, 1013 .write_delay = 5, 1014 1015 .status_error_msgs = adis16480_status_error_msgs, 1016 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | 1017 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | 1018 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | 1019 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | 1020 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | 1021 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | 1022 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | 1023 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | 1024 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | 1025 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), 1026 1027 .enable_irq = adis16480_enable_irq, 1028 }; 1029 1030 static int adis16480_config_irq_pin(struct device_node *of_node, 1031 struct adis16480 *st) 1032 { 1033 struct irq_data *desc; 1034 enum adis16480_int_pin pin; 1035 unsigned int irq_type; 1036 uint16_t val; 1037 int i, irq = 0; 1038 1039 desc = irq_get_irq_data(st->adis.spi->irq); 1040 if (!desc) { 1041 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1042 return -EINVAL; 1043 } 1044 1045 /* Disable data ready since the default after reset is on */ 1046 val = ADIS16480_DRDY_EN(0); 1047 1048 /* 1049 * Get the interrupt from the devicetre by reading the interrupt-names 1050 * property. If it is not specified, use DIO1 pin as default. 1051 * According to the datasheet, the factory default assigns DIO2 as data 1052 * ready signal. However, in the previous versions of the driver, DIO1 1053 * pin was used. So, we should leave it as is since some devices might 1054 * be expecting the interrupt on the wrong physical pin. 1055 */ 1056 pin = ADIS16480_PIN_DIO1; 1057 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1058 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1059 if (irq > 0) { 1060 pin = i; 1061 break; 1062 } 1063 } 1064 1065 val |= ADIS16480_DRDY_SEL(pin); 1066 1067 /* 1068 * Get the interrupt line behaviour. The data ready polarity can be 1069 * configured as positive or negative, corresponding to 1070 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. 1071 */ 1072 irq_type = irqd_get_trigger_type(desc); 1073 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ 1074 val |= ADIS16480_DRDY_POL(1); 1075 } else if (irq_type == IRQF_TRIGGER_FALLING) { 1076 val |= ADIS16480_DRDY_POL(0); 1077 } else { 1078 dev_err(&st->adis.spi->dev, 1079 "Invalid interrupt type 0x%x specified\n", irq_type); 1080 return -EINVAL; 1081 } 1082 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1083 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1084 } 1085 1086 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1087 struct device_node *of_node) 1088 { 1089 const char *ext_clk_pin; 1090 enum adis16480_int_pin pin; 1091 int i; 1092 1093 pin = ADIS16480_PIN_DIO2; 1094 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1095 goto clk_input_not_found; 1096 1097 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1098 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1099 return i; 1100 } 1101 1102 clk_input_not_found: 1103 dev_info(&st->adis.spi->dev, 1104 "clk input line not specified, using DIO2\n"); 1105 return pin; 1106 } 1107 1108 static int adis16480_ext_clk_config(struct adis16480 *st, 1109 struct device_node *of_node, 1110 bool enable) 1111 { 1112 unsigned int mode, mask; 1113 enum adis16480_int_pin pin; 1114 uint16_t val; 1115 int ret; 1116 1117 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1118 if (ret < 0) 1119 return ret; 1120 1121 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1122 /* 1123 * Each DIOx pin supports only one function at a time. When a single pin 1124 * has two assignments, the enable bit for a lower priority function 1125 * automatically resets to zero (disabling the lower priority function). 1126 */ 1127 if (pin == ADIS16480_DRDY_SEL(val)) 1128 dev_warn(&st->adis.spi->dev, 1129 "DIO%x pin supports only one function at a time\n", 1130 pin + 1); 1131 1132 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1133 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1134 /* Only ADIS1649x devices support pps ext clock mode */ 1135 if (st->chip_info->has_pps_clk_mode) { 1136 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1137 mask |= ADIS16480_SYNC_MODE_MSK; 1138 } 1139 1140 val &= ~mask; 1141 val |= mode; 1142 1143 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1144 if (ret < 0) 1145 return ret; 1146 1147 return clk_prepare_enable(st->ext_clk); 1148 } 1149 1150 static int adis16480_get_ext_clocks(struct adis16480 *st) 1151 { 1152 st->clk_mode = ADIS16480_CLK_INT; 1153 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1154 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1155 st->clk_mode = ADIS16480_CLK_SYNC; 1156 return 0; 1157 } 1158 1159 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1160 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1161 return PTR_ERR(st->ext_clk); 1162 } 1163 1164 if (st->chip_info->has_pps_clk_mode) { 1165 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1166 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1167 st->clk_mode = ADIS16480_CLK_PPS; 1168 return 0; 1169 } 1170 1171 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1172 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1173 return PTR_ERR(st->ext_clk); 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int adis16480_probe(struct spi_device *spi) 1181 { 1182 const struct spi_device_id *id = spi_get_device_id(spi); 1183 struct iio_dev *indio_dev; 1184 struct adis16480 *st; 1185 int ret; 1186 1187 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1188 if (indio_dev == NULL) 1189 return -ENOMEM; 1190 1191 spi_set_drvdata(spi, indio_dev); 1192 1193 st = iio_priv(indio_dev); 1194 1195 st->chip_info = &adis16480_chip_info[id->driver_data]; 1196 indio_dev->dev.parent = &spi->dev; 1197 indio_dev->name = spi_get_device_id(spi)->name; 1198 indio_dev->channels = st->chip_info->channels; 1199 indio_dev->num_channels = st->chip_info->num_channels; 1200 indio_dev->info = &adis16480_info; 1201 indio_dev->modes = INDIO_DIRECT_MODE; 1202 1203 ret = adis_init(&st->adis, indio_dev, spi, &adis16480_data); 1204 if (ret) 1205 return ret; 1206 1207 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1208 if (ret) 1209 return ret; 1210 1211 ret = adis16480_get_ext_clocks(st); 1212 if (ret) 1213 return ret; 1214 1215 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1216 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1217 if (ret) 1218 return ret; 1219 1220 st->clk_freq = clk_get_rate(st->ext_clk); 1221 st->clk_freq *= 1000; /* micro */ 1222 } else { 1223 st->clk_freq = st->chip_info->int_clk; 1224 } 1225 1226 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1227 if (ret) 1228 goto error_clk_disable_unprepare; 1229 1230 ret = adis16480_initial_setup(indio_dev); 1231 if (ret) 1232 goto error_cleanup_buffer; 1233 1234 ret = iio_device_register(indio_dev); 1235 if (ret) 1236 goto error_stop_device; 1237 1238 adis16480_debugfs_init(indio_dev); 1239 1240 return 0; 1241 1242 error_stop_device: 1243 adis16480_stop_device(indio_dev); 1244 error_cleanup_buffer: 1245 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1246 error_clk_disable_unprepare: 1247 clk_disable_unprepare(st->ext_clk); 1248 return ret; 1249 } 1250 1251 static int adis16480_remove(struct spi_device *spi) 1252 { 1253 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1254 struct adis16480 *st = iio_priv(indio_dev); 1255 1256 iio_device_unregister(indio_dev); 1257 adis16480_stop_device(indio_dev); 1258 1259 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1260 clk_disable_unprepare(st->ext_clk); 1261 1262 return 0; 1263 } 1264 1265 static const struct spi_device_id adis16480_ids[] = { 1266 { "adis16375", ADIS16375 }, 1267 { "adis16480", ADIS16480 }, 1268 { "adis16485", ADIS16485 }, 1269 { "adis16488", ADIS16488 }, 1270 { "adis16495-1", ADIS16495_1 }, 1271 { "adis16495-2", ADIS16495_2 }, 1272 { "adis16495-3", ADIS16495_3 }, 1273 { "adis16497-1", ADIS16497_1 }, 1274 { "adis16497-2", ADIS16497_2 }, 1275 { "adis16497-3", ADIS16497_3 }, 1276 { } 1277 }; 1278 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1279 1280 static const struct of_device_id adis16480_of_match[] = { 1281 { .compatible = "adi,adis16375" }, 1282 { .compatible = "adi,adis16480" }, 1283 { .compatible = "adi,adis16485" }, 1284 { .compatible = "adi,adis16488" }, 1285 { .compatible = "adi,adis16495-1" }, 1286 { .compatible = "adi,adis16495-2" }, 1287 { .compatible = "adi,adis16495-3" }, 1288 { .compatible = "adi,adis16497-1" }, 1289 { .compatible = "adi,adis16497-2" }, 1290 { .compatible = "adi,adis16497-3" }, 1291 { }, 1292 }; 1293 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1294 1295 static struct spi_driver adis16480_driver = { 1296 .driver = { 1297 .name = "adis16480", 1298 .of_match_table = adis16480_of_match, 1299 }, 1300 .id_table = adis16480_ids, 1301 .probe = adis16480_probe, 1302 .remove = adis16480_remove, 1303 }; 1304 module_spi_driver(adis16480_driver); 1305 1306 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1307 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1308 MODULE_LICENSE("GPL v2"); 1309