1 /* 2 * ADIS16480 and similar IMUs driver 3 * 4 * Copyright 2012 Analog Devices Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/bitfield.h> 14 #include <linux/of_irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/delay.h> 17 #include <linux/mutex.h> 18 #include <linux/device.h> 19 #include <linux/kernel.h> 20 #include <linux/spi/spi.h> 21 #include <linux/slab.h> 22 #include <linux/sysfs.h> 23 #include <linux/module.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/imu/adis.h> 29 30 #include <linux/debugfs.h> 31 32 #define ADIS16480_PAGE_SIZE 0x80 33 34 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 35 36 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 37 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 38 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 39 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 40 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 41 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 42 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 43 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 44 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 45 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 46 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 47 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 48 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 49 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 50 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 51 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 52 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 53 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 54 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 55 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 56 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 57 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 58 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 59 60 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 61 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 62 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 63 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 64 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 65 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 66 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 67 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 68 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 69 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 70 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 71 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 72 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 73 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 74 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 75 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 76 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 77 78 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 79 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 80 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 81 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 82 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 83 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 84 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 85 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 86 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 87 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 88 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 89 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 90 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 91 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 92 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 93 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 94 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 95 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 96 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 97 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 98 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 99 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 100 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 101 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 102 103 /* 104 * External clock scaling in PPS mode. 105 * Available only for ADIS1649x devices 106 */ 107 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 108 109 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 110 111 /* Each filter coefficent bank spans two pages */ 112 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 113 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 114 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 115 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 116 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 117 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 118 119 /* ADIS16480_REG_FNCTIO_CTRL */ 120 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 121 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 122 #define ADIS16480_DRDY_POL_MSK BIT(2) 123 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 124 #define ADIS16480_DRDY_EN_MSK BIT(3) 125 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 126 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 127 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 128 #define ADIS16480_SYNC_EN_MSK BIT(7) 129 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 130 #define ADIS16480_SYNC_MODE_MSK BIT(8) 131 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 132 133 struct adis16480_chip_info { 134 unsigned int num_channels; 135 const struct iio_chan_spec *channels; 136 unsigned int gyro_max_val; 137 unsigned int gyro_max_scale; 138 unsigned int accel_max_val; 139 unsigned int accel_max_scale; 140 unsigned int temp_scale; 141 unsigned int int_clk; 142 unsigned int max_dec_rate; 143 const unsigned int *filter_freqs; 144 bool has_pps_clk_mode; 145 }; 146 147 enum adis16480_int_pin { 148 ADIS16480_PIN_DIO1, 149 ADIS16480_PIN_DIO2, 150 ADIS16480_PIN_DIO3, 151 ADIS16480_PIN_DIO4 152 }; 153 154 enum adis16480_clock_mode { 155 ADIS16480_CLK_SYNC, 156 ADIS16480_CLK_PPS, 157 ADIS16480_CLK_INT 158 }; 159 160 struct adis16480 { 161 const struct adis16480_chip_info *chip_info; 162 163 struct adis adis; 164 struct clk *ext_clk; 165 enum adis16480_clock_mode clk_mode; 166 unsigned int clk_freq; 167 }; 168 169 static const char * const adis16480_int_pin_names[4] = { 170 [ADIS16480_PIN_DIO1] = "DIO1", 171 [ADIS16480_PIN_DIO2] = "DIO2", 172 [ADIS16480_PIN_DIO3] = "DIO3", 173 [ADIS16480_PIN_DIO4] = "DIO4", 174 }; 175 176 #ifdef CONFIG_DEBUG_FS 177 178 static ssize_t adis16480_show_firmware_revision(struct file *file, 179 char __user *userbuf, size_t count, loff_t *ppos) 180 { 181 struct adis16480 *adis16480 = file->private_data; 182 char buf[7]; 183 size_t len; 184 u16 rev; 185 int ret; 186 187 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 188 if (ret < 0) 189 return ret; 190 191 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 192 193 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 194 } 195 196 static const struct file_operations adis16480_firmware_revision_fops = { 197 .open = simple_open, 198 .read = adis16480_show_firmware_revision, 199 .llseek = default_llseek, 200 .owner = THIS_MODULE, 201 }; 202 203 static ssize_t adis16480_show_firmware_date(struct file *file, 204 char __user *userbuf, size_t count, loff_t *ppos) 205 { 206 struct adis16480 *adis16480 = file->private_data; 207 u16 md, year; 208 char buf[12]; 209 size_t len; 210 int ret; 211 212 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 213 if (ret < 0) 214 return ret; 215 216 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 217 if (ret < 0) 218 return ret; 219 220 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 221 md >> 8, md & 0xff, year); 222 223 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 224 } 225 226 static const struct file_operations adis16480_firmware_date_fops = { 227 .open = simple_open, 228 .read = adis16480_show_firmware_date, 229 .llseek = default_llseek, 230 .owner = THIS_MODULE, 231 }; 232 233 static int adis16480_show_serial_number(void *arg, u64 *val) 234 { 235 struct adis16480 *adis16480 = arg; 236 u16 serial; 237 int ret; 238 239 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 240 &serial); 241 if (ret < 0) 242 return ret; 243 244 *val = serial; 245 246 return 0; 247 } 248 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 249 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 250 251 static int adis16480_show_product_id(void *arg, u64 *val) 252 { 253 struct adis16480 *adis16480 = arg; 254 u16 prod_id; 255 int ret; 256 257 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 258 &prod_id); 259 if (ret < 0) 260 return ret; 261 262 *val = prod_id; 263 264 return 0; 265 } 266 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 267 adis16480_show_product_id, NULL, "%llu\n"); 268 269 static int adis16480_show_flash_count(void *arg, u64 *val) 270 { 271 struct adis16480 *adis16480 = arg; 272 u32 flash_count; 273 int ret; 274 275 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 276 &flash_count); 277 if (ret < 0) 278 return ret; 279 280 *val = flash_count; 281 282 return 0; 283 } 284 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 285 adis16480_show_flash_count, NULL, "%lld\n"); 286 287 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 288 { 289 struct adis16480 *adis16480 = iio_priv(indio_dev); 290 291 debugfs_create_file_unsafe("firmware_revision", 0400, 292 indio_dev->debugfs_dentry, adis16480, 293 &adis16480_firmware_revision_fops); 294 debugfs_create_file_unsafe("firmware_date", 0400, 295 indio_dev->debugfs_dentry, adis16480, 296 &adis16480_firmware_date_fops); 297 debugfs_create_file_unsafe("serial_number", 0400, 298 indio_dev->debugfs_dentry, adis16480, 299 &adis16480_serial_number_fops); 300 debugfs_create_file_unsafe("product_id", 0400, 301 indio_dev->debugfs_dentry, adis16480, 302 &adis16480_product_id_fops); 303 debugfs_create_file_unsafe("flash_count", 0400, 304 indio_dev->debugfs_dentry, adis16480, 305 &adis16480_flash_count_fops); 306 307 return 0; 308 } 309 310 #else 311 312 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 313 { 314 return 0; 315 } 316 317 #endif 318 319 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 320 { 321 struct adis16480 *st = iio_priv(indio_dev); 322 unsigned int t, reg; 323 324 t = val * 1000 + val2 / 1000; 325 if (t <= 0) 326 return -EINVAL; 327 328 /* 329 * When using PPS mode, the rate of data collection is equal to the 330 * product of the external clock frequency and the scale factor in the 331 * SYNC_SCALE register. 332 * When using sync mode, or internal clock, the output data rate is 333 * equal with the clock frequency divided by DEC_RATE + 1. 334 */ 335 if (st->clk_mode == ADIS16480_CLK_PPS) { 336 t = t / st->clk_freq; 337 reg = ADIS16495_REG_SYNC_SCALE; 338 } else { 339 t = st->clk_freq / t; 340 reg = ADIS16480_REG_DEC_RATE; 341 } 342 343 if (t > st->chip_info->max_dec_rate) 344 t = st->chip_info->max_dec_rate; 345 346 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 347 t--; 348 349 return adis_write_reg_16(&st->adis, reg, t); 350 } 351 352 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 353 { 354 struct adis16480 *st = iio_priv(indio_dev); 355 uint16_t t; 356 int ret; 357 unsigned freq; 358 unsigned int reg; 359 360 if (st->clk_mode == ADIS16480_CLK_PPS) 361 reg = ADIS16495_REG_SYNC_SCALE; 362 else 363 reg = ADIS16480_REG_DEC_RATE; 364 365 ret = adis_read_reg_16(&st->adis, reg, &t); 366 if (ret < 0) 367 return ret; 368 369 /* 370 * When using PPS mode, the rate of data collection is equal to the 371 * product of the external clock frequency and the scale factor in the 372 * SYNC_SCALE register. 373 * When using sync mode, or internal clock, the output data rate is 374 * equal with the clock frequency divided by DEC_RATE + 1. 375 */ 376 if (st->clk_mode == ADIS16480_CLK_PPS) 377 freq = st->clk_freq * t; 378 else 379 freq = st->clk_freq / (t + 1); 380 381 *val = freq / 1000; 382 *val2 = (freq % 1000) * 1000; 383 384 return IIO_VAL_INT_PLUS_MICRO; 385 } 386 387 enum { 388 ADIS16480_SCAN_GYRO_X, 389 ADIS16480_SCAN_GYRO_Y, 390 ADIS16480_SCAN_GYRO_Z, 391 ADIS16480_SCAN_ACCEL_X, 392 ADIS16480_SCAN_ACCEL_Y, 393 ADIS16480_SCAN_ACCEL_Z, 394 ADIS16480_SCAN_MAGN_X, 395 ADIS16480_SCAN_MAGN_Y, 396 ADIS16480_SCAN_MAGN_Z, 397 ADIS16480_SCAN_BARO, 398 ADIS16480_SCAN_TEMP, 399 }; 400 401 static const unsigned int adis16480_calibbias_regs[] = { 402 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 403 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 404 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 405 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 406 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 407 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 408 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 409 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 410 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 411 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 412 }; 413 414 static const unsigned int adis16480_calibscale_regs[] = { 415 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 416 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 417 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 418 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 419 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 420 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 421 }; 422 423 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 424 const struct iio_chan_spec *chan, int bias) 425 { 426 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 427 struct adis16480 *st = iio_priv(indio_dev); 428 429 switch (chan->type) { 430 case IIO_MAGN: 431 case IIO_PRESSURE: 432 if (bias < -0x8000 || bias >= 0x8000) 433 return -EINVAL; 434 return adis_write_reg_16(&st->adis, reg, bias); 435 case IIO_ANGL_VEL: 436 case IIO_ACCEL: 437 return adis_write_reg_32(&st->adis, reg, bias); 438 default: 439 break; 440 } 441 442 return -EINVAL; 443 } 444 445 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 446 const struct iio_chan_spec *chan, int *bias) 447 { 448 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 449 struct adis16480 *st = iio_priv(indio_dev); 450 uint16_t val16; 451 uint32_t val32; 452 int ret; 453 454 switch (chan->type) { 455 case IIO_MAGN: 456 case IIO_PRESSURE: 457 ret = adis_read_reg_16(&st->adis, reg, &val16); 458 *bias = sign_extend32(val16, 15); 459 break; 460 case IIO_ANGL_VEL: 461 case IIO_ACCEL: 462 ret = adis_read_reg_32(&st->adis, reg, &val32); 463 *bias = sign_extend32(val32, 31); 464 break; 465 default: 466 ret = -EINVAL; 467 } 468 469 if (ret < 0) 470 return ret; 471 472 return IIO_VAL_INT; 473 } 474 475 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 476 const struct iio_chan_spec *chan, int scale) 477 { 478 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 479 struct adis16480 *st = iio_priv(indio_dev); 480 481 if (scale < -0x8000 || scale >= 0x8000) 482 return -EINVAL; 483 484 return adis_write_reg_16(&st->adis, reg, scale); 485 } 486 487 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 488 const struct iio_chan_spec *chan, int *scale) 489 { 490 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 491 struct adis16480 *st = iio_priv(indio_dev); 492 uint16_t val16; 493 int ret; 494 495 ret = adis_read_reg_16(&st->adis, reg, &val16); 496 if (ret < 0) 497 return ret; 498 499 *scale = sign_extend32(val16, 15); 500 return IIO_VAL_INT; 501 } 502 503 static const unsigned int adis16480_def_filter_freqs[] = { 504 310, 505 55, 506 275, 507 63, 508 }; 509 510 static const unsigned int adis16495_def_filter_freqs[] = { 511 300, 512 100, 513 300, 514 100, 515 }; 516 517 static const unsigned int ad16480_filter_data[][2] = { 518 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 519 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 520 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 521 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 522 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 523 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 524 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 525 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 526 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 527 }; 528 529 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 530 const struct iio_chan_spec *chan, int *freq) 531 { 532 struct adis16480 *st = iio_priv(indio_dev); 533 unsigned int enable_mask, offset, reg; 534 uint16_t val; 535 int ret; 536 537 reg = ad16480_filter_data[chan->scan_index][0]; 538 offset = ad16480_filter_data[chan->scan_index][1]; 539 enable_mask = BIT(offset + 2); 540 541 ret = adis_read_reg_16(&st->adis, reg, &val); 542 if (ret < 0) 543 return ret; 544 545 if (!(val & enable_mask)) 546 *freq = 0; 547 else 548 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 549 550 return IIO_VAL_INT; 551 } 552 553 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 554 const struct iio_chan_spec *chan, unsigned int freq) 555 { 556 struct adis16480 *st = iio_priv(indio_dev); 557 unsigned int enable_mask, offset, reg; 558 unsigned int diff, best_diff; 559 unsigned int i, best_freq; 560 uint16_t val; 561 int ret; 562 563 reg = ad16480_filter_data[chan->scan_index][0]; 564 offset = ad16480_filter_data[chan->scan_index][1]; 565 enable_mask = BIT(offset + 2); 566 567 ret = adis_read_reg_16(&st->adis, reg, &val); 568 if (ret < 0) 569 return ret; 570 571 if (freq == 0) { 572 val &= ~enable_mask; 573 } else { 574 best_freq = 0; 575 best_diff = st->chip_info->filter_freqs[0]; 576 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 577 if (st->chip_info->filter_freqs[i] >= freq) { 578 diff = st->chip_info->filter_freqs[i] - freq; 579 if (diff < best_diff) { 580 best_diff = diff; 581 best_freq = i; 582 } 583 } 584 } 585 586 val &= ~(0x3 << offset); 587 val |= best_freq << offset; 588 val |= enable_mask; 589 } 590 591 return adis_write_reg_16(&st->adis, reg, val); 592 } 593 594 static int adis16480_read_raw(struct iio_dev *indio_dev, 595 const struct iio_chan_spec *chan, int *val, int *val2, long info) 596 { 597 struct adis16480 *st = iio_priv(indio_dev); 598 unsigned int temp; 599 600 switch (info) { 601 case IIO_CHAN_INFO_RAW: 602 return adis_single_conversion(indio_dev, chan, 0, val); 603 case IIO_CHAN_INFO_SCALE: 604 switch (chan->type) { 605 case IIO_ANGL_VEL: 606 *val = st->chip_info->gyro_max_scale; 607 *val2 = st->chip_info->gyro_max_val; 608 return IIO_VAL_FRACTIONAL; 609 case IIO_ACCEL: 610 *val = st->chip_info->accel_max_scale; 611 *val2 = st->chip_info->accel_max_val; 612 return IIO_VAL_FRACTIONAL; 613 case IIO_MAGN: 614 *val = 0; 615 *val2 = 100; /* 0.0001 gauss */ 616 return IIO_VAL_INT_PLUS_MICRO; 617 case IIO_TEMP: 618 /* 619 * +85 degrees Celsius = temp_max_scale 620 * +25 degrees Celsius = 0 621 * LSB, 25 degrees Celsius = 60 / temp_max_scale 622 */ 623 *val = st->chip_info->temp_scale / 1000; 624 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 625 return IIO_VAL_INT_PLUS_MICRO; 626 case IIO_PRESSURE: 627 *val = 0; 628 *val2 = 4000; /* 40ubar = 0.004 kPa */ 629 return IIO_VAL_INT_PLUS_MICRO; 630 default: 631 return -EINVAL; 632 } 633 case IIO_CHAN_INFO_OFFSET: 634 /* Only the temperature channel has a offset */ 635 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 636 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 637 return IIO_VAL_INT; 638 case IIO_CHAN_INFO_CALIBBIAS: 639 return adis16480_get_calibbias(indio_dev, chan, val); 640 case IIO_CHAN_INFO_CALIBSCALE: 641 return adis16480_get_calibscale(indio_dev, chan, val); 642 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 643 return adis16480_get_filter_freq(indio_dev, chan, val); 644 case IIO_CHAN_INFO_SAMP_FREQ: 645 return adis16480_get_freq(indio_dev, val, val2); 646 default: 647 return -EINVAL; 648 } 649 } 650 651 static int adis16480_write_raw(struct iio_dev *indio_dev, 652 const struct iio_chan_spec *chan, int val, int val2, long info) 653 { 654 switch (info) { 655 case IIO_CHAN_INFO_CALIBBIAS: 656 return adis16480_set_calibbias(indio_dev, chan, val); 657 case IIO_CHAN_INFO_CALIBSCALE: 658 return adis16480_set_calibscale(indio_dev, chan, val); 659 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 660 return adis16480_set_filter_freq(indio_dev, chan, val); 661 case IIO_CHAN_INFO_SAMP_FREQ: 662 return adis16480_set_freq(indio_dev, val, val2); 663 664 default: 665 return -EINVAL; 666 } 667 } 668 669 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 670 { \ 671 .type = (_type), \ 672 .modified = 1, \ 673 .channel2 = (_mod), \ 674 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 675 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 676 _info_sep, \ 677 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 678 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 679 .address = (_address), \ 680 .scan_index = (_si), \ 681 .scan_type = { \ 682 .sign = 's', \ 683 .realbits = (_bits), \ 684 .storagebits = (_bits), \ 685 .endianness = IIO_BE, \ 686 }, \ 687 } 688 689 #define ADIS16480_GYRO_CHANNEL(_mod) \ 690 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 691 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 692 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 693 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 694 32) 695 696 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 697 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 698 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 699 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 700 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 701 32) 702 703 #define ADIS16480_MAGN_CHANNEL(_mod) \ 704 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 705 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 706 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 707 16) 708 709 #define ADIS16480_PRESSURE_CHANNEL() \ 710 { \ 711 .type = IIO_PRESSURE, \ 712 .indexed = 1, \ 713 .channel = 0, \ 714 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 715 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 716 BIT(IIO_CHAN_INFO_SCALE), \ 717 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 718 .address = ADIS16480_REG_BAROM_OUT, \ 719 .scan_index = ADIS16480_SCAN_BARO, \ 720 .scan_type = { \ 721 .sign = 's', \ 722 .realbits = 32, \ 723 .storagebits = 32, \ 724 .endianness = IIO_BE, \ 725 }, \ 726 } 727 728 #define ADIS16480_TEMP_CHANNEL() { \ 729 .type = IIO_TEMP, \ 730 .indexed = 1, \ 731 .channel = 0, \ 732 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 733 BIT(IIO_CHAN_INFO_SCALE) | \ 734 BIT(IIO_CHAN_INFO_OFFSET), \ 735 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 736 .address = ADIS16480_REG_TEMP_OUT, \ 737 .scan_index = ADIS16480_SCAN_TEMP, \ 738 .scan_type = { \ 739 .sign = 's', \ 740 .realbits = 16, \ 741 .storagebits = 16, \ 742 .endianness = IIO_BE, \ 743 }, \ 744 } 745 746 static const struct iio_chan_spec adis16480_channels[] = { 747 ADIS16480_GYRO_CHANNEL(X), 748 ADIS16480_GYRO_CHANNEL(Y), 749 ADIS16480_GYRO_CHANNEL(Z), 750 ADIS16480_ACCEL_CHANNEL(X), 751 ADIS16480_ACCEL_CHANNEL(Y), 752 ADIS16480_ACCEL_CHANNEL(Z), 753 ADIS16480_MAGN_CHANNEL(X), 754 ADIS16480_MAGN_CHANNEL(Y), 755 ADIS16480_MAGN_CHANNEL(Z), 756 ADIS16480_PRESSURE_CHANNEL(), 757 ADIS16480_TEMP_CHANNEL(), 758 IIO_CHAN_SOFT_TIMESTAMP(11) 759 }; 760 761 static const struct iio_chan_spec adis16485_channels[] = { 762 ADIS16480_GYRO_CHANNEL(X), 763 ADIS16480_GYRO_CHANNEL(Y), 764 ADIS16480_GYRO_CHANNEL(Z), 765 ADIS16480_ACCEL_CHANNEL(X), 766 ADIS16480_ACCEL_CHANNEL(Y), 767 ADIS16480_ACCEL_CHANNEL(Z), 768 ADIS16480_TEMP_CHANNEL(), 769 IIO_CHAN_SOFT_TIMESTAMP(7) 770 }; 771 772 enum adis16480_variant { 773 ADIS16375, 774 ADIS16480, 775 ADIS16485, 776 ADIS16488, 777 ADIS16495_1, 778 ADIS16495_2, 779 ADIS16495_3, 780 ADIS16497_1, 781 ADIS16497_2, 782 ADIS16497_3, 783 }; 784 785 static const struct adis16480_chip_info adis16480_chip_info[] = { 786 [ADIS16375] = { 787 .channels = adis16485_channels, 788 .num_channels = ARRAY_SIZE(adis16485_channels), 789 /* 790 * storing the value in rad/degree and the scale in degree 791 * gives us the result in rad and better precession than 792 * storing the scale directly in rad. 793 */ 794 .gyro_max_val = IIO_RAD_TO_DEGREE(22887), 795 .gyro_max_scale = 300, 796 .accel_max_val = IIO_M_S_2_TO_G(21973), 797 .accel_max_scale = 18, 798 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 799 .int_clk = 2460000, 800 .max_dec_rate = 2048, 801 .filter_freqs = adis16480_def_filter_freqs, 802 }, 803 [ADIS16480] = { 804 .channels = adis16480_channels, 805 .num_channels = ARRAY_SIZE(adis16480_channels), 806 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 807 .gyro_max_scale = 450, 808 .accel_max_val = IIO_M_S_2_TO_G(12500), 809 .accel_max_scale = 10, 810 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 811 .int_clk = 2460000, 812 .max_dec_rate = 2048, 813 .filter_freqs = adis16480_def_filter_freqs, 814 }, 815 [ADIS16485] = { 816 .channels = adis16485_channels, 817 .num_channels = ARRAY_SIZE(adis16485_channels), 818 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 819 .gyro_max_scale = 450, 820 .accel_max_val = IIO_M_S_2_TO_G(20000), 821 .accel_max_scale = 5, 822 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 823 .int_clk = 2460000, 824 .max_dec_rate = 2048, 825 .filter_freqs = adis16480_def_filter_freqs, 826 }, 827 [ADIS16488] = { 828 .channels = adis16480_channels, 829 .num_channels = ARRAY_SIZE(adis16480_channels), 830 .gyro_max_val = IIO_RAD_TO_DEGREE(22500), 831 .gyro_max_scale = 450, 832 .accel_max_val = IIO_M_S_2_TO_G(22500), 833 .accel_max_scale = 18, 834 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 835 .int_clk = 2460000, 836 .max_dec_rate = 2048, 837 .filter_freqs = adis16480_def_filter_freqs, 838 }, 839 [ADIS16495_1] = { 840 .channels = adis16485_channels, 841 .num_channels = ARRAY_SIZE(adis16485_channels), 842 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 843 .gyro_max_scale = 125, 844 .accel_max_val = IIO_M_S_2_TO_G(32000), 845 .accel_max_scale = 8, 846 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 847 .int_clk = 4250000, 848 .max_dec_rate = 4250, 849 .filter_freqs = adis16495_def_filter_freqs, 850 .has_pps_clk_mode = true, 851 }, 852 [ADIS16495_2] = { 853 .channels = adis16485_channels, 854 .num_channels = ARRAY_SIZE(adis16485_channels), 855 .gyro_max_val = IIO_RAD_TO_DEGREE(18000), 856 .gyro_max_scale = 450, 857 .accel_max_val = IIO_M_S_2_TO_G(32000), 858 .accel_max_scale = 8, 859 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 860 .int_clk = 4250000, 861 .max_dec_rate = 4250, 862 .filter_freqs = adis16495_def_filter_freqs, 863 .has_pps_clk_mode = true, 864 }, 865 [ADIS16495_3] = { 866 .channels = adis16485_channels, 867 .num_channels = ARRAY_SIZE(adis16485_channels), 868 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 869 .gyro_max_scale = 2000, 870 .accel_max_val = IIO_M_S_2_TO_G(32000), 871 .accel_max_scale = 8, 872 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 873 .int_clk = 4250000, 874 .max_dec_rate = 4250, 875 .filter_freqs = adis16495_def_filter_freqs, 876 .has_pps_clk_mode = true, 877 }, 878 [ADIS16497_1] = { 879 .channels = adis16485_channels, 880 .num_channels = ARRAY_SIZE(adis16485_channels), 881 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 882 .gyro_max_scale = 125, 883 .accel_max_val = IIO_M_S_2_TO_G(32000), 884 .accel_max_scale = 40, 885 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 886 .int_clk = 4250000, 887 .max_dec_rate = 4250, 888 .filter_freqs = adis16495_def_filter_freqs, 889 .has_pps_clk_mode = true, 890 }, 891 [ADIS16497_2] = { 892 .channels = adis16485_channels, 893 .num_channels = ARRAY_SIZE(adis16485_channels), 894 .gyro_max_val = IIO_RAD_TO_DEGREE(18000), 895 .gyro_max_scale = 450, 896 .accel_max_val = IIO_M_S_2_TO_G(32000), 897 .accel_max_scale = 40, 898 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 899 .int_clk = 4250000, 900 .max_dec_rate = 4250, 901 .filter_freqs = adis16495_def_filter_freqs, 902 .has_pps_clk_mode = true, 903 }, 904 [ADIS16497_3] = { 905 .channels = adis16485_channels, 906 .num_channels = ARRAY_SIZE(adis16485_channels), 907 .gyro_max_val = IIO_RAD_TO_DEGREE(20000), 908 .gyro_max_scale = 2000, 909 .accel_max_val = IIO_M_S_2_TO_G(32000), 910 .accel_max_scale = 40, 911 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 912 .int_clk = 4250000, 913 .max_dec_rate = 4250, 914 .filter_freqs = adis16495_def_filter_freqs, 915 .has_pps_clk_mode = true, 916 }, 917 }; 918 919 static const struct iio_info adis16480_info = { 920 .read_raw = &adis16480_read_raw, 921 .write_raw = &adis16480_write_raw, 922 .update_scan_mode = adis_update_scan_mode, 923 }; 924 925 static int adis16480_stop_device(struct iio_dev *indio_dev) 926 { 927 struct adis16480 *st = iio_priv(indio_dev); 928 int ret; 929 930 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 931 if (ret) 932 dev_err(&indio_dev->dev, 933 "Could not power down device: %d\n", ret); 934 935 return ret; 936 } 937 938 static int adis16480_enable_irq(struct adis *adis, bool enable) 939 { 940 uint16_t val; 941 int ret; 942 943 ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 944 if (ret < 0) 945 return ret; 946 947 val &= ~ADIS16480_DRDY_EN_MSK; 948 val |= ADIS16480_DRDY_EN(enable); 949 950 return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 951 } 952 953 static int adis16480_initial_setup(struct iio_dev *indio_dev) 954 { 955 struct adis16480 *st = iio_priv(indio_dev); 956 uint16_t prod_id; 957 unsigned int device_id; 958 int ret; 959 960 adis_reset(&st->adis); 961 msleep(70); 962 963 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1)); 964 if (ret) 965 return ret; 966 msleep(30); 967 968 ret = adis_check_status(&st->adis); 969 if (ret) 970 return ret; 971 972 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id); 973 if (ret) 974 return ret; 975 976 ret = sscanf(indio_dev->name, "adis%u\n", &device_id); 977 if (ret != 1) 978 return -EINVAL; 979 980 if (prod_id != device_id) 981 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.", 982 device_id, prod_id); 983 984 return 0; 985 } 986 987 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 988 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 989 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 990 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 991 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 992 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 993 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 994 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 995 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 996 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 997 998 static const char * const adis16480_status_error_msgs[] = { 999 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 1000 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 1001 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 1002 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 1003 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 1004 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 1005 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 1006 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 1007 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 1008 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 1009 }; 1010 1011 static const struct adis_data adis16480_data = { 1012 .diag_stat_reg = ADIS16480_REG_DIAG_STS, 1013 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, 1014 .has_paging = true, 1015 1016 .read_delay = 5, 1017 .write_delay = 5, 1018 1019 .status_error_msgs = adis16480_status_error_msgs, 1020 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | 1021 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | 1022 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | 1023 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | 1024 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | 1025 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | 1026 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | 1027 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | 1028 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | 1029 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), 1030 1031 .enable_irq = adis16480_enable_irq, 1032 }; 1033 1034 static int adis16480_config_irq_pin(struct device_node *of_node, 1035 struct adis16480 *st) 1036 { 1037 struct irq_data *desc; 1038 enum adis16480_int_pin pin; 1039 unsigned int irq_type; 1040 uint16_t val; 1041 int i, irq = 0; 1042 1043 desc = irq_get_irq_data(st->adis.spi->irq); 1044 if (!desc) { 1045 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1046 return -EINVAL; 1047 } 1048 1049 /* Disable data ready since the default after reset is on */ 1050 val = ADIS16480_DRDY_EN(0); 1051 1052 /* 1053 * Get the interrupt from the devicetre by reading the interrupt-names 1054 * property. If it is not specified, use DIO1 pin as default. 1055 * According to the datasheet, the factory default assigns DIO2 as data 1056 * ready signal. However, in the previous versions of the driver, DIO1 1057 * pin was used. So, we should leave it as is since some devices might 1058 * be expecting the interrupt on the wrong physical pin. 1059 */ 1060 pin = ADIS16480_PIN_DIO1; 1061 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1062 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1063 if (irq > 0) { 1064 pin = i; 1065 break; 1066 } 1067 } 1068 1069 val |= ADIS16480_DRDY_SEL(pin); 1070 1071 /* 1072 * Get the interrupt line behaviour. The data ready polarity can be 1073 * configured as positive or negative, corresponding to 1074 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. 1075 */ 1076 irq_type = irqd_get_trigger_type(desc); 1077 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ 1078 val |= ADIS16480_DRDY_POL(1); 1079 } else if (irq_type == IRQF_TRIGGER_FALLING) { 1080 val |= ADIS16480_DRDY_POL(0); 1081 } else { 1082 dev_err(&st->adis.spi->dev, 1083 "Invalid interrupt type 0x%x specified\n", irq_type); 1084 return -EINVAL; 1085 } 1086 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1087 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1088 } 1089 1090 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1091 struct device_node *of_node) 1092 { 1093 const char *ext_clk_pin; 1094 enum adis16480_int_pin pin; 1095 int i; 1096 1097 pin = ADIS16480_PIN_DIO2; 1098 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1099 goto clk_input_not_found; 1100 1101 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1102 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1103 return i; 1104 } 1105 1106 clk_input_not_found: 1107 dev_info(&st->adis.spi->dev, 1108 "clk input line not specified, using DIO2\n"); 1109 return pin; 1110 } 1111 1112 static int adis16480_ext_clk_config(struct adis16480 *st, 1113 struct device_node *of_node, 1114 bool enable) 1115 { 1116 unsigned int mode, mask; 1117 enum adis16480_int_pin pin; 1118 uint16_t val; 1119 int ret; 1120 1121 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1122 if (ret < 0) 1123 return ret; 1124 1125 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1126 /* 1127 * Each DIOx pin supports only one function at a time. When a single pin 1128 * has two assignments, the enable bit for a lower priority function 1129 * automatically resets to zero (disabling the lower priority function). 1130 */ 1131 if (pin == ADIS16480_DRDY_SEL(val)) 1132 dev_warn(&st->adis.spi->dev, 1133 "DIO%x pin supports only one function at a time\n", 1134 pin + 1); 1135 1136 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1137 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1138 /* Only ADIS1649x devices support pps ext clock mode */ 1139 if (st->chip_info->has_pps_clk_mode) { 1140 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1141 mask |= ADIS16480_SYNC_MODE_MSK; 1142 } 1143 1144 val &= ~mask; 1145 val |= mode; 1146 1147 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1148 if (ret < 0) 1149 return ret; 1150 1151 return clk_prepare_enable(st->ext_clk); 1152 } 1153 1154 static int adis16480_get_ext_clocks(struct adis16480 *st) 1155 { 1156 st->clk_mode = ADIS16480_CLK_INT; 1157 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1158 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1159 st->clk_mode = ADIS16480_CLK_SYNC; 1160 return 0; 1161 } 1162 1163 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1164 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1165 return PTR_ERR(st->ext_clk); 1166 } 1167 1168 if (st->chip_info->has_pps_clk_mode) { 1169 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1170 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1171 st->clk_mode = ADIS16480_CLK_PPS; 1172 return 0; 1173 } 1174 1175 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1176 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1177 return PTR_ERR(st->ext_clk); 1178 } 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int adis16480_probe(struct spi_device *spi) 1185 { 1186 const struct spi_device_id *id = spi_get_device_id(spi); 1187 struct iio_dev *indio_dev; 1188 struct adis16480 *st; 1189 int ret; 1190 1191 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1192 if (indio_dev == NULL) 1193 return -ENOMEM; 1194 1195 spi_set_drvdata(spi, indio_dev); 1196 1197 st = iio_priv(indio_dev); 1198 1199 st->chip_info = &adis16480_chip_info[id->driver_data]; 1200 indio_dev->dev.parent = &spi->dev; 1201 indio_dev->name = spi_get_device_id(spi)->name; 1202 indio_dev->channels = st->chip_info->channels; 1203 indio_dev->num_channels = st->chip_info->num_channels; 1204 indio_dev->info = &adis16480_info; 1205 indio_dev->modes = INDIO_DIRECT_MODE; 1206 1207 ret = adis_init(&st->adis, indio_dev, spi, &adis16480_data); 1208 if (ret) 1209 return ret; 1210 1211 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1212 if (ret) 1213 return ret; 1214 1215 ret = adis16480_get_ext_clocks(st); 1216 if (ret) 1217 return ret; 1218 1219 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1220 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1221 if (ret) 1222 return ret; 1223 1224 st->clk_freq = clk_get_rate(st->ext_clk); 1225 st->clk_freq *= 1000; /* micro */ 1226 } else { 1227 st->clk_freq = st->chip_info->int_clk; 1228 } 1229 1230 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1231 if (ret) 1232 goto error_clk_disable_unprepare; 1233 1234 ret = adis16480_initial_setup(indio_dev); 1235 if (ret) 1236 goto error_cleanup_buffer; 1237 1238 ret = iio_device_register(indio_dev); 1239 if (ret) 1240 goto error_stop_device; 1241 1242 adis16480_debugfs_init(indio_dev); 1243 1244 return 0; 1245 1246 error_stop_device: 1247 adis16480_stop_device(indio_dev); 1248 error_cleanup_buffer: 1249 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1250 error_clk_disable_unprepare: 1251 clk_disable_unprepare(st->ext_clk); 1252 return ret; 1253 } 1254 1255 static int adis16480_remove(struct spi_device *spi) 1256 { 1257 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1258 struct adis16480 *st = iio_priv(indio_dev); 1259 1260 iio_device_unregister(indio_dev); 1261 adis16480_stop_device(indio_dev); 1262 1263 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1264 clk_disable_unprepare(st->ext_clk); 1265 1266 return 0; 1267 } 1268 1269 static const struct spi_device_id adis16480_ids[] = { 1270 { "adis16375", ADIS16375 }, 1271 { "adis16480", ADIS16480 }, 1272 { "adis16485", ADIS16485 }, 1273 { "adis16488", ADIS16488 }, 1274 { "adis16495-1", ADIS16495_1 }, 1275 { "adis16495-2", ADIS16495_2 }, 1276 { "adis16495-3", ADIS16495_3 }, 1277 { "adis16497-1", ADIS16497_1 }, 1278 { "adis16497-2", ADIS16497_2 }, 1279 { "adis16497-3", ADIS16497_3 }, 1280 { } 1281 }; 1282 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1283 1284 static const struct of_device_id adis16480_of_match[] = { 1285 { .compatible = "adi,adis16375" }, 1286 { .compatible = "adi,adis16480" }, 1287 { .compatible = "adi,adis16485" }, 1288 { .compatible = "adi,adis16488" }, 1289 { .compatible = "adi,adis16495-1" }, 1290 { .compatible = "adi,adis16495-2" }, 1291 { .compatible = "adi,adis16495-3" }, 1292 { .compatible = "adi,adis16497-1" }, 1293 { .compatible = "adi,adis16497-2" }, 1294 { .compatible = "adi,adis16497-3" }, 1295 { }, 1296 }; 1297 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1298 1299 static struct spi_driver adis16480_driver = { 1300 .driver = { 1301 .name = "adis16480", 1302 .of_match_table = adis16480_of_match, 1303 }, 1304 .id_table = adis16480_ids, 1305 .probe = adis16480_probe, 1306 .remove = adis16480_remove, 1307 }; 1308 module_spi_driver(adis16480_driver); 1309 1310 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1311 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1312 MODULE_LICENSE("GPL v2"); 1313