1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/spi/spi.h> 17 #include <linux/slab.h> 18 #include <linux/sysfs.h> 19 #include <linux/module.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/imu/adis.h> 25 26 #include <linux/debugfs.h> 27 28 #define ADIS16480_PAGE_SIZE 0x80 29 30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99 /* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 105 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 106 107 /* Each filter coefficent bank spans two pages */ 108 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 109 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 110 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 111 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 112 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 113 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 114 115 /* ADIS16480_REG_FNCTIO_CTRL */ 116 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 117 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 118 #define ADIS16480_DRDY_POL_MSK BIT(2) 119 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 120 #define ADIS16480_DRDY_EN_MSK BIT(3) 121 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 122 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 123 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 124 #define ADIS16480_SYNC_EN_MSK BIT(7) 125 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 126 #define ADIS16480_SYNC_MODE_MSK BIT(8) 127 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 128 129 struct adis16480_chip_info { 130 unsigned int num_channels; 131 const struct iio_chan_spec *channels; 132 unsigned int gyro_max_val; 133 unsigned int gyro_max_scale; 134 unsigned int accel_max_val; 135 unsigned int accel_max_scale; 136 unsigned int temp_scale; 137 unsigned int int_clk; 138 unsigned int max_dec_rate; 139 const unsigned int *filter_freqs; 140 bool has_pps_clk_mode; 141 }; 142 143 enum adis16480_int_pin { 144 ADIS16480_PIN_DIO1, 145 ADIS16480_PIN_DIO2, 146 ADIS16480_PIN_DIO3, 147 ADIS16480_PIN_DIO4 148 }; 149 150 enum adis16480_clock_mode { 151 ADIS16480_CLK_SYNC, 152 ADIS16480_CLK_PPS, 153 ADIS16480_CLK_INT 154 }; 155 156 struct adis16480 { 157 const struct adis16480_chip_info *chip_info; 158 159 struct adis adis; 160 struct clk *ext_clk; 161 enum adis16480_clock_mode clk_mode; 162 unsigned int clk_freq; 163 }; 164 165 static const char * const adis16480_int_pin_names[4] = { 166 [ADIS16480_PIN_DIO1] = "DIO1", 167 [ADIS16480_PIN_DIO2] = "DIO2", 168 [ADIS16480_PIN_DIO3] = "DIO3", 169 [ADIS16480_PIN_DIO4] = "DIO4", 170 }; 171 172 #ifdef CONFIG_DEBUG_FS 173 174 static ssize_t adis16480_show_firmware_revision(struct file *file, 175 char __user *userbuf, size_t count, loff_t *ppos) 176 { 177 struct adis16480 *adis16480 = file->private_data; 178 char buf[7]; 179 size_t len; 180 u16 rev; 181 int ret; 182 183 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 184 if (ret) 185 return ret; 186 187 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 188 189 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 190 } 191 192 static const struct file_operations adis16480_firmware_revision_fops = { 193 .open = simple_open, 194 .read = adis16480_show_firmware_revision, 195 .llseek = default_llseek, 196 .owner = THIS_MODULE, 197 }; 198 199 static ssize_t adis16480_show_firmware_date(struct file *file, 200 char __user *userbuf, size_t count, loff_t *ppos) 201 { 202 struct adis16480 *adis16480 = file->private_data; 203 u16 md, year; 204 char buf[12]; 205 size_t len; 206 int ret; 207 208 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 209 if (ret) 210 return ret; 211 212 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 213 if (ret) 214 return ret; 215 216 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 217 md >> 8, md & 0xff, year); 218 219 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 220 } 221 222 static const struct file_operations adis16480_firmware_date_fops = { 223 .open = simple_open, 224 .read = adis16480_show_firmware_date, 225 .llseek = default_llseek, 226 .owner = THIS_MODULE, 227 }; 228 229 static int adis16480_show_serial_number(void *arg, u64 *val) 230 { 231 struct adis16480 *adis16480 = arg; 232 u16 serial; 233 int ret; 234 235 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 236 &serial); 237 if (ret) 238 return ret; 239 240 *val = serial; 241 242 return 0; 243 } 244 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 245 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 246 247 static int adis16480_show_product_id(void *arg, u64 *val) 248 { 249 struct adis16480 *adis16480 = arg; 250 u16 prod_id; 251 int ret; 252 253 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 254 &prod_id); 255 if (ret) 256 return ret; 257 258 *val = prod_id; 259 260 return 0; 261 } 262 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 263 adis16480_show_product_id, NULL, "%llu\n"); 264 265 static int adis16480_show_flash_count(void *arg, u64 *val) 266 { 267 struct adis16480 *adis16480 = arg; 268 u32 flash_count; 269 int ret; 270 271 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 272 &flash_count); 273 if (ret) 274 return ret; 275 276 *val = flash_count; 277 278 return 0; 279 } 280 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 281 adis16480_show_flash_count, NULL, "%lld\n"); 282 283 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 284 { 285 struct adis16480 *adis16480 = iio_priv(indio_dev); 286 287 debugfs_create_file_unsafe("firmware_revision", 0400, 288 indio_dev->debugfs_dentry, adis16480, 289 &adis16480_firmware_revision_fops); 290 debugfs_create_file_unsafe("firmware_date", 0400, 291 indio_dev->debugfs_dentry, adis16480, 292 &adis16480_firmware_date_fops); 293 debugfs_create_file_unsafe("serial_number", 0400, 294 indio_dev->debugfs_dentry, adis16480, 295 &adis16480_serial_number_fops); 296 debugfs_create_file_unsafe("product_id", 0400, 297 indio_dev->debugfs_dentry, adis16480, 298 &adis16480_product_id_fops); 299 debugfs_create_file_unsafe("flash_count", 0400, 300 indio_dev->debugfs_dentry, adis16480, 301 &adis16480_flash_count_fops); 302 303 return 0; 304 } 305 306 #else 307 308 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 309 { 310 return 0; 311 } 312 313 #endif 314 315 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 316 { 317 struct adis16480 *st = iio_priv(indio_dev); 318 unsigned int t, reg; 319 320 if (val < 0 || val2 < 0) 321 return -EINVAL; 322 323 t = val * 1000 + val2 / 1000; 324 if (t == 0) 325 return -EINVAL; 326 327 /* 328 * When using PPS mode, the rate of data collection is equal to the 329 * product of the external clock frequency and the scale factor in the 330 * SYNC_SCALE register. 331 * When using sync mode, or internal clock, the output data rate is 332 * equal with the clock frequency divided by DEC_RATE + 1. 333 */ 334 if (st->clk_mode == ADIS16480_CLK_PPS) { 335 t = t / st->clk_freq; 336 reg = ADIS16495_REG_SYNC_SCALE; 337 } else { 338 t = st->clk_freq / t; 339 reg = ADIS16480_REG_DEC_RATE; 340 } 341 342 if (t > st->chip_info->max_dec_rate) 343 t = st->chip_info->max_dec_rate; 344 345 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 346 t--; 347 348 return adis_write_reg_16(&st->adis, reg, t); 349 } 350 351 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 352 { 353 struct adis16480 *st = iio_priv(indio_dev); 354 uint16_t t; 355 int ret; 356 unsigned int freq; 357 unsigned int reg; 358 359 if (st->clk_mode == ADIS16480_CLK_PPS) 360 reg = ADIS16495_REG_SYNC_SCALE; 361 else 362 reg = ADIS16480_REG_DEC_RATE; 363 364 ret = adis_read_reg_16(&st->adis, reg, &t); 365 if (ret) 366 return ret; 367 368 /* 369 * When using PPS mode, the rate of data collection is equal to the 370 * product of the external clock frequency and the scale factor in the 371 * SYNC_SCALE register. 372 * When using sync mode, or internal clock, the output data rate is 373 * equal with the clock frequency divided by DEC_RATE + 1. 374 */ 375 if (st->clk_mode == ADIS16480_CLK_PPS) 376 freq = st->clk_freq * t; 377 else 378 freq = st->clk_freq / (t + 1); 379 380 *val = freq / 1000; 381 *val2 = (freq % 1000) * 1000; 382 383 return IIO_VAL_INT_PLUS_MICRO; 384 } 385 386 enum { 387 ADIS16480_SCAN_GYRO_X, 388 ADIS16480_SCAN_GYRO_Y, 389 ADIS16480_SCAN_GYRO_Z, 390 ADIS16480_SCAN_ACCEL_X, 391 ADIS16480_SCAN_ACCEL_Y, 392 ADIS16480_SCAN_ACCEL_Z, 393 ADIS16480_SCAN_MAGN_X, 394 ADIS16480_SCAN_MAGN_Y, 395 ADIS16480_SCAN_MAGN_Z, 396 ADIS16480_SCAN_BARO, 397 ADIS16480_SCAN_TEMP, 398 }; 399 400 static const unsigned int adis16480_calibbias_regs[] = { 401 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 402 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 403 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 404 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 405 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 406 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 407 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 408 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 409 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 410 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 411 }; 412 413 static const unsigned int adis16480_calibscale_regs[] = { 414 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 415 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 416 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 417 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 418 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 419 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 420 }; 421 422 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 423 const struct iio_chan_spec *chan, int bias) 424 { 425 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 426 struct adis16480 *st = iio_priv(indio_dev); 427 428 switch (chan->type) { 429 case IIO_MAGN: 430 case IIO_PRESSURE: 431 if (bias < -0x8000 || bias >= 0x8000) 432 return -EINVAL; 433 return adis_write_reg_16(&st->adis, reg, bias); 434 case IIO_ANGL_VEL: 435 case IIO_ACCEL: 436 return adis_write_reg_32(&st->adis, reg, bias); 437 default: 438 break; 439 } 440 441 return -EINVAL; 442 } 443 444 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 445 const struct iio_chan_spec *chan, int *bias) 446 { 447 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 448 struct adis16480 *st = iio_priv(indio_dev); 449 uint16_t val16; 450 uint32_t val32; 451 int ret; 452 453 switch (chan->type) { 454 case IIO_MAGN: 455 case IIO_PRESSURE: 456 ret = adis_read_reg_16(&st->adis, reg, &val16); 457 if (ret == 0) 458 *bias = sign_extend32(val16, 15); 459 break; 460 case IIO_ANGL_VEL: 461 case IIO_ACCEL: 462 ret = adis_read_reg_32(&st->adis, reg, &val32); 463 if (ret == 0) 464 *bias = sign_extend32(val32, 31); 465 break; 466 default: 467 ret = -EINVAL; 468 } 469 470 if (ret) 471 return ret; 472 473 return IIO_VAL_INT; 474 } 475 476 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 477 const struct iio_chan_spec *chan, int scale) 478 { 479 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 480 struct adis16480 *st = iio_priv(indio_dev); 481 482 if (scale < -0x8000 || scale >= 0x8000) 483 return -EINVAL; 484 485 return adis_write_reg_16(&st->adis, reg, scale); 486 } 487 488 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 489 const struct iio_chan_spec *chan, int *scale) 490 { 491 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 492 struct adis16480 *st = iio_priv(indio_dev); 493 uint16_t val16; 494 int ret; 495 496 ret = adis_read_reg_16(&st->adis, reg, &val16); 497 if (ret) 498 return ret; 499 500 *scale = sign_extend32(val16, 15); 501 return IIO_VAL_INT; 502 } 503 504 static const unsigned int adis16480_def_filter_freqs[] = { 505 310, 506 55, 507 275, 508 63, 509 }; 510 511 static const unsigned int adis16495_def_filter_freqs[] = { 512 300, 513 100, 514 300, 515 100, 516 }; 517 518 static const unsigned int ad16480_filter_data[][2] = { 519 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 520 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 521 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 522 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 523 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 524 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 525 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 526 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 527 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 528 }; 529 530 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 531 const struct iio_chan_spec *chan, int *freq) 532 { 533 struct adis16480 *st = iio_priv(indio_dev); 534 unsigned int enable_mask, offset, reg; 535 uint16_t val; 536 int ret; 537 538 reg = ad16480_filter_data[chan->scan_index][0]; 539 offset = ad16480_filter_data[chan->scan_index][1]; 540 enable_mask = BIT(offset + 2); 541 542 ret = adis_read_reg_16(&st->adis, reg, &val); 543 if (ret) 544 return ret; 545 546 if (!(val & enable_mask)) 547 *freq = 0; 548 else 549 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 550 551 return IIO_VAL_INT; 552 } 553 554 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 555 const struct iio_chan_spec *chan, unsigned int freq) 556 { 557 struct adis16480 *st = iio_priv(indio_dev); 558 struct mutex *slock = &st->adis.state_lock; 559 unsigned int enable_mask, offset, reg; 560 unsigned int diff, best_diff; 561 unsigned int i, best_freq; 562 uint16_t val; 563 int ret; 564 565 reg = ad16480_filter_data[chan->scan_index][0]; 566 offset = ad16480_filter_data[chan->scan_index][1]; 567 enable_mask = BIT(offset + 2); 568 569 mutex_lock(slock); 570 571 ret = __adis_read_reg_16(&st->adis, reg, &val); 572 if (ret) 573 goto out_unlock; 574 575 if (freq == 0) { 576 val &= ~enable_mask; 577 } else { 578 best_freq = 0; 579 best_diff = st->chip_info->filter_freqs[0]; 580 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 581 if (st->chip_info->filter_freqs[i] >= freq) { 582 diff = st->chip_info->filter_freqs[i] - freq; 583 if (diff < best_diff) { 584 best_diff = diff; 585 best_freq = i; 586 } 587 } 588 } 589 590 val &= ~(0x3 << offset); 591 val |= best_freq << offset; 592 val |= enable_mask; 593 } 594 595 ret = __adis_write_reg_16(&st->adis, reg, val); 596 out_unlock: 597 mutex_unlock(slock); 598 599 return ret; 600 } 601 602 static int adis16480_read_raw(struct iio_dev *indio_dev, 603 const struct iio_chan_spec *chan, int *val, int *val2, long info) 604 { 605 struct adis16480 *st = iio_priv(indio_dev); 606 unsigned int temp; 607 608 switch (info) { 609 case IIO_CHAN_INFO_RAW: 610 return adis_single_conversion(indio_dev, chan, 0, val); 611 case IIO_CHAN_INFO_SCALE: 612 switch (chan->type) { 613 case IIO_ANGL_VEL: 614 *val = st->chip_info->gyro_max_scale; 615 *val2 = st->chip_info->gyro_max_val; 616 return IIO_VAL_FRACTIONAL; 617 case IIO_ACCEL: 618 *val = st->chip_info->accel_max_scale; 619 *val2 = st->chip_info->accel_max_val; 620 return IIO_VAL_FRACTIONAL; 621 case IIO_MAGN: 622 *val = 0; 623 *val2 = 100; /* 0.0001 gauss */ 624 return IIO_VAL_INT_PLUS_MICRO; 625 case IIO_TEMP: 626 /* 627 * +85 degrees Celsius = temp_max_scale 628 * +25 degrees Celsius = 0 629 * LSB, 25 degrees Celsius = 60 / temp_max_scale 630 */ 631 *val = st->chip_info->temp_scale / 1000; 632 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 633 return IIO_VAL_INT_PLUS_MICRO; 634 case IIO_PRESSURE: 635 /* 636 * max scale is 1310 mbar 637 * max raw value is 32767 shifted for 32bits 638 */ 639 *val = 131; /* 1310mbar = 131 kPa */ 640 *val2 = 32767 << 16; 641 return IIO_VAL_FRACTIONAL; 642 default: 643 return -EINVAL; 644 } 645 case IIO_CHAN_INFO_OFFSET: 646 /* Only the temperature channel has a offset */ 647 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 648 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 649 return IIO_VAL_INT; 650 case IIO_CHAN_INFO_CALIBBIAS: 651 return adis16480_get_calibbias(indio_dev, chan, val); 652 case IIO_CHAN_INFO_CALIBSCALE: 653 return adis16480_get_calibscale(indio_dev, chan, val); 654 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 655 return adis16480_get_filter_freq(indio_dev, chan, val); 656 case IIO_CHAN_INFO_SAMP_FREQ: 657 return adis16480_get_freq(indio_dev, val, val2); 658 default: 659 return -EINVAL; 660 } 661 } 662 663 static int adis16480_write_raw(struct iio_dev *indio_dev, 664 const struct iio_chan_spec *chan, int val, int val2, long info) 665 { 666 switch (info) { 667 case IIO_CHAN_INFO_CALIBBIAS: 668 return adis16480_set_calibbias(indio_dev, chan, val); 669 case IIO_CHAN_INFO_CALIBSCALE: 670 return adis16480_set_calibscale(indio_dev, chan, val); 671 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 672 return adis16480_set_filter_freq(indio_dev, chan, val); 673 case IIO_CHAN_INFO_SAMP_FREQ: 674 return adis16480_set_freq(indio_dev, val, val2); 675 676 default: 677 return -EINVAL; 678 } 679 } 680 681 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 682 { \ 683 .type = (_type), \ 684 .modified = 1, \ 685 .channel2 = (_mod), \ 686 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 687 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 688 _info_sep, \ 689 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 690 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 691 .address = (_address), \ 692 .scan_index = (_si), \ 693 .scan_type = { \ 694 .sign = 's', \ 695 .realbits = (_bits), \ 696 .storagebits = (_bits), \ 697 .endianness = IIO_BE, \ 698 }, \ 699 } 700 701 #define ADIS16480_GYRO_CHANNEL(_mod) \ 702 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 703 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 704 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 705 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 706 32) 707 708 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 709 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 710 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 711 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 712 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 713 32) 714 715 #define ADIS16480_MAGN_CHANNEL(_mod) \ 716 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 717 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 718 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 719 16) 720 721 #define ADIS16480_PRESSURE_CHANNEL() \ 722 { \ 723 .type = IIO_PRESSURE, \ 724 .indexed = 1, \ 725 .channel = 0, \ 726 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 727 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 728 BIT(IIO_CHAN_INFO_SCALE), \ 729 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 730 .address = ADIS16480_REG_BAROM_OUT, \ 731 .scan_index = ADIS16480_SCAN_BARO, \ 732 .scan_type = { \ 733 .sign = 's', \ 734 .realbits = 32, \ 735 .storagebits = 32, \ 736 .endianness = IIO_BE, \ 737 }, \ 738 } 739 740 #define ADIS16480_TEMP_CHANNEL() { \ 741 .type = IIO_TEMP, \ 742 .indexed = 1, \ 743 .channel = 0, \ 744 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 745 BIT(IIO_CHAN_INFO_SCALE) | \ 746 BIT(IIO_CHAN_INFO_OFFSET), \ 747 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 748 .address = ADIS16480_REG_TEMP_OUT, \ 749 .scan_index = ADIS16480_SCAN_TEMP, \ 750 .scan_type = { \ 751 .sign = 's', \ 752 .realbits = 16, \ 753 .storagebits = 16, \ 754 .endianness = IIO_BE, \ 755 }, \ 756 } 757 758 static const struct iio_chan_spec adis16480_channels[] = { 759 ADIS16480_GYRO_CHANNEL(X), 760 ADIS16480_GYRO_CHANNEL(Y), 761 ADIS16480_GYRO_CHANNEL(Z), 762 ADIS16480_ACCEL_CHANNEL(X), 763 ADIS16480_ACCEL_CHANNEL(Y), 764 ADIS16480_ACCEL_CHANNEL(Z), 765 ADIS16480_MAGN_CHANNEL(X), 766 ADIS16480_MAGN_CHANNEL(Y), 767 ADIS16480_MAGN_CHANNEL(Z), 768 ADIS16480_PRESSURE_CHANNEL(), 769 ADIS16480_TEMP_CHANNEL(), 770 IIO_CHAN_SOFT_TIMESTAMP(11) 771 }; 772 773 static const struct iio_chan_spec adis16485_channels[] = { 774 ADIS16480_GYRO_CHANNEL(X), 775 ADIS16480_GYRO_CHANNEL(Y), 776 ADIS16480_GYRO_CHANNEL(Z), 777 ADIS16480_ACCEL_CHANNEL(X), 778 ADIS16480_ACCEL_CHANNEL(Y), 779 ADIS16480_ACCEL_CHANNEL(Z), 780 ADIS16480_TEMP_CHANNEL(), 781 IIO_CHAN_SOFT_TIMESTAMP(7) 782 }; 783 784 enum adis16480_variant { 785 ADIS16375, 786 ADIS16480, 787 ADIS16485, 788 ADIS16488, 789 ADIS16495_1, 790 ADIS16495_2, 791 ADIS16495_3, 792 ADIS16497_1, 793 ADIS16497_2, 794 ADIS16497_3, 795 }; 796 797 static const struct adis16480_chip_info adis16480_chip_info[] = { 798 [ADIS16375] = { 799 .channels = adis16485_channels, 800 .num_channels = ARRAY_SIZE(adis16485_channels), 801 /* 802 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 803 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 804 * it gives better approximation. However, in this case we 805 * cannot do it since it would not fit in a 32bit variable. 806 */ 807 .gyro_max_val = 22887 << 16, 808 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 809 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 810 .accel_max_scale = 18, 811 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 812 .int_clk = 2460000, 813 .max_dec_rate = 2048, 814 .filter_freqs = adis16480_def_filter_freqs, 815 }, 816 [ADIS16480] = { 817 .channels = adis16480_channels, 818 .num_channels = ARRAY_SIZE(adis16480_channels), 819 .gyro_max_val = 22500 << 16, 820 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 821 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 822 .accel_max_scale = 10, 823 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 824 .int_clk = 2460000, 825 .max_dec_rate = 2048, 826 .filter_freqs = adis16480_def_filter_freqs, 827 }, 828 [ADIS16485] = { 829 .channels = adis16485_channels, 830 .num_channels = ARRAY_SIZE(adis16485_channels), 831 .gyro_max_val = 22500 << 16, 832 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 833 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 834 .accel_max_scale = 5, 835 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 836 .int_clk = 2460000, 837 .max_dec_rate = 2048, 838 .filter_freqs = adis16480_def_filter_freqs, 839 }, 840 [ADIS16488] = { 841 .channels = adis16480_channels, 842 .num_channels = ARRAY_SIZE(adis16480_channels), 843 .gyro_max_val = 22500 << 16, 844 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 845 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 846 .accel_max_scale = 18, 847 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 848 .int_clk = 2460000, 849 .max_dec_rate = 2048, 850 .filter_freqs = adis16480_def_filter_freqs, 851 }, 852 [ADIS16495_1] = { 853 .channels = adis16485_channels, 854 .num_channels = ARRAY_SIZE(adis16485_channels), 855 .gyro_max_val = 20000 << 16, 856 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 857 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 858 .accel_max_scale = 8, 859 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 860 .int_clk = 4250000, 861 .max_dec_rate = 4250, 862 .filter_freqs = adis16495_def_filter_freqs, 863 .has_pps_clk_mode = true, 864 }, 865 [ADIS16495_2] = { 866 .channels = adis16485_channels, 867 .num_channels = ARRAY_SIZE(adis16485_channels), 868 .gyro_max_val = 18000 << 16, 869 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 870 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 871 .accel_max_scale = 8, 872 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 873 .int_clk = 4250000, 874 .max_dec_rate = 4250, 875 .filter_freqs = adis16495_def_filter_freqs, 876 .has_pps_clk_mode = true, 877 }, 878 [ADIS16495_3] = { 879 .channels = adis16485_channels, 880 .num_channels = ARRAY_SIZE(adis16485_channels), 881 .gyro_max_val = 20000 << 16, 882 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 883 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 884 .accel_max_scale = 8, 885 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 886 .int_clk = 4250000, 887 .max_dec_rate = 4250, 888 .filter_freqs = adis16495_def_filter_freqs, 889 .has_pps_clk_mode = true, 890 }, 891 [ADIS16497_1] = { 892 .channels = adis16485_channels, 893 .num_channels = ARRAY_SIZE(adis16485_channels), 894 .gyro_max_val = 20000 << 16, 895 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 896 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 897 .accel_max_scale = 40, 898 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 899 .int_clk = 4250000, 900 .max_dec_rate = 4250, 901 .filter_freqs = adis16495_def_filter_freqs, 902 .has_pps_clk_mode = true, 903 }, 904 [ADIS16497_2] = { 905 .channels = adis16485_channels, 906 .num_channels = ARRAY_SIZE(adis16485_channels), 907 .gyro_max_val = 18000 << 16, 908 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 909 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 910 .accel_max_scale = 40, 911 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 912 .int_clk = 4250000, 913 .max_dec_rate = 4250, 914 .filter_freqs = adis16495_def_filter_freqs, 915 .has_pps_clk_mode = true, 916 }, 917 [ADIS16497_3] = { 918 .channels = adis16485_channels, 919 .num_channels = ARRAY_SIZE(adis16485_channels), 920 .gyro_max_val = 20000 << 16, 921 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 922 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 923 .accel_max_scale = 40, 924 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 925 .int_clk = 4250000, 926 .max_dec_rate = 4250, 927 .filter_freqs = adis16495_def_filter_freqs, 928 .has_pps_clk_mode = true, 929 }, 930 }; 931 932 static const struct iio_info adis16480_info = { 933 .read_raw = &adis16480_read_raw, 934 .write_raw = &adis16480_write_raw, 935 .update_scan_mode = adis_update_scan_mode, 936 .debugfs_reg_access = adis_debugfs_reg_access, 937 }; 938 939 static int adis16480_stop_device(struct iio_dev *indio_dev) 940 { 941 struct adis16480 *st = iio_priv(indio_dev); 942 int ret; 943 944 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 945 if (ret) 946 dev_err(&indio_dev->dev, 947 "Could not power down device: %d\n", ret); 948 949 return ret; 950 } 951 952 static int adis16480_enable_irq(struct adis *adis, bool enable) 953 { 954 uint16_t val; 955 int ret; 956 957 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 958 if (ret) 959 return ret; 960 961 val &= ~ADIS16480_DRDY_EN_MSK; 962 val |= ADIS16480_DRDY_EN(enable); 963 964 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 965 } 966 967 static int adis16480_initial_setup(struct iio_dev *indio_dev) 968 { 969 struct adis16480 *st = iio_priv(indio_dev); 970 uint16_t prod_id; 971 unsigned int device_id; 972 int ret; 973 974 adis_reset(&st->adis); 975 msleep(70); 976 977 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1)); 978 if (ret) 979 return ret; 980 msleep(30); 981 982 ret = adis_check_status(&st->adis); 983 if (ret) 984 return ret; 985 986 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id); 987 if (ret) 988 return ret; 989 990 ret = sscanf(indio_dev->name, "adis%u\n", &device_id); 991 if (ret != 1) 992 return -EINVAL; 993 994 if (prod_id != device_id) 995 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.", 996 device_id, prod_id); 997 998 return 0; 999 } 1000 1001 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 1002 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 1003 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 1004 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 1005 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 1006 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 1007 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 1008 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 1009 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 1010 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 1011 1012 static const char * const adis16480_status_error_msgs[] = { 1013 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 1014 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 1015 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 1016 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 1017 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 1018 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 1019 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 1020 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 1021 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 1022 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 1023 }; 1024 1025 static const struct adis_data adis16480_data = { 1026 .diag_stat_reg = ADIS16480_REG_DIAG_STS, 1027 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, 1028 .has_paging = true, 1029 1030 .read_delay = 5, 1031 .write_delay = 5, 1032 1033 .status_error_msgs = adis16480_status_error_msgs, 1034 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | 1035 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | 1036 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | 1037 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | 1038 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | 1039 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | 1040 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | 1041 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | 1042 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | 1043 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), 1044 1045 .enable_irq = adis16480_enable_irq, 1046 }; 1047 1048 static int adis16480_config_irq_pin(struct device_node *of_node, 1049 struct adis16480 *st) 1050 { 1051 struct irq_data *desc; 1052 enum adis16480_int_pin pin; 1053 unsigned int irq_type; 1054 uint16_t val; 1055 int i, irq = 0; 1056 1057 desc = irq_get_irq_data(st->adis.spi->irq); 1058 if (!desc) { 1059 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1060 return -EINVAL; 1061 } 1062 1063 /* Disable data ready since the default after reset is on */ 1064 val = ADIS16480_DRDY_EN(0); 1065 1066 /* 1067 * Get the interrupt from the devicetre by reading the interrupt-names 1068 * property. If it is not specified, use DIO1 pin as default. 1069 * According to the datasheet, the factory default assigns DIO2 as data 1070 * ready signal. However, in the previous versions of the driver, DIO1 1071 * pin was used. So, we should leave it as is since some devices might 1072 * be expecting the interrupt on the wrong physical pin. 1073 */ 1074 pin = ADIS16480_PIN_DIO1; 1075 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1076 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1077 if (irq > 0) { 1078 pin = i; 1079 break; 1080 } 1081 } 1082 1083 val |= ADIS16480_DRDY_SEL(pin); 1084 1085 /* 1086 * Get the interrupt line behaviour. The data ready polarity can be 1087 * configured as positive or negative, corresponding to 1088 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. 1089 */ 1090 irq_type = irqd_get_trigger_type(desc); 1091 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ 1092 val |= ADIS16480_DRDY_POL(1); 1093 } else if (irq_type == IRQF_TRIGGER_FALLING) { 1094 val |= ADIS16480_DRDY_POL(0); 1095 } else { 1096 dev_err(&st->adis.spi->dev, 1097 "Invalid interrupt type 0x%x specified\n", irq_type); 1098 return -EINVAL; 1099 } 1100 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1101 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1102 } 1103 1104 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1105 struct device_node *of_node) 1106 { 1107 const char *ext_clk_pin; 1108 enum adis16480_int_pin pin; 1109 int i; 1110 1111 pin = ADIS16480_PIN_DIO2; 1112 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1113 goto clk_input_not_found; 1114 1115 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1116 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1117 return i; 1118 } 1119 1120 clk_input_not_found: 1121 dev_info(&st->adis.spi->dev, 1122 "clk input line not specified, using DIO2\n"); 1123 return pin; 1124 } 1125 1126 static int adis16480_ext_clk_config(struct adis16480 *st, 1127 struct device_node *of_node, 1128 bool enable) 1129 { 1130 unsigned int mode, mask; 1131 enum adis16480_int_pin pin; 1132 uint16_t val; 1133 int ret; 1134 1135 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1136 if (ret) 1137 return ret; 1138 1139 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1140 /* 1141 * Each DIOx pin supports only one function at a time. When a single pin 1142 * has two assignments, the enable bit for a lower priority function 1143 * automatically resets to zero (disabling the lower priority function). 1144 */ 1145 if (pin == ADIS16480_DRDY_SEL(val)) 1146 dev_warn(&st->adis.spi->dev, 1147 "DIO%x pin supports only one function at a time\n", 1148 pin + 1); 1149 1150 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1151 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1152 /* Only ADIS1649x devices support pps ext clock mode */ 1153 if (st->chip_info->has_pps_clk_mode) { 1154 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1155 mask |= ADIS16480_SYNC_MODE_MSK; 1156 } 1157 1158 val &= ~mask; 1159 val |= mode; 1160 1161 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1162 if (ret) 1163 return ret; 1164 1165 return clk_prepare_enable(st->ext_clk); 1166 } 1167 1168 static int adis16480_get_ext_clocks(struct adis16480 *st) 1169 { 1170 st->clk_mode = ADIS16480_CLK_INT; 1171 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1172 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1173 st->clk_mode = ADIS16480_CLK_SYNC; 1174 return 0; 1175 } 1176 1177 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1178 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1179 return PTR_ERR(st->ext_clk); 1180 } 1181 1182 if (st->chip_info->has_pps_clk_mode) { 1183 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1184 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1185 st->clk_mode = ADIS16480_CLK_PPS; 1186 return 0; 1187 } 1188 1189 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1190 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1191 return PTR_ERR(st->ext_clk); 1192 } 1193 } 1194 1195 return 0; 1196 } 1197 1198 static int adis16480_probe(struct spi_device *spi) 1199 { 1200 const struct spi_device_id *id = spi_get_device_id(spi); 1201 struct iio_dev *indio_dev; 1202 struct adis16480 *st; 1203 int ret; 1204 1205 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1206 if (indio_dev == NULL) 1207 return -ENOMEM; 1208 1209 spi_set_drvdata(spi, indio_dev); 1210 1211 st = iio_priv(indio_dev); 1212 1213 st->chip_info = &adis16480_chip_info[id->driver_data]; 1214 indio_dev->dev.parent = &spi->dev; 1215 indio_dev->name = spi_get_device_id(spi)->name; 1216 indio_dev->channels = st->chip_info->channels; 1217 indio_dev->num_channels = st->chip_info->num_channels; 1218 indio_dev->info = &adis16480_info; 1219 indio_dev->modes = INDIO_DIRECT_MODE; 1220 1221 ret = adis_init(&st->adis, indio_dev, spi, &adis16480_data); 1222 if (ret) 1223 return ret; 1224 1225 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1226 if (ret) 1227 return ret; 1228 1229 ret = adis16480_get_ext_clocks(st); 1230 if (ret) 1231 return ret; 1232 1233 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1234 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1235 if (ret) 1236 return ret; 1237 1238 st->clk_freq = clk_get_rate(st->ext_clk); 1239 st->clk_freq *= 1000; /* micro */ 1240 } else { 1241 st->clk_freq = st->chip_info->int_clk; 1242 } 1243 1244 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1245 if (ret) 1246 goto error_clk_disable_unprepare; 1247 1248 ret = adis16480_initial_setup(indio_dev); 1249 if (ret) 1250 goto error_cleanup_buffer; 1251 1252 ret = iio_device_register(indio_dev); 1253 if (ret) 1254 goto error_stop_device; 1255 1256 adis16480_debugfs_init(indio_dev); 1257 1258 return 0; 1259 1260 error_stop_device: 1261 adis16480_stop_device(indio_dev); 1262 error_cleanup_buffer: 1263 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1264 error_clk_disable_unprepare: 1265 clk_disable_unprepare(st->ext_clk); 1266 return ret; 1267 } 1268 1269 static int adis16480_remove(struct spi_device *spi) 1270 { 1271 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1272 struct adis16480 *st = iio_priv(indio_dev); 1273 1274 iio_device_unregister(indio_dev); 1275 adis16480_stop_device(indio_dev); 1276 1277 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1278 clk_disable_unprepare(st->ext_clk); 1279 1280 return 0; 1281 } 1282 1283 static const struct spi_device_id adis16480_ids[] = { 1284 { "adis16375", ADIS16375 }, 1285 { "adis16480", ADIS16480 }, 1286 { "adis16485", ADIS16485 }, 1287 { "adis16488", ADIS16488 }, 1288 { "adis16495-1", ADIS16495_1 }, 1289 { "adis16495-2", ADIS16495_2 }, 1290 { "adis16495-3", ADIS16495_3 }, 1291 { "adis16497-1", ADIS16497_1 }, 1292 { "adis16497-2", ADIS16497_2 }, 1293 { "adis16497-3", ADIS16497_3 }, 1294 { } 1295 }; 1296 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1297 1298 static const struct of_device_id adis16480_of_match[] = { 1299 { .compatible = "adi,adis16375" }, 1300 { .compatible = "adi,adis16480" }, 1301 { .compatible = "adi,adis16485" }, 1302 { .compatible = "adi,adis16488" }, 1303 { .compatible = "adi,adis16495-1" }, 1304 { .compatible = "adi,adis16495-2" }, 1305 { .compatible = "adi,adis16495-3" }, 1306 { .compatible = "adi,adis16497-1" }, 1307 { .compatible = "adi,adis16497-2" }, 1308 { .compatible = "adi,adis16497-3" }, 1309 { }, 1310 }; 1311 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1312 1313 static struct spi_driver adis16480_driver = { 1314 .driver = { 1315 .name = "adis16480", 1316 .of_match_table = adis16480_of_match, 1317 }, 1318 .id_table = adis16480_ids, 1319 .probe = adis16480_probe, 1320 .remove = adis16480_remove, 1321 }; 1322 module_spi_driver(adis16480_driver); 1323 1324 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1325 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1326 MODULE_LICENSE("GPL v2"); 1327