1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/math.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/spi/spi.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/lcm.h> 19 #include <linux/property.h> 20 #include <linux/swab.h> 21 #include <linux/crc32.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/imu/adis.h> 26 #include <linux/iio/trigger_consumer.h> 27 28 #include <linux/debugfs.h> 29 30 #define ADIS16480_PAGE_SIZE 0x80 31 32 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 33 34 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 35 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 36 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 37 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 38 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 39 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 40 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 41 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 42 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 43 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 44 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 45 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 46 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 47 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 48 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 49 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 50 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 51 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 52 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 53 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 54 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 55 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 56 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 57 58 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 59 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 60 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 61 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 62 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 63 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 64 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 65 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 66 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 67 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 68 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 69 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 70 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 71 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 72 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 73 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 74 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 75 76 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 77 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 78 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 79 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 80 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 81 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 82 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 83 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 84 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 85 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 86 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 87 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 88 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 89 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 90 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 91 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 92 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 93 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 94 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 95 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 96 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 97 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 98 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 99 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 100 101 /* 102 * External clock scaling in PPS mode. 103 * Available only for ADIS1649x devices 104 */ 105 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 106 #define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C) 107 #define ADIS16495_BURST_ID 0xA5A5 108 /* total number of segments in burst */ 109 #define ADIS16495_BURST_MAX_DATA 20 110 /* spi max speed in burst mode */ 111 #define ADIS16495_BURST_MAX_SPEED 6000000 112 113 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 114 115 /* Each filter coefficent bank spans two pages */ 116 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 117 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 118 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 119 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 120 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 121 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 122 123 /* ADIS16480_REG_FNCTIO_CTRL */ 124 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 125 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 126 #define ADIS16480_DRDY_POL_MSK BIT(2) 127 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 128 #define ADIS16480_DRDY_EN_MSK BIT(3) 129 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 130 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 131 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 132 #define ADIS16480_SYNC_EN_MSK BIT(7) 133 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 134 #define ADIS16480_SYNC_MODE_MSK BIT(8) 135 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 136 137 struct adis16480_chip_info { 138 unsigned int num_channels; 139 const struct iio_chan_spec *channels; 140 unsigned int gyro_max_val; 141 unsigned int gyro_max_scale; 142 unsigned int accel_max_val; 143 unsigned int accel_max_scale; 144 unsigned int temp_scale; 145 unsigned int int_clk; 146 unsigned int max_dec_rate; 147 const unsigned int *filter_freqs; 148 bool has_pps_clk_mode; 149 bool has_sleep_cnt; 150 const struct adis_data adis_data; 151 }; 152 153 enum adis16480_int_pin { 154 ADIS16480_PIN_DIO1, 155 ADIS16480_PIN_DIO2, 156 ADIS16480_PIN_DIO3, 157 ADIS16480_PIN_DIO4 158 }; 159 160 enum adis16480_clock_mode { 161 ADIS16480_CLK_SYNC, 162 ADIS16480_CLK_PPS, 163 ADIS16480_CLK_INT 164 }; 165 166 struct adis16480 { 167 const struct adis16480_chip_info *chip_info; 168 169 struct adis adis; 170 struct clk *ext_clk; 171 enum adis16480_clock_mode clk_mode; 172 unsigned int clk_freq; 173 /* Alignment needed for the timestamp */ 174 __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8); 175 }; 176 177 static const char * const adis16480_int_pin_names[4] = { 178 [ADIS16480_PIN_DIO1] = "DIO1", 179 [ADIS16480_PIN_DIO2] = "DIO2", 180 [ADIS16480_PIN_DIO3] = "DIO3", 181 [ADIS16480_PIN_DIO4] = "DIO4", 182 }; 183 184 static bool low_rate_allow; 185 module_param(low_rate_allow, bool, 0444); 186 MODULE_PARM_DESC(low_rate_allow, 187 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)"); 188 189 #ifdef CONFIG_DEBUG_FS 190 191 static ssize_t adis16480_show_firmware_revision(struct file *file, 192 char __user *userbuf, size_t count, loff_t *ppos) 193 { 194 struct adis16480 *adis16480 = file->private_data; 195 char buf[7]; 196 size_t len; 197 u16 rev; 198 int ret; 199 200 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 201 if (ret) 202 return ret; 203 204 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 205 206 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 207 } 208 209 static const struct file_operations adis16480_firmware_revision_fops = { 210 .open = simple_open, 211 .read = adis16480_show_firmware_revision, 212 .llseek = default_llseek, 213 .owner = THIS_MODULE, 214 }; 215 216 static ssize_t adis16480_show_firmware_date(struct file *file, 217 char __user *userbuf, size_t count, loff_t *ppos) 218 { 219 struct adis16480 *adis16480 = file->private_data; 220 u16 md, year; 221 char buf[12]; 222 size_t len; 223 int ret; 224 225 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 226 if (ret) 227 return ret; 228 229 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 230 if (ret) 231 return ret; 232 233 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 234 md >> 8, md & 0xff, year); 235 236 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 237 } 238 239 static const struct file_operations adis16480_firmware_date_fops = { 240 .open = simple_open, 241 .read = adis16480_show_firmware_date, 242 .llseek = default_llseek, 243 .owner = THIS_MODULE, 244 }; 245 246 static int adis16480_show_serial_number(void *arg, u64 *val) 247 { 248 struct adis16480 *adis16480 = arg; 249 u16 serial; 250 int ret; 251 252 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 253 &serial); 254 if (ret) 255 return ret; 256 257 *val = serial; 258 259 return 0; 260 } 261 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 262 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 263 264 static int adis16480_show_product_id(void *arg, u64 *val) 265 { 266 struct adis16480 *adis16480 = arg; 267 u16 prod_id; 268 int ret; 269 270 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 271 &prod_id); 272 if (ret) 273 return ret; 274 275 *val = prod_id; 276 277 return 0; 278 } 279 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 280 adis16480_show_product_id, NULL, "%llu\n"); 281 282 static int adis16480_show_flash_count(void *arg, u64 *val) 283 { 284 struct adis16480 *adis16480 = arg; 285 u32 flash_count; 286 int ret; 287 288 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 289 &flash_count); 290 if (ret) 291 return ret; 292 293 *val = flash_count; 294 295 return 0; 296 } 297 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 298 adis16480_show_flash_count, NULL, "%lld\n"); 299 300 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 301 { 302 struct adis16480 *adis16480 = iio_priv(indio_dev); 303 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 304 305 debugfs_create_file_unsafe("firmware_revision", 0400, 306 d, adis16480, &adis16480_firmware_revision_fops); 307 debugfs_create_file_unsafe("firmware_date", 0400, 308 d, adis16480, &adis16480_firmware_date_fops); 309 debugfs_create_file_unsafe("serial_number", 0400, 310 d, adis16480, &adis16480_serial_number_fops); 311 debugfs_create_file_unsafe("product_id", 0400, 312 d, adis16480, &adis16480_product_id_fops); 313 debugfs_create_file_unsafe("flash_count", 0400, 314 d, adis16480, &adis16480_flash_count_fops); 315 316 return 0; 317 } 318 319 #else 320 321 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 322 { 323 return 0; 324 } 325 326 #endif 327 328 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 329 { 330 struct adis16480 *st = iio_priv(indio_dev); 331 unsigned int t, sample_rate = st->clk_freq; 332 int ret; 333 334 if (val < 0 || val2 < 0) 335 return -EINVAL; 336 337 t = val * 1000 + val2 / 1000; 338 if (t == 0) 339 return -EINVAL; 340 341 adis_dev_lock(&st->adis); 342 /* 343 * When using PPS mode, the input clock needs to be scaled so that we have an IMU 344 * sample rate between (optimally) 4000 and 4250. After this, we can use the 345 * decimation filter to lower the sampling rate in order to get what the user wants. 346 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 347 * the input clock. Hence, calculating the sync_scale dynamically gives us better 348 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 349 * 1. lcm of the input clock and the desired output rate. 350 * 2. get the highest multiple of the previous result lower than the adis max rate. 351 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 352 * and DEC_RATE (to get the user output rate) 353 */ 354 if (st->clk_mode == ADIS16480_CLK_PPS) { 355 unsigned long scaled_rate = lcm(st->clk_freq, t); 356 int sync_scale; 357 358 /* 359 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 360 * solution. In this case, we get the highest multiple of the input clock 361 * lower than the IMU max sample rate. 362 */ 363 if (scaled_rate > st->chip_info->int_clk) 364 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq; 365 else 366 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate; 367 368 /* 369 * This is not an hard requirement but it's not advised to run the IMU 370 * with a sample rate lower than 4000Hz due to possible undersampling 371 * issues. However, there are users that might really want to take the risk. 372 * Hence, we provide a module parameter for them. If set, we allow sample 373 * rates lower than 4KHz. By default, we won't allow this and we just roundup 374 * the rate to the next multiple of the input clock bigger than 4KHz. This 375 * is done like this as in some cases (when DEC_RATE is 0) might give 376 * us the closest value to the one desired by the user... 377 */ 378 if (scaled_rate < 4000000 && !low_rate_allow) 379 scaled_rate = roundup(4000000, st->clk_freq); 380 381 sync_scale = scaled_rate / st->clk_freq; 382 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 383 if (ret) 384 goto error; 385 386 sample_rate = scaled_rate; 387 } 388 389 t = DIV_ROUND_CLOSEST(sample_rate, t); 390 if (t) 391 t--; 392 393 if (t > st->chip_info->max_dec_rate) 394 t = st->chip_info->max_dec_rate; 395 396 ret = __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t); 397 error: 398 adis_dev_unlock(&st->adis); 399 return ret; 400 } 401 402 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 403 { 404 struct adis16480 *st = iio_priv(indio_dev); 405 uint16_t t; 406 int ret; 407 unsigned int freq, sample_rate = st->clk_freq; 408 409 adis_dev_lock(&st->adis); 410 411 if (st->clk_mode == ADIS16480_CLK_PPS) { 412 u16 sync_scale; 413 414 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale); 415 if (ret) 416 goto error; 417 418 sample_rate = st->clk_freq * sync_scale; 419 } 420 421 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t); 422 if (ret) 423 goto error; 424 425 adis_dev_unlock(&st->adis); 426 427 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1)); 428 429 *val = freq / 1000; 430 *val2 = (freq % 1000) * 1000; 431 432 return IIO_VAL_INT_PLUS_MICRO; 433 error: 434 adis_dev_unlock(&st->adis); 435 return ret; 436 } 437 438 enum { 439 ADIS16480_SCAN_GYRO_X, 440 ADIS16480_SCAN_GYRO_Y, 441 ADIS16480_SCAN_GYRO_Z, 442 ADIS16480_SCAN_ACCEL_X, 443 ADIS16480_SCAN_ACCEL_Y, 444 ADIS16480_SCAN_ACCEL_Z, 445 ADIS16480_SCAN_MAGN_X, 446 ADIS16480_SCAN_MAGN_Y, 447 ADIS16480_SCAN_MAGN_Z, 448 ADIS16480_SCAN_BARO, 449 ADIS16480_SCAN_TEMP, 450 }; 451 452 static const unsigned int adis16480_calibbias_regs[] = { 453 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 454 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 455 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 456 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 457 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 458 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 459 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 460 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 461 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 462 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 463 }; 464 465 static const unsigned int adis16480_calibscale_regs[] = { 466 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 467 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 468 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 469 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 470 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 471 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 472 }; 473 474 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 475 const struct iio_chan_spec *chan, int bias) 476 { 477 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 478 struct adis16480 *st = iio_priv(indio_dev); 479 480 switch (chan->type) { 481 case IIO_MAGN: 482 case IIO_PRESSURE: 483 if (bias < -0x8000 || bias >= 0x8000) 484 return -EINVAL; 485 return adis_write_reg_16(&st->adis, reg, bias); 486 case IIO_ANGL_VEL: 487 case IIO_ACCEL: 488 return adis_write_reg_32(&st->adis, reg, bias); 489 default: 490 break; 491 } 492 493 return -EINVAL; 494 } 495 496 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 497 const struct iio_chan_spec *chan, int *bias) 498 { 499 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 500 struct adis16480 *st = iio_priv(indio_dev); 501 uint16_t val16; 502 uint32_t val32; 503 int ret; 504 505 switch (chan->type) { 506 case IIO_MAGN: 507 case IIO_PRESSURE: 508 ret = adis_read_reg_16(&st->adis, reg, &val16); 509 if (ret == 0) 510 *bias = sign_extend32(val16, 15); 511 break; 512 case IIO_ANGL_VEL: 513 case IIO_ACCEL: 514 ret = adis_read_reg_32(&st->adis, reg, &val32); 515 if (ret == 0) 516 *bias = sign_extend32(val32, 31); 517 break; 518 default: 519 ret = -EINVAL; 520 } 521 522 if (ret) 523 return ret; 524 525 return IIO_VAL_INT; 526 } 527 528 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 529 const struct iio_chan_spec *chan, int scale) 530 { 531 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 532 struct adis16480 *st = iio_priv(indio_dev); 533 534 if (scale < -0x8000 || scale >= 0x8000) 535 return -EINVAL; 536 537 return adis_write_reg_16(&st->adis, reg, scale); 538 } 539 540 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 541 const struct iio_chan_spec *chan, int *scale) 542 { 543 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 544 struct adis16480 *st = iio_priv(indio_dev); 545 uint16_t val16; 546 int ret; 547 548 ret = adis_read_reg_16(&st->adis, reg, &val16); 549 if (ret) 550 return ret; 551 552 *scale = sign_extend32(val16, 15); 553 return IIO_VAL_INT; 554 } 555 556 static const unsigned int adis16480_def_filter_freqs[] = { 557 310, 558 55, 559 275, 560 63, 561 }; 562 563 static const unsigned int adis16495_def_filter_freqs[] = { 564 300, 565 100, 566 300, 567 100, 568 }; 569 570 static const unsigned int ad16480_filter_data[][2] = { 571 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 572 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 573 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 574 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 575 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 576 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 577 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 578 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 579 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 580 }; 581 582 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 583 const struct iio_chan_spec *chan, int *freq) 584 { 585 struct adis16480 *st = iio_priv(indio_dev); 586 unsigned int enable_mask, offset, reg; 587 uint16_t val; 588 int ret; 589 590 reg = ad16480_filter_data[chan->scan_index][0]; 591 offset = ad16480_filter_data[chan->scan_index][1]; 592 enable_mask = BIT(offset + 2); 593 594 ret = adis_read_reg_16(&st->adis, reg, &val); 595 if (ret) 596 return ret; 597 598 if (!(val & enable_mask)) 599 *freq = 0; 600 else 601 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 602 603 return IIO_VAL_INT; 604 } 605 606 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 607 const struct iio_chan_spec *chan, unsigned int freq) 608 { 609 struct adis16480 *st = iio_priv(indio_dev); 610 unsigned int enable_mask, offset, reg; 611 unsigned int diff, best_diff; 612 unsigned int i, best_freq; 613 uint16_t val; 614 int ret; 615 616 reg = ad16480_filter_data[chan->scan_index][0]; 617 offset = ad16480_filter_data[chan->scan_index][1]; 618 enable_mask = BIT(offset + 2); 619 620 adis_dev_lock(&st->adis); 621 622 ret = __adis_read_reg_16(&st->adis, reg, &val); 623 if (ret) 624 goto out_unlock; 625 626 if (freq == 0) { 627 val &= ~enable_mask; 628 } else { 629 best_freq = 0; 630 best_diff = st->chip_info->filter_freqs[0]; 631 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 632 if (st->chip_info->filter_freqs[i] >= freq) { 633 diff = st->chip_info->filter_freqs[i] - freq; 634 if (diff < best_diff) { 635 best_diff = diff; 636 best_freq = i; 637 } 638 } 639 } 640 641 val &= ~(0x3 << offset); 642 val |= best_freq << offset; 643 val |= enable_mask; 644 } 645 646 ret = __adis_write_reg_16(&st->adis, reg, val); 647 out_unlock: 648 adis_dev_unlock(&st->adis); 649 650 return ret; 651 } 652 653 static int adis16480_read_raw(struct iio_dev *indio_dev, 654 const struct iio_chan_spec *chan, int *val, int *val2, long info) 655 { 656 struct adis16480 *st = iio_priv(indio_dev); 657 unsigned int temp; 658 659 switch (info) { 660 case IIO_CHAN_INFO_RAW: 661 return adis_single_conversion(indio_dev, chan, 0, val); 662 case IIO_CHAN_INFO_SCALE: 663 switch (chan->type) { 664 case IIO_ANGL_VEL: 665 *val = st->chip_info->gyro_max_scale; 666 *val2 = st->chip_info->gyro_max_val; 667 return IIO_VAL_FRACTIONAL; 668 case IIO_ACCEL: 669 *val = st->chip_info->accel_max_scale; 670 *val2 = st->chip_info->accel_max_val; 671 return IIO_VAL_FRACTIONAL; 672 case IIO_MAGN: 673 *val = 0; 674 *val2 = 100; /* 0.0001 gauss */ 675 return IIO_VAL_INT_PLUS_MICRO; 676 case IIO_TEMP: 677 /* 678 * +85 degrees Celsius = temp_max_scale 679 * +25 degrees Celsius = 0 680 * LSB, 25 degrees Celsius = 60 / temp_max_scale 681 */ 682 *val = st->chip_info->temp_scale / 1000; 683 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 684 return IIO_VAL_INT_PLUS_MICRO; 685 case IIO_PRESSURE: 686 /* 687 * max scale is 1310 mbar 688 * max raw value is 32767 shifted for 32bits 689 */ 690 *val = 131; /* 1310mbar = 131 kPa */ 691 *val2 = 32767 << 16; 692 return IIO_VAL_FRACTIONAL; 693 default: 694 return -EINVAL; 695 } 696 case IIO_CHAN_INFO_OFFSET: 697 /* Only the temperature channel has a offset */ 698 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 699 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 700 return IIO_VAL_INT; 701 case IIO_CHAN_INFO_CALIBBIAS: 702 return adis16480_get_calibbias(indio_dev, chan, val); 703 case IIO_CHAN_INFO_CALIBSCALE: 704 return adis16480_get_calibscale(indio_dev, chan, val); 705 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 706 return adis16480_get_filter_freq(indio_dev, chan, val); 707 case IIO_CHAN_INFO_SAMP_FREQ: 708 return adis16480_get_freq(indio_dev, val, val2); 709 default: 710 return -EINVAL; 711 } 712 } 713 714 static int adis16480_write_raw(struct iio_dev *indio_dev, 715 const struct iio_chan_spec *chan, int val, int val2, long info) 716 { 717 switch (info) { 718 case IIO_CHAN_INFO_CALIBBIAS: 719 return adis16480_set_calibbias(indio_dev, chan, val); 720 case IIO_CHAN_INFO_CALIBSCALE: 721 return adis16480_set_calibscale(indio_dev, chan, val); 722 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 723 return adis16480_set_filter_freq(indio_dev, chan, val); 724 case IIO_CHAN_INFO_SAMP_FREQ: 725 return adis16480_set_freq(indio_dev, val, val2); 726 727 default: 728 return -EINVAL; 729 } 730 } 731 732 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 733 { \ 734 .type = (_type), \ 735 .modified = 1, \ 736 .channel2 = (_mod), \ 737 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 738 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 739 _info_sep, \ 740 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 741 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 742 .address = (_address), \ 743 .scan_index = (_si), \ 744 .scan_type = { \ 745 .sign = 's', \ 746 .realbits = (_bits), \ 747 .storagebits = (_bits), \ 748 .endianness = IIO_BE, \ 749 }, \ 750 } 751 752 #define ADIS16480_GYRO_CHANNEL(_mod) \ 753 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 754 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 755 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 756 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 757 32) 758 759 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 760 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 761 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 762 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 763 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 764 32) 765 766 #define ADIS16480_MAGN_CHANNEL(_mod) \ 767 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 768 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 769 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 770 16) 771 772 #define ADIS16480_PRESSURE_CHANNEL() \ 773 { \ 774 .type = IIO_PRESSURE, \ 775 .indexed = 1, \ 776 .channel = 0, \ 777 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 778 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 779 BIT(IIO_CHAN_INFO_SCALE), \ 780 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 781 .address = ADIS16480_REG_BAROM_OUT, \ 782 .scan_index = ADIS16480_SCAN_BARO, \ 783 .scan_type = { \ 784 .sign = 's', \ 785 .realbits = 32, \ 786 .storagebits = 32, \ 787 .endianness = IIO_BE, \ 788 }, \ 789 } 790 791 #define ADIS16480_TEMP_CHANNEL() { \ 792 .type = IIO_TEMP, \ 793 .indexed = 1, \ 794 .channel = 0, \ 795 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 796 BIT(IIO_CHAN_INFO_SCALE) | \ 797 BIT(IIO_CHAN_INFO_OFFSET), \ 798 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 799 .address = ADIS16480_REG_TEMP_OUT, \ 800 .scan_index = ADIS16480_SCAN_TEMP, \ 801 .scan_type = { \ 802 .sign = 's', \ 803 .realbits = 16, \ 804 .storagebits = 16, \ 805 .endianness = IIO_BE, \ 806 }, \ 807 } 808 809 static const struct iio_chan_spec adis16480_channels[] = { 810 ADIS16480_GYRO_CHANNEL(X), 811 ADIS16480_GYRO_CHANNEL(Y), 812 ADIS16480_GYRO_CHANNEL(Z), 813 ADIS16480_ACCEL_CHANNEL(X), 814 ADIS16480_ACCEL_CHANNEL(Y), 815 ADIS16480_ACCEL_CHANNEL(Z), 816 ADIS16480_MAGN_CHANNEL(X), 817 ADIS16480_MAGN_CHANNEL(Y), 818 ADIS16480_MAGN_CHANNEL(Z), 819 ADIS16480_PRESSURE_CHANNEL(), 820 ADIS16480_TEMP_CHANNEL(), 821 IIO_CHAN_SOFT_TIMESTAMP(11) 822 }; 823 824 static const struct iio_chan_spec adis16485_channels[] = { 825 ADIS16480_GYRO_CHANNEL(X), 826 ADIS16480_GYRO_CHANNEL(Y), 827 ADIS16480_GYRO_CHANNEL(Z), 828 ADIS16480_ACCEL_CHANNEL(X), 829 ADIS16480_ACCEL_CHANNEL(Y), 830 ADIS16480_ACCEL_CHANNEL(Z), 831 ADIS16480_TEMP_CHANNEL(), 832 IIO_CHAN_SOFT_TIMESTAMP(7) 833 }; 834 835 enum adis16480_variant { 836 ADIS16375, 837 ADIS16480, 838 ADIS16485, 839 ADIS16488, 840 ADIS16490, 841 ADIS16495_1, 842 ADIS16495_2, 843 ADIS16495_3, 844 ADIS16497_1, 845 ADIS16497_2, 846 ADIS16497_3, 847 }; 848 849 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 850 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 851 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 852 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 853 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 854 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 855 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 856 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 857 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 858 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 859 860 static const char * const adis16480_status_error_msgs[] = { 861 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 862 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 863 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 864 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 865 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 866 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 867 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 868 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 869 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 870 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 871 }; 872 873 static int adis16480_enable_irq(struct adis *adis, bool enable); 874 875 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len) \ 876 { \ 877 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 878 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 879 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 880 .prod_id = (_prod_id), \ 881 .has_paging = true, \ 882 .read_delay = 5, \ 883 .write_delay = 5, \ 884 .self_test_mask = BIT(1), \ 885 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 886 .status_error_msgs = adis16480_status_error_msgs, \ 887 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 888 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 889 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 890 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 891 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 892 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 893 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 894 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 895 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 896 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 897 .enable_irq = adis16480_enable_irq, \ 898 .timeouts = (_timeouts), \ 899 .burst_reg_cmd = ADIS16495_REG_BURST_CMD, \ 900 .burst_len = (_burst_len), \ 901 .burst_max_speed_hz = ADIS16495_BURST_MAX_SPEED \ 902 } 903 904 static const struct adis_timeout adis16485_timeouts = { 905 .reset_ms = 560, 906 .sw_reset_ms = 120, 907 .self_test_ms = 12, 908 }; 909 910 static const struct adis_timeout adis16480_timeouts = { 911 .reset_ms = 560, 912 .sw_reset_ms = 560, 913 .self_test_ms = 12, 914 }; 915 916 static const struct adis_timeout adis16495_timeouts = { 917 .reset_ms = 170, 918 .sw_reset_ms = 130, 919 .self_test_ms = 40, 920 }; 921 922 static const struct adis_timeout adis16495_1_timeouts = { 923 .reset_ms = 250, 924 .sw_reset_ms = 210, 925 .self_test_ms = 20, 926 }; 927 928 static const struct adis16480_chip_info adis16480_chip_info[] = { 929 [ADIS16375] = { 930 .channels = adis16485_channels, 931 .num_channels = ARRAY_SIZE(adis16485_channels), 932 /* 933 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 934 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 935 * it gives better approximation. However, in this case we 936 * cannot do it since it would not fit in a 32bit variable. 937 */ 938 .gyro_max_val = 22887 << 16, 939 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 940 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 941 .accel_max_scale = 18, 942 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 943 .int_clk = 2460000, 944 .max_dec_rate = 2048, 945 .has_sleep_cnt = true, 946 .filter_freqs = adis16480_def_filter_freqs, 947 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0), 948 }, 949 [ADIS16480] = { 950 .channels = adis16480_channels, 951 .num_channels = ARRAY_SIZE(adis16480_channels), 952 .gyro_max_val = 22500 << 16, 953 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 954 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 955 .accel_max_scale = 10, 956 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 957 .int_clk = 2460000, 958 .max_dec_rate = 2048, 959 .has_sleep_cnt = true, 960 .filter_freqs = adis16480_def_filter_freqs, 961 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0), 962 }, 963 [ADIS16485] = { 964 .channels = adis16485_channels, 965 .num_channels = ARRAY_SIZE(adis16485_channels), 966 .gyro_max_val = 22500 << 16, 967 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 968 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 969 .accel_max_scale = 5, 970 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 971 .int_clk = 2460000, 972 .max_dec_rate = 2048, 973 .has_sleep_cnt = true, 974 .filter_freqs = adis16480_def_filter_freqs, 975 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0), 976 }, 977 [ADIS16488] = { 978 .channels = adis16480_channels, 979 .num_channels = ARRAY_SIZE(adis16480_channels), 980 .gyro_max_val = 22500 << 16, 981 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 982 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 983 .accel_max_scale = 18, 984 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 985 .int_clk = 2460000, 986 .max_dec_rate = 2048, 987 .has_sleep_cnt = true, 988 .filter_freqs = adis16480_def_filter_freqs, 989 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0), 990 }, 991 [ADIS16490] = { 992 .channels = adis16485_channels, 993 .num_channels = ARRAY_SIZE(adis16485_channels), 994 .gyro_max_val = 20000 << 16, 995 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 996 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 997 .accel_max_scale = 8, 998 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 999 .int_clk = 4250000, 1000 .max_dec_rate = 4250, 1001 .filter_freqs = adis16495_def_filter_freqs, 1002 .has_pps_clk_mode = true, 1003 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0), 1004 }, 1005 [ADIS16495_1] = { 1006 .channels = adis16485_channels, 1007 .num_channels = ARRAY_SIZE(adis16485_channels), 1008 .gyro_max_val = 20000 << 16, 1009 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1010 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1011 .accel_max_scale = 8, 1012 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1013 .int_clk = 4250000, 1014 .max_dec_rate = 4250, 1015 .filter_freqs = adis16495_def_filter_freqs, 1016 .has_pps_clk_mode = true, 1017 /* 20 elements of 16bits */ 1018 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1019 ADIS16495_BURST_MAX_DATA * 2), 1020 }, 1021 [ADIS16495_2] = { 1022 .channels = adis16485_channels, 1023 .num_channels = ARRAY_SIZE(adis16485_channels), 1024 .gyro_max_val = 18000 << 16, 1025 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1026 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1027 .accel_max_scale = 8, 1028 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1029 .int_clk = 4250000, 1030 .max_dec_rate = 4250, 1031 .filter_freqs = adis16495_def_filter_freqs, 1032 .has_pps_clk_mode = true, 1033 /* 20 elements of 16bits */ 1034 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1035 ADIS16495_BURST_MAX_DATA * 2), 1036 }, 1037 [ADIS16495_3] = { 1038 .channels = adis16485_channels, 1039 .num_channels = ARRAY_SIZE(adis16485_channels), 1040 .gyro_max_val = 20000 << 16, 1041 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1042 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1043 .accel_max_scale = 8, 1044 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1045 .int_clk = 4250000, 1046 .max_dec_rate = 4250, 1047 .filter_freqs = adis16495_def_filter_freqs, 1048 .has_pps_clk_mode = true, 1049 /* 20 elements of 16bits */ 1050 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1051 ADIS16495_BURST_MAX_DATA * 2), 1052 }, 1053 [ADIS16497_1] = { 1054 .channels = adis16485_channels, 1055 .num_channels = ARRAY_SIZE(adis16485_channels), 1056 .gyro_max_val = 20000 << 16, 1057 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1058 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1059 .accel_max_scale = 40, 1060 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1061 .int_clk = 4250000, 1062 .max_dec_rate = 4250, 1063 .filter_freqs = adis16495_def_filter_freqs, 1064 .has_pps_clk_mode = true, 1065 /* 20 elements of 16bits */ 1066 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1067 ADIS16495_BURST_MAX_DATA * 2), 1068 }, 1069 [ADIS16497_2] = { 1070 .channels = adis16485_channels, 1071 .num_channels = ARRAY_SIZE(adis16485_channels), 1072 .gyro_max_val = 18000 << 16, 1073 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1074 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1075 .accel_max_scale = 40, 1076 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1077 .int_clk = 4250000, 1078 .max_dec_rate = 4250, 1079 .filter_freqs = adis16495_def_filter_freqs, 1080 .has_pps_clk_mode = true, 1081 /* 20 elements of 16bits */ 1082 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1083 ADIS16495_BURST_MAX_DATA * 2), 1084 }, 1085 [ADIS16497_3] = { 1086 .channels = adis16485_channels, 1087 .num_channels = ARRAY_SIZE(adis16485_channels), 1088 .gyro_max_val = 20000 << 16, 1089 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1090 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1091 .accel_max_scale = 40, 1092 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1093 .int_clk = 4250000, 1094 .max_dec_rate = 4250, 1095 .filter_freqs = adis16495_def_filter_freqs, 1096 .has_pps_clk_mode = true, 1097 /* 20 elements of 16bits */ 1098 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1099 ADIS16495_BURST_MAX_DATA * 2), 1100 }, 1101 }; 1102 1103 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc) 1104 { 1105 u32 crc_calc; 1106 u16 crc_buf[15]; 1107 int j; 1108 1109 for (j = 0; j < n_elem; j++) 1110 crc_buf[j] = swab16(buf[j]); 1111 1112 crc_calc = crc32(~0, crc_buf, n_elem * 2); 1113 crc_calc ^= ~0; 1114 1115 return (crc == crc_calc); 1116 } 1117 1118 static irqreturn_t adis16480_trigger_handler(int irq, void *p) 1119 { 1120 struct iio_poll_func *pf = p; 1121 struct iio_dev *indio_dev = pf->indio_dev; 1122 struct adis16480 *st = iio_priv(indio_dev); 1123 struct adis *adis = &st->adis; 1124 struct device *dev = &adis->spi->dev; 1125 int ret, bit, offset, i = 0; 1126 __be16 *buffer; 1127 u32 crc; 1128 bool valid; 1129 1130 adis_dev_lock(adis); 1131 if (adis->current_page != 0) { 1132 adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID); 1133 adis->tx[1] = 0; 1134 ret = spi_write(adis->spi, adis->tx, 2); 1135 if (ret) { 1136 dev_err(dev, "Failed to change device page: %d\n", ret); 1137 adis_dev_unlock(adis); 1138 goto irq_done; 1139 } 1140 1141 adis->current_page = 0; 1142 } 1143 1144 ret = spi_sync(adis->spi, &adis->msg); 1145 if (ret) { 1146 dev_err(dev, "Failed to read data: %d\n", ret); 1147 adis_dev_unlock(adis); 1148 goto irq_done; 1149 } 1150 1151 adis_dev_unlock(adis); 1152 1153 /* 1154 * After making the burst request, the response can have one or two 1155 * 16-bit responses containing the BURST_ID depending on the sclk. If 1156 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ, 1157 * we have only one. To manage that variation, we use the transition from the 1158 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5. If 1159 * we not find this variation in the first 4 segments, then the data should 1160 * not be valid. 1161 */ 1162 buffer = adis->buffer; 1163 for (offset = 0; offset < 4; offset++) { 1164 u16 curr = be16_to_cpu(buffer[offset]); 1165 u16 next = be16_to_cpu(buffer[offset + 1]); 1166 1167 if (curr == ADIS16495_BURST_ID && next != ADIS16495_BURST_ID) { 1168 offset++; 1169 break; 1170 } 1171 } 1172 1173 if (offset == 4) { 1174 dev_err(dev, "Invalid burst data\n"); 1175 goto irq_done; 1176 } 1177 1178 crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]); 1179 valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc); 1180 if (!valid) { 1181 dev_err(dev, "Invalid crc\n"); 1182 goto irq_done; 1183 } 1184 1185 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 1186 /* 1187 * When burst mode is used, temperature is the first data 1188 * channel in the sequence, but the temperature scan index 1189 * is 10. 1190 */ 1191 switch (bit) { 1192 case ADIS16480_SCAN_TEMP: 1193 st->data[i++] = buffer[offset + 1]; 1194 break; 1195 case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z: 1196 /* The lower register data is sequenced first */ 1197 st->data[i++] = buffer[2 * bit + offset + 3]; 1198 st->data[i++] = buffer[2 * bit + offset + 2]; 1199 break; 1200 } 1201 } 1202 1203 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1204 irq_done: 1205 iio_trigger_notify_done(indio_dev->trig); 1206 1207 return IRQ_HANDLED; 1208 } 1209 1210 static const struct iio_info adis16480_info = { 1211 .read_raw = &adis16480_read_raw, 1212 .write_raw = &adis16480_write_raw, 1213 .update_scan_mode = adis_update_scan_mode, 1214 .debugfs_reg_access = adis_debugfs_reg_access, 1215 }; 1216 1217 static int adis16480_stop_device(struct iio_dev *indio_dev) 1218 { 1219 struct adis16480 *st = iio_priv(indio_dev); 1220 struct device *dev = &st->adis.spi->dev; 1221 int ret; 1222 1223 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1224 if (ret) 1225 dev_err(dev, "Could not power down device: %d\n", ret); 1226 1227 return ret; 1228 } 1229 1230 static int adis16480_enable_irq(struct adis *adis, bool enable) 1231 { 1232 uint16_t val; 1233 int ret; 1234 1235 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1236 if (ret) 1237 return ret; 1238 1239 val &= ~ADIS16480_DRDY_EN_MSK; 1240 val |= ADIS16480_DRDY_EN(enable); 1241 1242 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1243 } 1244 1245 static int adis16480_config_irq_pin(struct adis16480 *st) 1246 { 1247 struct device *dev = &st->adis.spi->dev; 1248 struct fwnode_handle *fwnode = dev_fwnode(dev); 1249 struct irq_data *desc; 1250 enum adis16480_int_pin pin; 1251 unsigned int irq_type; 1252 uint16_t val; 1253 int i, irq = 0; 1254 1255 desc = irq_get_irq_data(st->adis.spi->irq); 1256 if (!desc) { 1257 dev_err(dev, "Could not find IRQ %d\n", irq); 1258 return -EINVAL; 1259 } 1260 1261 /* Disable data ready since the default after reset is on */ 1262 val = ADIS16480_DRDY_EN(0); 1263 1264 /* 1265 * Get the interrupt from the devicetre by reading the interrupt-names 1266 * property. If it is not specified, use DIO1 pin as default. 1267 * According to the datasheet, the factory default assigns DIO2 as data 1268 * ready signal. However, in the previous versions of the driver, DIO1 1269 * pin was used. So, we should leave it as is since some devices might 1270 * be expecting the interrupt on the wrong physical pin. 1271 */ 1272 pin = ADIS16480_PIN_DIO1; 1273 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1274 irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]); 1275 if (irq > 0) { 1276 pin = i; 1277 break; 1278 } 1279 } 1280 1281 val |= ADIS16480_DRDY_SEL(pin); 1282 1283 /* 1284 * Get the interrupt line behaviour. The data ready polarity can be 1285 * configured as positive or negative, corresponding to 1286 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively. 1287 */ 1288 irq_type = irqd_get_trigger_type(desc); 1289 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */ 1290 val |= ADIS16480_DRDY_POL(1); 1291 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1292 val |= ADIS16480_DRDY_POL(0); 1293 } else { 1294 dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type); 1295 return -EINVAL; 1296 } 1297 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1298 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1299 } 1300 1301 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st) 1302 { 1303 struct device *dev = &st->adis.spi->dev; 1304 const char *ext_clk_pin; 1305 enum adis16480_int_pin pin; 1306 int i; 1307 1308 pin = ADIS16480_PIN_DIO2; 1309 if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin)) 1310 goto clk_input_not_found; 1311 1312 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1313 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1314 return i; 1315 } 1316 1317 clk_input_not_found: 1318 dev_info(dev, "clk input line not specified, using DIO2\n"); 1319 return pin; 1320 } 1321 1322 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable) 1323 { 1324 struct device *dev = &st->adis.spi->dev; 1325 unsigned int mode, mask; 1326 enum adis16480_int_pin pin; 1327 uint16_t val; 1328 int ret; 1329 1330 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1331 if (ret) 1332 return ret; 1333 1334 pin = adis16480_fw_get_ext_clk_pin(st); 1335 /* 1336 * Each DIOx pin supports only one function at a time. When a single pin 1337 * has two assignments, the enable bit for a lower priority function 1338 * automatically resets to zero (disabling the lower priority function). 1339 */ 1340 if (pin == ADIS16480_DRDY_SEL(val)) 1341 dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1); 1342 1343 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1344 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1345 /* Only ADIS1649x devices support pps ext clock mode */ 1346 if (st->chip_info->has_pps_clk_mode) { 1347 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1348 mask |= ADIS16480_SYNC_MODE_MSK; 1349 } 1350 1351 val &= ~mask; 1352 val |= mode; 1353 1354 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1355 if (ret) 1356 return ret; 1357 1358 return clk_prepare_enable(st->ext_clk); 1359 } 1360 1361 static int adis16480_get_ext_clocks(struct adis16480 *st) 1362 { 1363 struct device *dev = &st->adis.spi->dev; 1364 1365 st->ext_clk = devm_clk_get_optional(dev, "sync"); 1366 if (IS_ERR(st->ext_clk)) 1367 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n"); 1368 if (st->ext_clk) { 1369 st->clk_mode = ADIS16480_CLK_SYNC; 1370 return 0; 1371 } 1372 1373 if (st->chip_info->has_pps_clk_mode) { 1374 st->ext_clk = devm_clk_get_optional(dev, "pps"); 1375 if (IS_ERR(st->ext_clk)) 1376 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n"); 1377 if (st->ext_clk) { 1378 st->clk_mode = ADIS16480_CLK_PPS; 1379 return 0; 1380 } 1381 } 1382 1383 st->clk_mode = ADIS16480_CLK_INT; 1384 return 0; 1385 } 1386 1387 static void adis16480_stop(void *data) 1388 { 1389 adis16480_stop_device(data); 1390 } 1391 1392 static void adis16480_clk_disable(void *data) 1393 { 1394 clk_disable_unprepare(data); 1395 } 1396 1397 static int adis16480_probe(struct spi_device *spi) 1398 { 1399 const struct spi_device_id *id = spi_get_device_id(spi); 1400 const struct adis_data *adis16480_data; 1401 irq_handler_t trigger_handler = NULL; 1402 struct device *dev = &spi->dev; 1403 struct iio_dev *indio_dev; 1404 struct adis16480 *st; 1405 int ret; 1406 1407 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1408 if (indio_dev == NULL) 1409 return -ENOMEM; 1410 1411 st = iio_priv(indio_dev); 1412 1413 st->chip_info = &adis16480_chip_info[id->driver_data]; 1414 indio_dev->name = spi_get_device_id(spi)->name; 1415 indio_dev->channels = st->chip_info->channels; 1416 indio_dev->num_channels = st->chip_info->num_channels; 1417 indio_dev->info = &adis16480_info; 1418 indio_dev->modes = INDIO_DIRECT_MODE; 1419 1420 adis16480_data = &st->chip_info->adis_data; 1421 1422 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1423 if (ret) 1424 return ret; 1425 1426 ret = __adis_initial_startup(&st->adis); 1427 if (ret) 1428 return ret; 1429 1430 if (st->chip_info->has_sleep_cnt) { 1431 ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev); 1432 if (ret) 1433 return ret; 1434 } 1435 1436 ret = adis16480_config_irq_pin(st); 1437 if (ret) 1438 return ret; 1439 1440 ret = adis16480_get_ext_clocks(st); 1441 if (ret) 1442 return ret; 1443 1444 if (st->ext_clk) { 1445 ret = adis16480_ext_clk_config(st, true); 1446 if (ret) 1447 return ret; 1448 1449 ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk); 1450 if (ret) 1451 return ret; 1452 1453 st->clk_freq = clk_get_rate(st->ext_clk); 1454 st->clk_freq *= 1000; /* micro */ 1455 if (st->clk_mode == ADIS16480_CLK_PPS) { 1456 u16 sync_scale; 1457 1458 /* 1459 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence, 1460 * default the IMU sample rate to the highest multiple of the input clock 1461 * lower than the IMU max sample rate. The internal sample rate is the 1462 * max... 1463 */ 1464 sync_scale = st->chip_info->int_clk / st->clk_freq; 1465 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 1466 if (ret) 1467 return ret; 1468 } 1469 } else { 1470 st->clk_freq = st->chip_info->int_clk; 1471 } 1472 1473 /* Only use our trigger handler if burst mode is supported */ 1474 if (adis16480_data->burst_len) 1475 trigger_handler = adis16480_trigger_handler; 1476 1477 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1478 trigger_handler); 1479 if (ret) 1480 return ret; 1481 1482 ret = devm_iio_device_register(dev, indio_dev); 1483 if (ret) 1484 return ret; 1485 1486 adis16480_debugfs_init(indio_dev); 1487 1488 return 0; 1489 } 1490 1491 static const struct spi_device_id adis16480_ids[] = { 1492 { "adis16375", ADIS16375 }, 1493 { "adis16480", ADIS16480 }, 1494 { "adis16485", ADIS16485 }, 1495 { "adis16488", ADIS16488 }, 1496 { "adis16490", ADIS16490 }, 1497 { "adis16495-1", ADIS16495_1 }, 1498 { "adis16495-2", ADIS16495_2 }, 1499 { "adis16495-3", ADIS16495_3 }, 1500 { "adis16497-1", ADIS16497_1 }, 1501 { "adis16497-2", ADIS16497_2 }, 1502 { "adis16497-3", ADIS16497_3 }, 1503 { } 1504 }; 1505 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1506 1507 static const struct of_device_id adis16480_of_match[] = { 1508 { .compatible = "adi,adis16375" }, 1509 { .compatible = "adi,adis16480" }, 1510 { .compatible = "adi,adis16485" }, 1511 { .compatible = "adi,adis16488" }, 1512 { .compatible = "adi,adis16490" }, 1513 { .compatible = "adi,adis16495-1" }, 1514 { .compatible = "adi,adis16495-2" }, 1515 { .compatible = "adi,adis16495-3" }, 1516 { .compatible = "adi,adis16497-1" }, 1517 { .compatible = "adi,adis16497-2" }, 1518 { .compatible = "adi,adis16497-3" }, 1519 { }, 1520 }; 1521 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1522 1523 static struct spi_driver adis16480_driver = { 1524 .driver = { 1525 .name = "adis16480", 1526 .of_match_table = adis16480_of_match, 1527 }, 1528 .id_table = adis16480_ids, 1529 .probe = adis16480_probe, 1530 }; 1531 module_spi_driver(adis16480_driver); 1532 1533 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1534 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1535 MODULE_LICENSE("GPL v2"); 1536 MODULE_IMPORT_NS(IIO_ADISLIB); 1537