1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/spi/spi.h> 17 #include <linux/slab.h> 18 #include <linux/sysfs.h> 19 #include <linux/module.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/imu/adis.h> 25 26 #include <linux/debugfs.h> 27 28 #define ADIS16480_PAGE_SIZE 0x80 29 30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99 /* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 105 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 106 107 /* Each filter coefficent bank spans two pages */ 108 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 109 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 110 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 111 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 112 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 113 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 114 115 /* ADIS16480_REG_FNCTIO_CTRL */ 116 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 117 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 118 #define ADIS16480_DRDY_POL_MSK BIT(2) 119 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 120 #define ADIS16480_DRDY_EN_MSK BIT(3) 121 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 122 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 123 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 124 #define ADIS16480_SYNC_EN_MSK BIT(7) 125 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 126 #define ADIS16480_SYNC_MODE_MSK BIT(8) 127 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 128 129 struct adis16480_chip_info { 130 unsigned int num_channels; 131 const struct iio_chan_spec *channels; 132 unsigned int gyro_max_val; 133 unsigned int gyro_max_scale; 134 unsigned int accel_max_val; 135 unsigned int accel_max_scale; 136 unsigned int temp_scale; 137 unsigned int int_clk; 138 unsigned int max_dec_rate; 139 const unsigned int *filter_freqs; 140 bool has_pps_clk_mode; 141 }; 142 143 enum adis16480_int_pin { 144 ADIS16480_PIN_DIO1, 145 ADIS16480_PIN_DIO2, 146 ADIS16480_PIN_DIO3, 147 ADIS16480_PIN_DIO4 148 }; 149 150 enum adis16480_clock_mode { 151 ADIS16480_CLK_SYNC, 152 ADIS16480_CLK_PPS, 153 ADIS16480_CLK_INT 154 }; 155 156 struct adis16480 { 157 const struct adis16480_chip_info *chip_info; 158 159 struct adis adis; 160 struct clk *ext_clk; 161 enum adis16480_clock_mode clk_mode; 162 unsigned int clk_freq; 163 }; 164 165 static const char * const adis16480_int_pin_names[4] = { 166 [ADIS16480_PIN_DIO1] = "DIO1", 167 [ADIS16480_PIN_DIO2] = "DIO2", 168 [ADIS16480_PIN_DIO3] = "DIO3", 169 [ADIS16480_PIN_DIO4] = "DIO4", 170 }; 171 172 #ifdef CONFIG_DEBUG_FS 173 174 static ssize_t adis16480_show_firmware_revision(struct file *file, 175 char __user *userbuf, size_t count, loff_t *ppos) 176 { 177 struct adis16480 *adis16480 = file->private_data; 178 char buf[7]; 179 size_t len; 180 u16 rev; 181 int ret; 182 183 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 184 if (ret) 185 return ret; 186 187 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 188 189 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 190 } 191 192 static const struct file_operations adis16480_firmware_revision_fops = { 193 .open = simple_open, 194 .read = adis16480_show_firmware_revision, 195 .llseek = default_llseek, 196 .owner = THIS_MODULE, 197 }; 198 199 static ssize_t adis16480_show_firmware_date(struct file *file, 200 char __user *userbuf, size_t count, loff_t *ppos) 201 { 202 struct adis16480 *adis16480 = file->private_data; 203 u16 md, year; 204 char buf[12]; 205 size_t len; 206 int ret; 207 208 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 209 if (ret) 210 return ret; 211 212 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 213 if (ret) 214 return ret; 215 216 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 217 md >> 8, md & 0xff, year); 218 219 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 220 } 221 222 static const struct file_operations adis16480_firmware_date_fops = { 223 .open = simple_open, 224 .read = adis16480_show_firmware_date, 225 .llseek = default_llseek, 226 .owner = THIS_MODULE, 227 }; 228 229 static int adis16480_show_serial_number(void *arg, u64 *val) 230 { 231 struct adis16480 *adis16480 = arg; 232 u16 serial; 233 int ret; 234 235 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 236 &serial); 237 if (ret) 238 return ret; 239 240 *val = serial; 241 242 return 0; 243 } 244 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 245 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 246 247 static int adis16480_show_product_id(void *arg, u64 *val) 248 { 249 struct adis16480 *adis16480 = arg; 250 u16 prod_id; 251 int ret; 252 253 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 254 &prod_id); 255 if (ret) 256 return ret; 257 258 *val = prod_id; 259 260 return 0; 261 } 262 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 263 adis16480_show_product_id, NULL, "%llu\n"); 264 265 static int adis16480_show_flash_count(void *arg, u64 *val) 266 { 267 struct adis16480 *adis16480 = arg; 268 u32 flash_count; 269 int ret; 270 271 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 272 &flash_count); 273 if (ret) 274 return ret; 275 276 *val = flash_count; 277 278 return 0; 279 } 280 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 281 adis16480_show_flash_count, NULL, "%lld\n"); 282 283 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 284 { 285 struct adis16480 *adis16480 = iio_priv(indio_dev); 286 287 debugfs_create_file_unsafe("firmware_revision", 0400, 288 indio_dev->debugfs_dentry, adis16480, 289 &adis16480_firmware_revision_fops); 290 debugfs_create_file_unsafe("firmware_date", 0400, 291 indio_dev->debugfs_dentry, adis16480, 292 &adis16480_firmware_date_fops); 293 debugfs_create_file_unsafe("serial_number", 0400, 294 indio_dev->debugfs_dentry, adis16480, 295 &adis16480_serial_number_fops); 296 debugfs_create_file_unsafe("product_id", 0400, 297 indio_dev->debugfs_dentry, adis16480, 298 &adis16480_product_id_fops); 299 debugfs_create_file_unsafe("flash_count", 0400, 300 indio_dev->debugfs_dentry, adis16480, 301 &adis16480_flash_count_fops); 302 303 return 0; 304 } 305 306 #else 307 308 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 309 { 310 return 0; 311 } 312 313 #endif 314 315 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 316 { 317 struct adis16480 *st = iio_priv(indio_dev); 318 unsigned int t, reg; 319 320 if (val < 0 || val2 < 0) 321 return -EINVAL; 322 323 t = val * 1000 + val2 / 1000; 324 if (t == 0) 325 return -EINVAL; 326 327 /* 328 * When using PPS mode, the rate of data collection is equal to the 329 * product of the external clock frequency and the scale factor in the 330 * SYNC_SCALE register. 331 * When using sync mode, or internal clock, the output data rate is 332 * equal with the clock frequency divided by DEC_RATE + 1. 333 */ 334 if (st->clk_mode == ADIS16480_CLK_PPS) { 335 t = t / st->clk_freq; 336 reg = ADIS16495_REG_SYNC_SCALE; 337 } else { 338 t = st->clk_freq / t; 339 reg = ADIS16480_REG_DEC_RATE; 340 } 341 342 if (t > st->chip_info->max_dec_rate) 343 t = st->chip_info->max_dec_rate; 344 345 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 346 t--; 347 348 return adis_write_reg_16(&st->adis, reg, t); 349 } 350 351 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 352 { 353 struct adis16480 *st = iio_priv(indio_dev); 354 uint16_t t; 355 int ret; 356 unsigned int freq; 357 unsigned int reg; 358 359 if (st->clk_mode == ADIS16480_CLK_PPS) 360 reg = ADIS16495_REG_SYNC_SCALE; 361 else 362 reg = ADIS16480_REG_DEC_RATE; 363 364 ret = adis_read_reg_16(&st->adis, reg, &t); 365 if (ret) 366 return ret; 367 368 /* 369 * When using PPS mode, the rate of data collection is equal to the 370 * product of the external clock frequency and the scale factor in the 371 * SYNC_SCALE register. 372 * When using sync mode, or internal clock, the output data rate is 373 * equal with the clock frequency divided by DEC_RATE + 1. 374 */ 375 if (st->clk_mode == ADIS16480_CLK_PPS) 376 freq = st->clk_freq * t; 377 else 378 freq = st->clk_freq / (t + 1); 379 380 *val = freq / 1000; 381 *val2 = (freq % 1000) * 1000; 382 383 return IIO_VAL_INT_PLUS_MICRO; 384 } 385 386 enum { 387 ADIS16480_SCAN_GYRO_X, 388 ADIS16480_SCAN_GYRO_Y, 389 ADIS16480_SCAN_GYRO_Z, 390 ADIS16480_SCAN_ACCEL_X, 391 ADIS16480_SCAN_ACCEL_Y, 392 ADIS16480_SCAN_ACCEL_Z, 393 ADIS16480_SCAN_MAGN_X, 394 ADIS16480_SCAN_MAGN_Y, 395 ADIS16480_SCAN_MAGN_Z, 396 ADIS16480_SCAN_BARO, 397 ADIS16480_SCAN_TEMP, 398 }; 399 400 static const unsigned int adis16480_calibbias_regs[] = { 401 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 402 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 403 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 404 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 405 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 406 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 407 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 408 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 409 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 410 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 411 }; 412 413 static const unsigned int adis16480_calibscale_regs[] = { 414 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 415 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 416 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 417 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 418 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 419 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 420 }; 421 422 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 423 const struct iio_chan_spec *chan, int bias) 424 { 425 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 426 struct adis16480 *st = iio_priv(indio_dev); 427 428 switch (chan->type) { 429 case IIO_MAGN: 430 case IIO_PRESSURE: 431 if (bias < -0x8000 || bias >= 0x8000) 432 return -EINVAL; 433 return adis_write_reg_16(&st->adis, reg, bias); 434 case IIO_ANGL_VEL: 435 case IIO_ACCEL: 436 return adis_write_reg_32(&st->adis, reg, bias); 437 default: 438 break; 439 } 440 441 return -EINVAL; 442 } 443 444 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 445 const struct iio_chan_spec *chan, int *bias) 446 { 447 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 448 struct adis16480 *st = iio_priv(indio_dev); 449 uint16_t val16; 450 uint32_t val32; 451 int ret; 452 453 switch (chan->type) { 454 case IIO_MAGN: 455 case IIO_PRESSURE: 456 ret = adis_read_reg_16(&st->adis, reg, &val16); 457 if (ret == 0) 458 *bias = sign_extend32(val16, 15); 459 break; 460 case IIO_ANGL_VEL: 461 case IIO_ACCEL: 462 ret = adis_read_reg_32(&st->adis, reg, &val32); 463 if (ret == 0) 464 *bias = sign_extend32(val32, 31); 465 break; 466 default: 467 ret = -EINVAL; 468 } 469 470 if (ret) 471 return ret; 472 473 return IIO_VAL_INT; 474 } 475 476 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 477 const struct iio_chan_spec *chan, int scale) 478 { 479 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 480 struct adis16480 *st = iio_priv(indio_dev); 481 482 if (scale < -0x8000 || scale >= 0x8000) 483 return -EINVAL; 484 485 return adis_write_reg_16(&st->adis, reg, scale); 486 } 487 488 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 489 const struct iio_chan_spec *chan, int *scale) 490 { 491 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 492 struct adis16480 *st = iio_priv(indio_dev); 493 uint16_t val16; 494 int ret; 495 496 ret = adis_read_reg_16(&st->adis, reg, &val16); 497 if (ret) 498 return ret; 499 500 *scale = sign_extend32(val16, 15); 501 return IIO_VAL_INT; 502 } 503 504 static const unsigned int adis16480_def_filter_freqs[] = { 505 310, 506 55, 507 275, 508 63, 509 }; 510 511 static const unsigned int adis16495_def_filter_freqs[] = { 512 300, 513 100, 514 300, 515 100, 516 }; 517 518 static const unsigned int ad16480_filter_data[][2] = { 519 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 520 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 521 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 522 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 523 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 524 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 525 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 526 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 527 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 528 }; 529 530 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 531 const struct iio_chan_spec *chan, int *freq) 532 { 533 struct adis16480 *st = iio_priv(indio_dev); 534 unsigned int enable_mask, offset, reg; 535 uint16_t val; 536 int ret; 537 538 reg = ad16480_filter_data[chan->scan_index][0]; 539 offset = ad16480_filter_data[chan->scan_index][1]; 540 enable_mask = BIT(offset + 2); 541 542 ret = adis_read_reg_16(&st->adis, reg, &val); 543 if (ret) 544 return ret; 545 546 if (!(val & enable_mask)) 547 *freq = 0; 548 else 549 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 550 551 return IIO_VAL_INT; 552 } 553 554 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 555 const struct iio_chan_spec *chan, unsigned int freq) 556 { 557 struct adis16480 *st = iio_priv(indio_dev); 558 unsigned int enable_mask, offset, reg; 559 unsigned int diff, best_diff; 560 unsigned int i, best_freq; 561 uint16_t val; 562 int ret; 563 564 reg = ad16480_filter_data[chan->scan_index][0]; 565 offset = ad16480_filter_data[chan->scan_index][1]; 566 enable_mask = BIT(offset + 2); 567 568 ret = adis_read_reg_16(&st->adis, reg, &val); 569 if (ret) 570 return ret; 571 572 if (freq == 0) { 573 val &= ~enable_mask; 574 } else { 575 best_freq = 0; 576 best_diff = st->chip_info->filter_freqs[0]; 577 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 578 if (st->chip_info->filter_freqs[i] >= freq) { 579 diff = st->chip_info->filter_freqs[i] - freq; 580 if (diff < best_diff) { 581 best_diff = diff; 582 best_freq = i; 583 } 584 } 585 } 586 587 val &= ~(0x3 << offset); 588 val |= best_freq << offset; 589 val |= enable_mask; 590 } 591 592 return adis_write_reg_16(&st->adis, reg, val); 593 } 594 595 static int adis16480_read_raw(struct iio_dev *indio_dev, 596 const struct iio_chan_spec *chan, int *val, int *val2, long info) 597 { 598 struct adis16480 *st = iio_priv(indio_dev); 599 unsigned int temp; 600 601 switch (info) { 602 case IIO_CHAN_INFO_RAW: 603 return adis_single_conversion(indio_dev, chan, 0, val); 604 case IIO_CHAN_INFO_SCALE: 605 switch (chan->type) { 606 case IIO_ANGL_VEL: 607 *val = st->chip_info->gyro_max_scale; 608 *val2 = st->chip_info->gyro_max_val; 609 return IIO_VAL_FRACTIONAL; 610 case IIO_ACCEL: 611 *val = st->chip_info->accel_max_scale; 612 *val2 = st->chip_info->accel_max_val; 613 return IIO_VAL_FRACTIONAL; 614 case IIO_MAGN: 615 *val = 0; 616 *val2 = 100; /* 0.0001 gauss */ 617 return IIO_VAL_INT_PLUS_MICRO; 618 case IIO_TEMP: 619 /* 620 * +85 degrees Celsius = temp_max_scale 621 * +25 degrees Celsius = 0 622 * LSB, 25 degrees Celsius = 60 / temp_max_scale 623 */ 624 *val = st->chip_info->temp_scale / 1000; 625 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 626 return IIO_VAL_INT_PLUS_MICRO; 627 case IIO_PRESSURE: 628 /* 629 * max scale is 1310 mbar 630 * max raw value is 32767 shifted for 32bits 631 */ 632 *val = 131; /* 1310mbar = 131 kPa */ 633 *val2 = 32767 << 16; 634 return IIO_VAL_FRACTIONAL; 635 default: 636 return -EINVAL; 637 } 638 case IIO_CHAN_INFO_OFFSET: 639 /* Only the temperature channel has a offset */ 640 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 641 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 642 return IIO_VAL_INT; 643 case IIO_CHAN_INFO_CALIBBIAS: 644 return adis16480_get_calibbias(indio_dev, chan, val); 645 case IIO_CHAN_INFO_CALIBSCALE: 646 return adis16480_get_calibscale(indio_dev, chan, val); 647 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 648 return adis16480_get_filter_freq(indio_dev, chan, val); 649 case IIO_CHAN_INFO_SAMP_FREQ: 650 return adis16480_get_freq(indio_dev, val, val2); 651 default: 652 return -EINVAL; 653 } 654 } 655 656 static int adis16480_write_raw(struct iio_dev *indio_dev, 657 const struct iio_chan_spec *chan, int val, int val2, long info) 658 { 659 switch (info) { 660 case IIO_CHAN_INFO_CALIBBIAS: 661 return adis16480_set_calibbias(indio_dev, chan, val); 662 case IIO_CHAN_INFO_CALIBSCALE: 663 return adis16480_set_calibscale(indio_dev, chan, val); 664 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 665 return adis16480_set_filter_freq(indio_dev, chan, val); 666 case IIO_CHAN_INFO_SAMP_FREQ: 667 return adis16480_set_freq(indio_dev, val, val2); 668 669 default: 670 return -EINVAL; 671 } 672 } 673 674 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 675 { \ 676 .type = (_type), \ 677 .modified = 1, \ 678 .channel2 = (_mod), \ 679 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 680 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 681 _info_sep, \ 682 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 683 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 684 .address = (_address), \ 685 .scan_index = (_si), \ 686 .scan_type = { \ 687 .sign = 's', \ 688 .realbits = (_bits), \ 689 .storagebits = (_bits), \ 690 .endianness = IIO_BE, \ 691 }, \ 692 } 693 694 #define ADIS16480_GYRO_CHANNEL(_mod) \ 695 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 696 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 697 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 698 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 699 32) 700 701 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 702 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 703 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 704 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 705 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 706 32) 707 708 #define ADIS16480_MAGN_CHANNEL(_mod) \ 709 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 710 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 711 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 712 16) 713 714 #define ADIS16480_PRESSURE_CHANNEL() \ 715 { \ 716 .type = IIO_PRESSURE, \ 717 .indexed = 1, \ 718 .channel = 0, \ 719 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 720 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 721 BIT(IIO_CHAN_INFO_SCALE), \ 722 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 723 .address = ADIS16480_REG_BAROM_OUT, \ 724 .scan_index = ADIS16480_SCAN_BARO, \ 725 .scan_type = { \ 726 .sign = 's', \ 727 .realbits = 32, \ 728 .storagebits = 32, \ 729 .endianness = IIO_BE, \ 730 }, \ 731 } 732 733 #define ADIS16480_TEMP_CHANNEL() { \ 734 .type = IIO_TEMP, \ 735 .indexed = 1, \ 736 .channel = 0, \ 737 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 738 BIT(IIO_CHAN_INFO_SCALE) | \ 739 BIT(IIO_CHAN_INFO_OFFSET), \ 740 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 741 .address = ADIS16480_REG_TEMP_OUT, \ 742 .scan_index = ADIS16480_SCAN_TEMP, \ 743 .scan_type = { \ 744 .sign = 's', \ 745 .realbits = 16, \ 746 .storagebits = 16, \ 747 .endianness = IIO_BE, \ 748 }, \ 749 } 750 751 static const struct iio_chan_spec adis16480_channels[] = { 752 ADIS16480_GYRO_CHANNEL(X), 753 ADIS16480_GYRO_CHANNEL(Y), 754 ADIS16480_GYRO_CHANNEL(Z), 755 ADIS16480_ACCEL_CHANNEL(X), 756 ADIS16480_ACCEL_CHANNEL(Y), 757 ADIS16480_ACCEL_CHANNEL(Z), 758 ADIS16480_MAGN_CHANNEL(X), 759 ADIS16480_MAGN_CHANNEL(Y), 760 ADIS16480_MAGN_CHANNEL(Z), 761 ADIS16480_PRESSURE_CHANNEL(), 762 ADIS16480_TEMP_CHANNEL(), 763 IIO_CHAN_SOFT_TIMESTAMP(11) 764 }; 765 766 static const struct iio_chan_spec adis16485_channels[] = { 767 ADIS16480_GYRO_CHANNEL(X), 768 ADIS16480_GYRO_CHANNEL(Y), 769 ADIS16480_GYRO_CHANNEL(Z), 770 ADIS16480_ACCEL_CHANNEL(X), 771 ADIS16480_ACCEL_CHANNEL(Y), 772 ADIS16480_ACCEL_CHANNEL(Z), 773 ADIS16480_TEMP_CHANNEL(), 774 IIO_CHAN_SOFT_TIMESTAMP(7) 775 }; 776 777 enum adis16480_variant { 778 ADIS16375, 779 ADIS16480, 780 ADIS16485, 781 ADIS16488, 782 ADIS16495_1, 783 ADIS16495_2, 784 ADIS16495_3, 785 ADIS16497_1, 786 ADIS16497_2, 787 ADIS16497_3, 788 }; 789 790 static const struct adis16480_chip_info adis16480_chip_info[] = { 791 [ADIS16375] = { 792 .channels = adis16485_channels, 793 .num_channels = ARRAY_SIZE(adis16485_channels), 794 /* 795 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 796 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 797 * it gives better approximation. However, in this case we 798 * cannot do it since it would not fit in a 32bit variable. 799 */ 800 .gyro_max_val = 22887 << 16, 801 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 802 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 803 .accel_max_scale = 18, 804 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 805 .int_clk = 2460000, 806 .max_dec_rate = 2048, 807 .filter_freqs = adis16480_def_filter_freqs, 808 }, 809 [ADIS16480] = { 810 .channels = adis16480_channels, 811 .num_channels = ARRAY_SIZE(adis16480_channels), 812 .gyro_max_val = 22500 << 16, 813 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 814 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 815 .accel_max_scale = 10, 816 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 817 .int_clk = 2460000, 818 .max_dec_rate = 2048, 819 .filter_freqs = adis16480_def_filter_freqs, 820 }, 821 [ADIS16485] = { 822 .channels = adis16485_channels, 823 .num_channels = ARRAY_SIZE(adis16485_channels), 824 .gyro_max_val = 22500 << 16, 825 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 826 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 827 .accel_max_scale = 5, 828 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 829 .int_clk = 2460000, 830 .max_dec_rate = 2048, 831 .filter_freqs = adis16480_def_filter_freqs, 832 }, 833 [ADIS16488] = { 834 .channels = adis16480_channels, 835 .num_channels = ARRAY_SIZE(adis16480_channels), 836 .gyro_max_val = 22500 << 16, 837 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 838 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 839 .accel_max_scale = 18, 840 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 841 .int_clk = 2460000, 842 .max_dec_rate = 2048, 843 .filter_freqs = adis16480_def_filter_freqs, 844 }, 845 [ADIS16495_1] = { 846 .channels = adis16485_channels, 847 .num_channels = ARRAY_SIZE(adis16485_channels), 848 .gyro_max_val = 20000 << 16, 849 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 850 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 851 .accel_max_scale = 8, 852 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 853 .int_clk = 4250000, 854 .max_dec_rate = 4250, 855 .filter_freqs = adis16495_def_filter_freqs, 856 .has_pps_clk_mode = true, 857 }, 858 [ADIS16495_2] = { 859 .channels = adis16485_channels, 860 .num_channels = ARRAY_SIZE(adis16485_channels), 861 .gyro_max_val = 18000 << 16, 862 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 863 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 864 .accel_max_scale = 8, 865 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 866 .int_clk = 4250000, 867 .max_dec_rate = 4250, 868 .filter_freqs = adis16495_def_filter_freqs, 869 .has_pps_clk_mode = true, 870 }, 871 [ADIS16495_3] = { 872 .channels = adis16485_channels, 873 .num_channels = ARRAY_SIZE(adis16485_channels), 874 .gyro_max_val = 20000 << 16, 875 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 876 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 877 .accel_max_scale = 8, 878 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 879 .int_clk = 4250000, 880 .max_dec_rate = 4250, 881 .filter_freqs = adis16495_def_filter_freqs, 882 .has_pps_clk_mode = true, 883 }, 884 [ADIS16497_1] = { 885 .channels = adis16485_channels, 886 .num_channels = ARRAY_SIZE(adis16485_channels), 887 .gyro_max_val = 20000 << 16, 888 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 889 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 890 .accel_max_scale = 40, 891 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 892 .int_clk = 4250000, 893 .max_dec_rate = 4250, 894 .filter_freqs = adis16495_def_filter_freqs, 895 .has_pps_clk_mode = true, 896 }, 897 [ADIS16497_2] = { 898 .channels = adis16485_channels, 899 .num_channels = ARRAY_SIZE(adis16485_channels), 900 .gyro_max_val = 18000 << 16, 901 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 902 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 903 .accel_max_scale = 40, 904 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 905 .int_clk = 4250000, 906 .max_dec_rate = 4250, 907 .filter_freqs = adis16495_def_filter_freqs, 908 .has_pps_clk_mode = true, 909 }, 910 [ADIS16497_3] = { 911 .channels = adis16485_channels, 912 .num_channels = ARRAY_SIZE(adis16485_channels), 913 .gyro_max_val = 20000 << 16, 914 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 915 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 916 .accel_max_scale = 40, 917 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 918 .int_clk = 4250000, 919 .max_dec_rate = 4250, 920 .filter_freqs = adis16495_def_filter_freqs, 921 .has_pps_clk_mode = true, 922 }, 923 }; 924 925 static const struct iio_info adis16480_info = { 926 .read_raw = &adis16480_read_raw, 927 .write_raw = &adis16480_write_raw, 928 .update_scan_mode = adis_update_scan_mode, 929 .debugfs_reg_access = adis_debugfs_reg_access, 930 }; 931 932 static int adis16480_stop_device(struct iio_dev *indio_dev) 933 { 934 struct adis16480 *st = iio_priv(indio_dev); 935 int ret; 936 937 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 938 if (ret) 939 dev_err(&indio_dev->dev, 940 "Could not power down device: %d\n", ret); 941 942 return ret; 943 } 944 945 static int adis16480_enable_irq(struct adis *adis, bool enable) 946 { 947 uint16_t val; 948 int ret; 949 950 ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 951 if (ret) 952 return ret; 953 954 val &= ~ADIS16480_DRDY_EN_MSK; 955 val |= ADIS16480_DRDY_EN(enable); 956 957 return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 958 } 959 960 static int adis16480_initial_setup(struct iio_dev *indio_dev) 961 { 962 struct adis16480 *st = iio_priv(indio_dev); 963 uint16_t prod_id; 964 unsigned int device_id; 965 int ret; 966 967 adis_reset(&st->adis); 968 msleep(70); 969 970 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1)); 971 if (ret) 972 return ret; 973 msleep(30); 974 975 ret = adis_check_status(&st->adis); 976 if (ret) 977 return ret; 978 979 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id); 980 if (ret) 981 return ret; 982 983 ret = sscanf(indio_dev->name, "adis%u\n", &device_id); 984 if (ret != 1) 985 return -EINVAL; 986 987 if (prod_id != device_id) 988 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.", 989 device_id, prod_id); 990 991 return 0; 992 } 993 994 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 995 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 996 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 997 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 998 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 999 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 1000 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 1001 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 1002 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 1003 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 1004 1005 static const char * const adis16480_status_error_msgs[] = { 1006 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 1007 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 1008 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 1009 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 1010 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 1011 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 1012 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 1013 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 1014 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 1015 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 1016 }; 1017 1018 static const struct adis_data adis16480_data = { 1019 .diag_stat_reg = ADIS16480_REG_DIAG_STS, 1020 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, 1021 .has_paging = true, 1022 1023 .read_delay = 5, 1024 .write_delay = 5, 1025 1026 .status_error_msgs = adis16480_status_error_msgs, 1027 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | 1028 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | 1029 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | 1030 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | 1031 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | 1032 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | 1033 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | 1034 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | 1035 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | 1036 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), 1037 1038 .enable_irq = adis16480_enable_irq, 1039 }; 1040 1041 static int adis16480_config_irq_pin(struct device_node *of_node, 1042 struct adis16480 *st) 1043 { 1044 struct irq_data *desc; 1045 enum adis16480_int_pin pin; 1046 unsigned int irq_type; 1047 uint16_t val; 1048 int i, irq = 0; 1049 1050 desc = irq_get_irq_data(st->adis.spi->irq); 1051 if (!desc) { 1052 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1053 return -EINVAL; 1054 } 1055 1056 /* Disable data ready since the default after reset is on */ 1057 val = ADIS16480_DRDY_EN(0); 1058 1059 /* 1060 * Get the interrupt from the devicetre by reading the interrupt-names 1061 * property. If it is not specified, use DIO1 pin as default. 1062 * According to the datasheet, the factory default assigns DIO2 as data 1063 * ready signal. However, in the previous versions of the driver, DIO1 1064 * pin was used. So, we should leave it as is since some devices might 1065 * be expecting the interrupt on the wrong physical pin. 1066 */ 1067 pin = ADIS16480_PIN_DIO1; 1068 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1069 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1070 if (irq > 0) { 1071 pin = i; 1072 break; 1073 } 1074 } 1075 1076 val |= ADIS16480_DRDY_SEL(pin); 1077 1078 /* 1079 * Get the interrupt line behaviour. The data ready polarity can be 1080 * configured as positive or negative, corresponding to 1081 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. 1082 */ 1083 irq_type = irqd_get_trigger_type(desc); 1084 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ 1085 val |= ADIS16480_DRDY_POL(1); 1086 } else if (irq_type == IRQF_TRIGGER_FALLING) { 1087 val |= ADIS16480_DRDY_POL(0); 1088 } else { 1089 dev_err(&st->adis.spi->dev, 1090 "Invalid interrupt type 0x%x specified\n", irq_type); 1091 return -EINVAL; 1092 } 1093 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1094 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1095 } 1096 1097 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1098 struct device_node *of_node) 1099 { 1100 const char *ext_clk_pin; 1101 enum adis16480_int_pin pin; 1102 int i; 1103 1104 pin = ADIS16480_PIN_DIO2; 1105 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1106 goto clk_input_not_found; 1107 1108 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1109 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1110 return i; 1111 } 1112 1113 clk_input_not_found: 1114 dev_info(&st->adis.spi->dev, 1115 "clk input line not specified, using DIO2\n"); 1116 return pin; 1117 } 1118 1119 static int adis16480_ext_clk_config(struct adis16480 *st, 1120 struct device_node *of_node, 1121 bool enable) 1122 { 1123 unsigned int mode, mask; 1124 enum adis16480_int_pin pin; 1125 uint16_t val; 1126 int ret; 1127 1128 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1129 if (ret) 1130 return ret; 1131 1132 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1133 /* 1134 * Each DIOx pin supports only one function at a time. When a single pin 1135 * has two assignments, the enable bit for a lower priority function 1136 * automatically resets to zero (disabling the lower priority function). 1137 */ 1138 if (pin == ADIS16480_DRDY_SEL(val)) 1139 dev_warn(&st->adis.spi->dev, 1140 "DIO%x pin supports only one function at a time\n", 1141 pin + 1); 1142 1143 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1144 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1145 /* Only ADIS1649x devices support pps ext clock mode */ 1146 if (st->chip_info->has_pps_clk_mode) { 1147 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1148 mask |= ADIS16480_SYNC_MODE_MSK; 1149 } 1150 1151 val &= ~mask; 1152 val |= mode; 1153 1154 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1155 if (ret) 1156 return ret; 1157 1158 return clk_prepare_enable(st->ext_clk); 1159 } 1160 1161 static int adis16480_get_ext_clocks(struct adis16480 *st) 1162 { 1163 st->clk_mode = ADIS16480_CLK_INT; 1164 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1165 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1166 st->clk_mode = ADIS16480_CLK_SYNC; 1167 return 0; 1168 } 1169 1170 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1171 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1172 return PTR_ERR(st->ext_clk); 1173 } 1174 1175 if (st->chip_info->has_pps_clk_mode) { 1176 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1177 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1178 st->clk_mode = ADIS16480_CLK_PPS; 1179 return 0; 1180 } 1181 1182 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1183 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1184 return PTR_ERR(st->ext_clk); 1185 } 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int adis16480_probe(struct spi_device *spi) 1192 { 1193 const struct spi_device_id *id = spi_get_device_id(spi); 1194 struct iio_dev *indio_dev; 1195 struct adis16480 *st; 1196 int ret; 1197 1198 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1199 if (indio_dev == NULL) 1200 return -ENOMEM; 1201 1202 spi_set_drvdata(spi, indio_dev); 1203 1204 st = iio_priv(indio_dev); 1205 1206 st->chip_info = &adis16480_chip_info[id->driver_data]; 1207 indio_dev->dev.parent = &spi->dev; 1208 indio_dev->name = spi_get_device_id(spi)->name; 1209 indio_dev->channels = st->chip_info->channels; 1210 indio_dev->num_channels = st->chip_info->num_channels; 1211 indio_dev->info = &adis16480_info; 1212 indio_dev->modes = INDIO_DIRECT_MODE; 1213 1214 ret = adis_init(&st->adis, indio_dev, spi, &adis16480_data); 1215 if (ret) 1216 return ret; 1217 1218 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1219 if (ret) 1220 return ret; 1221 1222 ret = adis16480_get_ext_clocks(st); 1223 if (ret) 1224 return ret; 1225 1226 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1227 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1228 if (ret) 1229 return ret; 1230 1231 st->clk_freq = clk_get_rate(st->ext_clk); 1232 st->clk_freq *= 1000; /* micro */ 1233 } else { 1234 st->clk_freq = st->chip_info->int_clk; 1235 } 1236 1237 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1238 if (ret) 1239 goto error_clk_disable_unprepare; 1240 1241 ret = adis16480_initial_setup(indio_dev); 1242 if (ret) 1243 goto error_cleanup_buffer; 1244 1245 ret = iio_device_register(indio_dev); 1246 if (ret) 1247 goto error_stop_device; 1248 1249 adis16480_debugfs_init(indio_dev); 1250 1251 return 0; 1252 1253 error_stop_device: 1254 adis16480_stop_device(indio_dev); 1255 error_cleanup_buffer: 1256 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1257 error_clk_disable_unprepare: 1258 clk_disable_unprepare(st->ext_clk); 1259 return ret; 1260 } 1261 1262 static int adis16480_remove(struct spi_device *spi) 1263 { 1264 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1265 struct adis16480 *st = iio_priv(indio_dev); 1266 1267 iio_device_unregister(indio_dev); 1268 adis16480_stop_device(indio_dev); 1269 1270 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1271 clk_disable_unprepare(st->ext_clk); 1272 1273 return 0; 1274 } 1275 1276 static const struct spi_device_id adis16480_ids[] = { 1277 { "adis16375", ADIS16375 }, 1278 { "adis16480", ADIS16480 }, 1279 { "adis16485", ADIS16485 }, 1280 { "adis16488", ADIS16488 }, 1281 { "adis16495-1", ADIS16495_1 }, 1282 { "adis16495-2", ADIS16495_2 }, 1283 { "adis16495-3", ADIS16495_3 }, 1284 { "adis16497-1", ADIS16497_1 }, 1285 { "adis16497-2", ADIS16497_2 }, 1286 { "adis16497-3", ADIS16497_3 }, 1287 { } 1288 }; 1289 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1290 1291 static const struct of_device_id adis16480_of_match[] = { 1292 { .compatible = "adi,adis16375" }, 1293 { .compatible = "adi,adis16480" }, 1294 { .compatible = "adi,adis16485" }, 1295 { .compatible = "adi,adis16488" }, 1296 { .compatible = "adi,adis16495-1" }, 1297 { .compatible = "adi,adis16495-2" }, 1298 { .compatible = "adi,adis16495-3" }, 1299 { .compatible = "adi,adis16497-1" }, 1300 { .compatible = "adi,adis16497-2" }, 1301 { .compatible = "adi,adis16497-3" }, 1302 { }, 1303 }; 1304 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1305 1306 static struct spi_driver adis16480_driver = { 1307 .driver = { 1308 .name = "adis16480", 1309 .of_match_table = adis16480_of_match, 1310 }, 1311 .id_table = adis16480_ids, 1312 .probe = adis16480_probe, 1313 .remove = adis16480_remove, 1314 }; 1315 module_spi_driver(adis16480_driver); 1316 1317 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1318 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1319 MODULE_LICENSE("GPL v2"); 1320