1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/spi/spi.h> 17 #include <linux/slab.h> 18 #include <linux/sysfs.h> 19 #include <linux/module.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/imu/adis.h> 25 26 #include <linux/debugfs.h> 27 28 #define ADIS16480_PAGE_SIZE 0x80 29 30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99 /* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 105 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 106 107 /* Each filter coefficent bank spans two pages */ 108 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 109 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 110 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 111 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 112 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 113 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 114 115 /* ADIS16480_REG_FNCTIO_CTRL */ 116 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 117 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 118 #define ADIS16480_DRDY_POL_MSK BIT(2) 119 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 120 #define ADIS16480_DRDY_EN_MSK BIT(3) 121 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 122 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 123 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 124 #define ADIS16480_SYNC_EN_MSK BIT(7) 125 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 126 #define ADIS16480_SYNC_MODE_MSK BIT(8) 127 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 128 129 struct adis16480_chip_info { 130 unsigned int num_channels; 131 const struct iio_chan_spec *channels; 132 unsigned int gyro_max_val; 133 unsigned int gyro_max_scale; 134 unsigned int accel_max_val; 135 unsigned int accel_max_scale; 136 unsigned int temp_scale; 137 unsigned int int_clk; 138 unsigned int max_dec_rate; 139 const unsigned int *filter_freqs; 140 bool has_pps_clk_mode; 141 const struct adis_data adis_data; 142 }; 143 144 enum adis16480_int_pin { 145 ADIS16480_PIN_DIO1, 146 ADIS16480_PIN_DIO2, 147 ADIS16480_PIN_DIO3, 148 ADIS16480_PIN_DIO4 149 }; 150 151 enum adis16480_clock_mode { 152 ADIS16480_CLK_SYNC, 153 ADIS16480_CLK_PPS, 154 ADIS16480_CLK_INT 155 }; 156 157 struct adis16480 { 158 const struct adis16480_chip_info *chip_info; 159 160 struct adis adis; 161 struct clk *ext_clk; 162 enum adis16480_clock_mode clk_mode; 163 unsigned int clk_freq; 164 }; 165 166 static const char * const adis16480_int_pin_names[4] = { 167 [ADIS16480_PIN_DIO1] = "DIO1", 168 [ADIS16480_PIN_DIO2] = "DIO2", 169 [ADIS16480_PIN_DIO3] = "DIO3", 170 [ADIS16480_PIN_DIO4] = "DIO4", 171 }; 172 173 #ifdef CONFIG_DEBUG_FS 174 175 static ssize_t adis16480_show_firmware_revision(struct file *file, 176 char __user *userbuf, size_t count, loff_t *ppos) 177 { 178 struct adis16480 *adis16480 = file->private_data; 179 char buf[7]; 180 size_t len; 181 u16 rev; 182 int ret; 183 184 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 185 if (ret) 186 return ret; 187 188 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 189 190 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 191 } 192 193 static const struct file_operations adis16480_firmware_revision_fops = { 194 .open = simple_open, 195 .read = adis16480_show_firmware_revision, 196 .llseek = default_llseek, 197 .owner = THIS_MODULE, 198 }; 199 200 static ssize_t adis16480_show_firmware_date(struct file *file, 201 char __user *userbuf, size_t count, loff_t *ppos) 202 { 203 struct adis16480 *adis16480 = file->private_data; 204 u16 md, year; 205 char buf[12]; 206 size_t len; 207 int ret; 208 209 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 210 if (ret) 211 return ret; 212 213 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 214 if (ret) 215 return ret; 216 217 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 218 md >> 8, md & 0xff, year); 219 220 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 221 } 222 223 static const struct file_operations adis16480_firmware_date_fops = { 224 .open = simple_open, 225 .read = adis16480_show_firmware_date, 226 .llseek = default_llseek, 227 .owner = THIS_MODULE, 228 }; 229 230 static int adis16480_show_serial_number(void *arg, u64 *val) 231 { 232 struct adis16480 *adis16480 = arg; 233 u16 serial; 234 int ret; 235 236 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 237 &serial); 238 if (ret) 239 return ret; 240 241 *val = serial; 242 243 return 0; 244 } 245 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 246 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 247 248 static int adis16480_show_product_id(void *arg, u64 *val) 249 { 250 struct adis16480 *adis16480 = arg; 251 u16 prod_id; 252 int ret; 253 254 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 255 &prod_id); 256 if (ret) 257 return ret; 258 259 *val = prod_id; 260 261 return 0; 262 } 263 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 264 adis16480_show_product_id, NULL, "%llu\n"); 265 266 static int adis16480_show_flash_count(void *arg, u64 *val) 267 { 268 struct adis16480 *adis16480 = arg; 269 u32 flash_count; 270 int ret; 271 272 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 273 &flash_count); 274 if (ret) 275 return ret; 276 277 *val = flash_count; 278 279 return 0; 280 } 281 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 282 adis16480_show_flash_count, NULL, "%lld\n"); 283 284 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 285 { 286 struct adis16480 *adis16480 = iio_priv(indio_dev); 287 288 debugfs_create_file_unsafe("firmware_revision", 0400, 289 indio_dev->debugfs_dentry, adis16480, 290 &adis16480_firmware_revision_fops); 291 debugfs_create_file_unsafe("firmware_date", 0400, 292 indio_dev->debugfs_dentry, adis16480, 293 &adis16480_firmware_date_fops); 294 debugfs_create_file_unsafe("serial_number", 0400, 295 indio_dev->debugfs_dentry, adis16480, 296 &adis16480_serial_number_fops); 297 debugfs_create_file_unsafe("product_id", 0400, 298 indio_dev->debugfs_dentry, adis16480, 299 &adis16480_product_id_fops); 300 debugfs_create_file_unsafe("flash_count", 0400, 301 indio_dev->debugfs_dentry, adis16480, 302 &adis16480_flash_count_fops); 303 304 return 0; 305 } 306 307 #else 308 309 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 310 { 311 return 0; 312 } 313 314 #endif 315 316 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 317 { 318 struct adis16480 *st = iio_priv(indio_dev); 319 unsigned int t, reg; 320 321 if (val < 0 || val2 < 0) 322 return -EINVAL; 323 324 t = val * 1000 + val2 / 1000; 325 if (t == 0) 326 return -EINVAL; 327 328 /* 329 * When using PPS mode, the rate of data collection is equal to the 330 * product of the external clock frequency and the scale factor in the 331 * SYNC_SCALE register. 332 * When using sync mode, or internal clock, the output data rate is 333 * equal with the clock frequency divided by DEC_RATE + 1. 334 */ 335 if (st->clk_mode == ADIS16480_CLK_PPS) { 336 t = t / st->clk_freq; 337 reg = ADIS16495_REG_SYNC_SCALE; 338 } else { 339 t = st->clk_freq / t; 340 reg = ADIS16480_REG_DEC_RATE; 341 } 342 343 if (t > st->chip_info->max_dec_rate) 344 t = st->chip_info->max_dec_rate; 345 346 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 347 t--; 348 349 return adis_write_reg_16(&st->adis, reg, t); 350 } 351 352 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 353 { 354 struct adis16480 *st = iio_priv(indio_dev); 355 uint16_t t; 356 int ret; 357 unsigned int freq; 358 unsigned int reg; 359 360 if (st->clk_mode == ADIS16480_CLK_PPS) 361 reg = ADIS16495_REG_SYNC_SCALE; 362 else 363 reg = ADIS16480_REG_DEC_RATE; 364 365 ret = adis_read_reg_16(&st->adis, reg, &t); 366 if (ret) 367 return ret; 368 369 /* 370 * When using PPS mode, the rate of data collection is equal to the 371 * product of the external clock frequency and the scale factor in the 372 * SYNC_SCALE register. 373 * When using sync mode, or internal clock, the output data rate is 374 * equal with the clock frequency divided by DEC_RATE + 1. 375 */ 376 if (st->clk_mode == ADIS16480_CLK_PPS) 377 freq = st->clk_freq * t; 378 else 379 freq = st->clk_freq / (t + 1); 380 381 *val = freq / 1000; 382 *val2 = (freq % 1000) * 1000; 383 384 return IIO_VAL_INT_PLUS_MICRO; 385 } 386 387 enum { 388 ADIS16480_SCAN_GYRO_X, 389 ADIS16480_SCAN_GYRO_Y, 390 ADIS16480_SCAN_GYRO_Z, 391 ADIS16480_SCAN_ACCEL_X, 392 ADIS16480_SCAN_ACCEL_Y, 393 ADIS16480_SCAN_ACCEL_Z, 394 ADIS16480_SCAN_MAGN_X, 395 ADIS16480_SCAN_MAGN_Y, 396 ADIS16480_SCAN_MAGN_Z, 397 ADIS16480_SCAN_BARO, 398 ADIS16480_SCAN_TEMP, 399 }; 400 401 static const unsigned int adis16480_calibbias_regs[] = { 402 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 403 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 404 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 405 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 406 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 407 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 408 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 409 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 410 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 411 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 412 }; 413 414 static const unsigned int adis16480_calibscale_regs[] = { 415 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 416 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 417 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 418 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 419 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 420 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 421 }; 422 423 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 424 const struct iio_chan_spec *chan, int bias) 425 { 426 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 427 struct adis16480 *st = iio_priv(indio_dev); 428 429 switch (chan->type) { 430 case IIO_MAGN: 431 case IIO_PRESSURE: 432 if (bias < -0x8000 || bias >= 0x8000) 433 return -EINVAL; 434 return adis_write_reg_16(&st->adis, reg, bias); 435 case IIO_ANGL_VEL: 436 case IIO_ACCEL: 437 return adis_write_reg_32(&st->adis, reg, bias); 438 default: 439 break; 440 } 441 442 return -EINVAL; 443 } 444 445 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 446 const struct iio_chan_spec *chan, int *bias) 447 { 448 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 449 struct adis16480 *st = iio_priv(indio_dev); 450 uint16_t val16; 451 uint32_t val32; 452 int ret; 453 454 switch (chan->type) { 455 case IIO_MAGN: 456 case IIO_PRESSURE: 457 ret = adis_read_reg_16(&st->adis, reg, &val16); 458 if (ret == 0) 459 *bias = sign_extend32(val16, 15); 460 break; 461 case IIO_ANGL_VEL: 462 case IIO_ACCEL: 463 ret = adis_read_reg_32(&st->adis, reg, &val32); 464 if (ret == 0) 465 *bias = sign_extend32(val32, 31); 466 break; 467 default: 468 ret = -EINVAL; 469 } 470 471 if (ret) 472 return ret; 473 474 return IIO_VAL_INT; 475 } 476 477 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 478 const struct iio_chan_spec *chan, int scale) 479 { 480 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 481 struct adis16480 *st = iio_priv(indio_dev); 482 483 if (scale < -0x8000 || scale >= 0x8000) 484 return -EINVAL; 485 486 return adis_write_reg_16(&st->adis, reg, scale); 487 } 488 489 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 490 const struct iio_chan_spec *chan, int *scale) 491 { 492 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 493 struct adis16480 *st = iio_priv(indio_dev); 494 uint16_t val16; 495 int ret; 496 497 ret = adis_read_reg_16(&st->adis, reg, &val16); 498 if (ret) 499 return ret; 500 501 *scale = sign_extend32(val16, 15); 502 return IIO_VAL_INT; 503 } 504 505 static const unsigned int adis16480_def_filter_freqs[] = { 506 310, 507 55, 508 275, 509 63, 510 }; 511 512 static const unsigned int adis16495_def_filter_freqs[] = { 513 300, 514 100, 515 300, 516 100, 517 }; 518 519 static const unsigned int ad16480_filter_data[][2] = { 520 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 521 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 522 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 523 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 524 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 525 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 526 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 527 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 528 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 529 }; 530 531 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 532 const struct iio_chan_spec *chan, int *freq) 533 { 534 struct adis16480 *st = iio_priv(indio_dev); 535 unsigned int enable_mask, offset, reg; 536 uint16_t val; 537 int ret; 538 539 reg = ad16480_filter_data[chan->scan_index][0]; 540 offset = ad16480_filter_data[chan->scan_index][1]; 541 enable_mask = BIT(offset + 2); 542 543 ret = adis_read_reg_16(&st->adis, reg, &val); 544 if (ret) 545 return ret; 546 547 if (!(val & enable_mask)) 548 *freq = 0; 549 else 550 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 551 552 return IIO_VAL_INT; 553 } 554 555 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 556 const struct iio_chan_spec *chan, unsigned int freq) 557 { 558 struct adis16480 *st = iio_priv(indio_dev); 559 struct mutex *slock = &st->adis.state_lock; 560 unsigned int enable_mask, offset, reg; 561 unsigned int diff, best_diff; 562 unsigned int i, best_freq; 563 uint16_t val; 564 int ret; 565 566 reg = ad16480_filter_data[chan->scan_index][0]; 567 offset = ad16480_filter_data[chan->scan_index][1]; 568 enable_mask = BIT(offset + 2); 569 570 mutex_lock(slock); 571 572 ret = __adis_read_reg_16(&st->adis, reg, &val); 573 if (ret) 574 goto out_unlock; 575 576 if (freq == 0) { 577 val &= ~enable_mask; 578 } else { 579 best_freq = 0; 580 best_diff = st->chip_info->filter_freqs[0]; 581 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 582 if (st->chip_info->filter_freqs[i] >= freq) { 583 diff = st->chip_info->filter_freqs[i] - freq; 584 if (diff < best_diff) { 585 best_diff = diff; 586 best_freq = i; 587 } 588 } 589 } 590 591 val &= ~(0x3 << offset); 592 val |= best_freq << offset; 593 val |= enable_mask; 594 } 595 596 ret = __adis_write_reg_16(&st->adis, reg, val); 597 out_unlock: 598 mutex_unlock(slock); 599 600 return ret; 601 } 602 603 static int adis16480_read_raw(struct iio_dev *indio_dev, 604 const struct iio_chan_spec *chan, int *val, int *val2, long info) 605 { 606 struct adis16480 *st = iio_priv(indio_dev); 607 unsigned int temp; 608 609 switch (info) { 610 case IIO_CHAN_INFO_RAW: 611 return adis_single_conversion(indio_dev, chan, 0, val); 612 case IIO_CHAN_INFO_SCALE: 613 switch (chan->type) { 614 case IIO_ANGL_VEL: 615 *val = st->chip_info->gyro_max_scale; 616 *val2 = st->chip_info->gyro_max_val; 617 return IIO_VAL_FRACTIONAL; 618 case IIO_ACCEL: 619 *val = st->chip_info->accel_max_scale; 620 *val2 = st->chip_info->accel_max_val; 621 return IIO_VAL_FRACTIONAL; 622 case IIO_MAGN: 623 *val = 0; 624 *val2 = 100; /* 0.0001 gauss */ 625 return IIO_VAL_INT_PLUS_MICRO; 626 case IIO_TEMP: 627 /* 628 * +85 degrees Celsius = temp_max_scale 629 * +25 degrees Celsius = 0 630 * LSB, 25 degrees Celsius = 60 / temp_max_scale 631 */ 632 *val = st->chip_info->temp_scale / 1000; 633 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 634 return IIO_VAL_INT_PLUS_MICRO; 635 case IIO_PRESSURE: 636 /* 637 * max scale is 1310 mbar 638 * max raw value is 32767 shifted for 32bits 639 */ 640 *val = 131; /* 1310mbar = 131 kPa */ 641 *val2 = 32767 << 16; 642 return IIO_VAL_FRACTIONAL; 643 default: 644 return -EINVAL; 645 } 646 case IIO_CHAN_INFO_OFFSET: 647 /* Only the temperature channel has a offset */ 648 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 649 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 650 return IIO_VAL_INT; 651 case IIO_CHAN_INFO_CALIBBIAS: 652 return adis16480_get_calibbias(indio_dev, chan, val); 653 case IIO_CHAN_INFO_CALIBSCALE: 654 return adis16480_get_calibscale(indio_dev, chan, val); 655 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 656 return adis16480_get_filter_freq(indio_dev, chan, val); 657 case IIO_CHAN_INFO_SAMP_FREQ: 658 return adis16480_get_freq(indio_dev, val, val2); 659 default: 660 return -EINVAL; 661 } 662 } 663 664 static int adis16480_write_raw(struct iio_dev *indio_dev, 665 const struct iio_chan_spec *chan, int val, int val2, long info) 666 { 667 switch (info) { 668 case IIO_CHAN_INFO_CALIBBIAS: 669 return adis16480_set_calibbias(indio_dev, chan, val); 670 case IIO_CHAN_INFO_CALIBSCALE: 671 return adis16480_set_calibscale(indio_dev, chan, val); 672 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 673 return adis16480_set_filter_freq(indio_dev, chan, val); 674 case IIO_CHAN_INFO_SAMP_FREQ: 675 return adis16480_set_freq(indio_dev, val, val2); 676 677 default: 678 return -EINVAL; 679 } 680 } 681 682 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 683 { \ 684 .type = (_type), \ 685 .modified = 1, \ 686 .channel2 = (_mod), \ 687 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 688 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 689 _info_sep, \ 690 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 691 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 692 .address = (_address), \ 693 .scan_index = (_si), \ 694 .scan_type = { \ 695 .sign = 's', \ 696 .realbits = (_bits), \ 697 .storagebits = (_bits), \ 698 .endianness = IIO_BE, \ 699 }, \ 700 } 701 702 #define ADIS16480_GYRO_CHANNEL(_mod) \ 703 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 704 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 705 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 706 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 707 32) 708 709 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 710 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 711 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 712 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 713 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 714 32) 715 716 #define ADIS16480_MAGN_CHANNEL(_mod) \ 717 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 718 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 719 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 720 16) 721 722 #define ADIS16480_PRESSURE_CHANNEL() \ 723 { \ 724 .type = IIO_PRESSURE, \ 725 .indexed = 1, \ 726 .channel = 0, \ 727 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 728 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 729 BIT(IIO_CHAN_INFO_SCALE), \ 730 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 731 .address = ADIS16480_REG_BAROM_OUT, \ 732 .scan_index = ADIS16480_SCAN_BARO, \ 733 .scan_type = { \ 734 .sign = 's', \ 735 .realbits = 32, \ 736 .storagebits = 32, \ 737 .endianness = IIO_BE, \ 738 }, \ 739 } 740 741 #define ADIS16480_TEMP_CHANNEL() { \ 742 .type = IIO_TEMP, \ 743 .indexed = 1, \ 744 .channel = 0, \ 745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 746 BIT(IIO_CHAN_INFO_SCALE) | \ 747 BIT(IIO_CHAN_INFO_OFFSET), \ 748 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 749 .address = ADIS16480_REG_TEMP_OUT, \ 750 .scan_index = ADIS16480_SCAN_TEMP, \ 751 .scan_type = { \ 752 .sign = 's', \ 753 .realbits = 16, \ 754 .storagebits = 16, \ 755 .endianness = IIO_BE, \ 756 }, \ 757 } 758 759 static const struct iio_chan_spec adis16480_channels[] = { 760 ADIS16480_GYRO_CHANNEL(X), 761 ADIS16480_GYRO_CHANNEL(Y), 762 ADIS16480_GYRO_CHANNEL(Z), 763 ADIS16480_ACCEL_CHANNEL(X), 764 ADIS16480_ACCEL_CHANNEL(Y), 765 ADIS16480_ACCEL_CHANNEL(Z), 766 ADIS16480_MAGN_CHANNEL(X), 767 ADIS16480_MAGN_CHANNEL(Y), 768 ADIS16480_MAGN_CHANNEL(Z), 769 ADIS16480_PRESSURE_CHANNEL(), 770 ADIS16480_TEMP_CHANNEL(), 771 IIO_CHAN_SOFT_TIMESTAMP(11) 772 }; 773 774 static const struct iio_chan_spec adis16485_channels[] = { 775 ADIS16480_GYRO_CHANNEL(X), 776 ADIS16480_GYRO_CHANNEL(Y), 777 ADIS16480_GYRO_CHANNEL(Z), 778 ADIS16480_ACCEL_CHANNEL(X), 779 ADIS16480_ACCEL_CHANNEL(Y), 780 ADIS16480_ACCEL_CHANNEL(Z), 781 ADIS16480_TEMP_CHANNEL(), 782 IIO_CHAN_SOFT_TIMESTAMP(7) 783 }; 784 785 enum adis16480_variant { 786 ADIS16375, 787 ADIS16480, 788 ADIS16485, 789 ADIS16488, 790 ADIS16490, 791 ADIS16495_1, 792 ADIS16495_2, 793 ADIS16495_3, 794 ADIS16497_1, 795 ADIS16497_2, 796 ADIS16497_3, 797 }; 798 799 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 800 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 801 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 802 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 803 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 804 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 805 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 806 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 807 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 808 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 809 810 static const char * const adis16480_status_error_msgs[] = { 811 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 812 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 813 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 814 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 815 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 816 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 817 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 818 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 819 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 820 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 821 }; 822 823 static int adis16480_enable_irq(struct adis *adis, bool enable); 824 825 #define ADIS16480_DATA(_prod_id, _timeouts) \ 826 { \ 827 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 828 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 829 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 830 .prod_id = (_prod_id), \ 831 .has_paging = true, \ 832 .read_delay = 5, \ 833 .write_delay = 5, \ 834 .self_test_mask = BIT(1), \ 835 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 836 .status_error_msgs = adis16480_status_error_msgs, \ 837 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 838 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 839 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 840 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 841 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 842 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 843 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 844 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 845 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 846 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 847 .enable_irq = adis16480_enable_irq, \ 848 .timeouts = (_timeouts), \ 849 } 850 851 static const struct adis_timeout adis16485_timeouts = { 852 .reset_ms = 560, 853 .sw_reset_ms = 120, 854 .self_test_ms = 12, 855 }; 856 857 static const struct adis_timeout adis16480_timeouts = { 858 .reset_ms = 560, 859 .sw_reset_ms = 560, 860 .self_test_ms = 12, 861 }; 862 863 static const struct adis_timeout adis16495_timeouts = { 864 .reset_ms = 170, 865 .sw_reset_ms = 130, 866 .self_test_ms = 40, 867 }; 868 869 static const struct adis_timeout adis16495_1_timeouts = { 870 .reset_ms = 250, 871 .sw_reset_ms = 210, 872 .self_test_ms = 20, 873 }; 874 875 static const struct adis16480_chip_info adis16480_chip_info[] = { 876 [ADIS16375] = { 877 .channels = adis16485_channels, 878 .num_channels = ARRAY_SIZE(adis16485_channels), 879 /* 880 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 881 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 882 * it gives better approximation. However, in this case we 883 * cannot do it since it would not fit in a 32bit variable. 884 */ 885 .gyro_max_val = 22887 << 16, 886 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 887 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 888 .accel_max_scale = 18, 889 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 890 .int_clk = 2460000, 891 .max_dec_rate = 2048, 892 .filter_freqs = adis16480_def_filter_freqs, 893 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts), 894 }, 895 [ADIS16480] = { 896 .channels = adis16480_channels, 897 .num_channels = ARRAY_SIZE(adis16480_channels), 898 .gyro_max_val = 22500 << 16, 899 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 900 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 901 .accel_max_scale = 10, 902 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 903 .int_clk = 2460000, 904 .max_dec_rate = 2048, 905 .filter_freqs = adis16480_def_filter_freqs, 906 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts), 907 }, 908 [ADIS16485] = { 909 .channels = adis16485_channels, 910 .num_channels = ARRAY_SIZE(adis16485_channels), 911 .gyro_max_val = 22500 << 16, 912 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 913 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 914 .accel_max_scale = 5, 915 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 916 .int_clk = 2460000, 917 .max_dec_rate = 2048, 918 .filter_freqs = adis16480_def_filter_freqs, 919 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts), 920 }, 921 [ADIS16488] = { 922 .channels = adis16480_channels, 923 .num_channels = ARRAY_SIZE(adis16480_channels), 924 .gyro_max_val = 22500 << 16, 925 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 926 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 927 .accel_max_scale = 18, 928 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 929 .int_clk = 2460000, 930 .max_dec_rate = 2048, 931 .filter_freqs = adis16480_def_filter_freqs, 932 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts), 933 }, 934 [ADIS16490] = { 935 .channels = adis16485_channels, 936 .num_channels = ARRAY_SIZE(adis16485_channels), 937 .gyro_max_val = 20000 << 16, 938 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 939 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 940 .accel_max_scale = 8, 941 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 942 .int_clk = 4250000, 943 .max_dec_rate = 4250, 944 .filter_freqs = adis16495_def_filter_freqs, 945 .has_pps_clk_mode = true, 946 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts), 947 }, 948 [ADIS16495_1] = { 949 .channels = adis16485_channels, 950 .num_channels = ARRAY_SIZE(adis16485_channels), 951 .gyro_max_val = 20000 << 16, 952 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 953 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 954 .accel_max_scale = 8, 955 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 956 .int_clk = 4250000, 957 .max_dec_rate = 4250, 958 .filter_freqs = adis16495_def_filter_freqs, 959 .has_pps_clk_mode = true, 960 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 961 }, 962 [ADIS16495_2] = { 963 .channels = adis16485_channels, 964 .num_channels = ARRAY_SIZE(adis16485_channels), 965 .gyro_max_val = 18000 << 16, 966 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 967 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 968 .accel_max_scale = 8, 969 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 970 .int_clk = 4250000, 971 .max_dec_rate = 4250, 972 .filter_freqs = adis16495_def_filter_freqs, 973 .has_pps_clk_mode = true, 974 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 975 }, 976 [ADIS16495_3] = { 977 .channels = adis16485_channels, 978 .num_channels = ARRAY_SIZE(adis16485_channels), 979 .gyro_max_val = 20000 << 16, 980 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 981 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 982 .accel_max_scale = 8, 983 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 984 .int_clk = 4250000, 985 .max_dec_rate = 4250, 986 .filter_freqs = adis16495_def_filter_freqs, 987 .has_pps_clk_mode = true, 988 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 989 }, 990 [ADIS16497_1] = { 991 .channels = adis16485_channels, 992 .num_channels = ARRAY_SIZE(adis16485_channels), 993 .gyro_max_val = 20000 << 16, 994 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 995 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 996 .accel_max_scale = 40, 997 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 998 .int_clk = 4250000, 999 .max_dec_rate = 4250, 1000 .filter_freqs = adis16495_def_filter_freqs, 1001 .has_pps_clk_mode = true, 1002 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1003 }, 1004 [ADIS16497_2] = { 1005 .channels = adis16485_channels, 1006 .num_channels = ARRAY_SIZE(adis16485_channels), 1007 .gyro_max_val = 18000 << 16, 1008 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1009 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1010 .accel_max_scale = 40, 1011 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1012 .int_clk = 4250000, 1013 .max_dec_rate = 4250, 1014 .filter_freqs = adis16495_def_filter_freqs, 1015 .has_pps_clk_mode = true, 1016 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1017 }, 1018 [ADIS16497_3] = { 1019 .channels = adis16485_channels, 1020 .num_channels = ARRAY_SIZE(adis16485_channels), 1021 .gyro_max_val = 20000 << 16, 1022 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1023 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1024 .accel_max_scale = 40, 1025 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1026 .int_clk = 4250000, 1027 .max_dec_rate = 4250, 1028 .filter_freqs = adis16495_def_filter_freqs, 1029 .has_pps_clk_mode = true, 1030 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1031 }, 1032 }; 1033 1034 static const struct iio_info adis16480_info = { 1035 .read_raw = &adis16480_read_raw, 1036 .write_raw = &adis16480_write_raw, 1037 .update_scan_mode = adis_update_scan_mode, 1038 .debugfs_reg_access = adis_debugfs_reg_access, 1039 }; 1040 1041 static int adis16480_stop_device(struct iio_dev *indio_dev) 1042 { 1043 struct adis16480 *st = iio_priv(indio_dev); 1044 int ret; 1045 1046 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1047 if (ret) 1048 dev_err(&indio_dev->dev, 1049 "Could not power down device: %d\n", ret); 1050 1051 return ret; 1052 } 1053 1054 static int adis16480_enable_irq(struct adis *adis, bool enable) 1055 { 1056 uint16_t val; 1057 int ret; 1058 1059 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1060 if (ret) 1061 return ret; 1062 1063 val &= ~ADIS16480_DRDY_EN_MSK; 1064 val |= ADIS16480_DRDY_EN(enable); 1065 1066 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1067 } 1068 1069 static int adis16480_config_irq_pin(struct device_node *of_node, 1070 struct adis16480 *st) 1071 { 1072 struct irq_data *desc; 1073 enum adis16480_int_pin pin; 1074 unsigned int irq_type; 1075 uint16_t val; 1076 int i, irq = 0; 1077 1078 desc = irq_get_irq_data(st->adis.spi->irq); 1079 if (!desc) { 1080 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1081 return -EINVAL; 1082 } 1083 1084 /* Disable data ready since the default after reset is on */ 1085 val = ADIS16480_DRDY_EN(0); 1086 1087 /* 1088 * Get the interrupt from the devicetre by reading the interrupt-names 1089 * property. If it is not specified, use DIO1 pin as default. 1090 * According to the datasheet, the factory default assigns DIO2 as data 1091 * ready signal. However, in the previous versions of the driver, DIO1 1092 * pin was used. So, we should leave it as is since some devices might 1093 * be expecting the interrupt on the wrong physical pin. 1094 */ 1095 pin = ADIS16480_PIN_DIO1; 1096 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1097 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1098 if (irq > 0) { 1099 pin = i; 1100 break; 1101 } 1102 } 1103 1104 val |= ADIS16480_DRDY_SEL(pin); 1105 1106 /* 1107 * Get the interrupt line behaviour. The data ready polarity can be 1108 * configured as positive or negative, corresponding to 1109 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. 1110 */ 1111 irq_type = irqd_get_trigger_type(desc); 1112 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ 1113 val |= ADIS16480_DRDY_POL(1); 1114 } else if (irq_type == IRQF_TRIGGER_FALLING) { 1115 val |= ADIS16480_DRDY_POL(0); 1116 } else { 1117 dev_err(&st->adis.spi->dev, 1118 "Invalid interrupt type 0x%x specified\n", irq_type); 1119 return -EINVAL; 1120 } 1121 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1122 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1123 } 1124 1125 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1126 struct device_node *of_node) 1127 { 1128 const char *ext_clk_pin; 1129 enum adis16480_int_pin pin; 1130 int i; 1131 1132 pin = ADIS16480_PIN_DIO2; 1133 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1134 goto clk_input_not_found; 1135 1136 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1137 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1138 return i; 1139 } 1140 1141 clk_input_not_found: 1142 dev_info(&st->adis.spi->dev, 1143 "clk input line not specified, using DIO2\n"); 1144 return pin; 1145 } 1146 1147 static int adis16480_ext_clk_config(struct adis16480 *st, 1148 struct device_node *of_node, 1149 bool enable) 1150 { 1151 unsigned int mode, mask; 1152 enum adis16480_int_pin pin; 1153 uint16_t val; 1154 int ret; 1155 1156 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1157 if (ret) 1158 return ret; 1159 1160 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1161 /* 1162 * Each DIOx pin supports only one function at a time. When a single pin 1163 * has two assignments, the enable bit for a lower priority function 1164 * automatically resets to zero (disabling the lower priority function). 1165 */ 1166 if (pin == ADIS16480_DRDY_SEL(val)) 1167 dev_warn(&st->adis.spi->dev, 1168 "DIO%x pin supports only one function at a time\n", 1169 pin + 1); 1170 1171 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1172 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1173 /* Only ADIS1649x devices support pps ext clock mode */ 1174 if (st->chip_info->has_pps_clk_mode) { 1175 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1176 mask |= ADIS16480_SYNC_MODE_MSK; 1177 } 1178 1179 val &= ~mask; 1180 val |= mode; 1181 1182 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1183 if (ret) 1184 return ret; 1185 1186 return clk_prepare_enable(st->ext_clk); 1187 } 1188 1189 static int adis16480_get_ext_clocks(struct adis16480 *st) 1190 { 1191 st->clk_mode = ADIS16480_CLK_INT; 1192 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1193 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1194 st->clk_mode = ADIS16480_CLK_SYNC; 1195 return 0; 1196 } 1197 1198 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1199 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1200 return PTR_ERR(st->ext_clk); 1201 } 1202 1203 if (st->chip_info->has_pps_clk_mode) { 1204 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1205 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1206 st->clk_mode = ADIS16480_CLK_PPS; 1207 return 0; 1208 } 1209 1210 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1211 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1212 return PTR_ERR(st->ext_clk); 1213 } 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int adis16480_probe(struct spi_device *spi) 1220 { 1221 const struct spi_device_id *id = spi_get_device_id(spi); 1222 const struct adis_data *adis16480_data; 1223 struct iio_dev *indio_dev; 1224 struct adis16480 *st; 1225 int ret; 1226 1227 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1228 if (indio_dev == NULL) 1229 return -ENOMEM; 1230 1231 spi_set_drvdata(spi, indio_dev); 1232 1233 st = iio_priv(indio_dev); 1234 1235 st->chip_info = &adis16480_chip_info[id->driver_data]; 1236 indio_dev->dev.parent = &spi->dev; 1237 indio_dev->name = spi_get_device_id(spi)->name; 1238 indio_dev->channels = st->chip_info->channels; 1239 indio_dev->num_channels = st->chip_info->num_channels; 1240 indio_dev->info = &adis16480_info; 1241 indio_dev->modes = INDIO_DIRECT_MODE; 1242 1243 adis16480_data = &st->chip_info->adis_data; 1244 1245 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1246 if (ret) 1247 return ret; 1248 1249 ret = __adis_initial_startup(&st->adis); 1250 if (ret) 1251 return ret; 1252 1253 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1254 if (ret) 1255 goto error_stop_device; 1256 1257 ret = adis16480_get_ext_clocks(st); 1258 if (ret) 1259 goto error_stop_device; 1260 1261 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1262 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1263 if (ret) 1264 goto error_stop_device; 1265 1266 st->clk_freq = clk_get_rate(st->ext_clk); 1267 st->clk_freq *= 1000; /* micro */ 1268 } else { 1269 st->clk_freq = st->chip_info->int_clk; 1270 } 1271 1272 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1273 if (ret) 1274 goto error_clk_disable_unprepare; 1275 1276 ret = iio_device_register(indio_dev); 1277 if (ret) 1278 goto error_cleanup_buffer; 1279 1280 adis16480_debugfs_init(indio_dev); 1281 1282 return 0; 1283 1284 error_cleanup_buffer: 1285 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1286 error_clk_disable_unprepare: 1287 clk_disable_unprepare(st->ext_clk); 1288 error_stop_device: 1289 adis16480_stop_device(indio_dev); 1290 return ret; 1291 } 1292 1293 static int adis16480_remove(struct spi_device *spi) 1294 { 1295 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1296 struct adis16480 *st = iio_priv(indio_dev); 1297 1298 iio_device_unregister(indio_dev); 1299 adis16480_stop_device(indio_dev); 1300 1301 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); 1302 clk_disable_unprepare(st->ext_clk); 1303 1304 return 0; 1305 } 1306 1307 static const struct spi_device_id adis16480_ids[] = { 1308 { "adis16375", ADIS16375 }, 1309 { "adis16480", ADIS16480 }, 1310 { "adis16485", ADIS16485 }, 1311 { "adis16488", ADIS16488 }, 1312 { "adis16490", ADIS16490 }, 1313 { "adis16495-1", ADIS16495_1 }, 1314 { "adis16495-2", ADIS16495_2 }, 1315 { "adis16495-3", ADIS16495_3 }, 1316 { "adis16497-1", ADIS16497_1 }, 1317 { "adis16497-2", ADIS16497_2 }, 1318 { "adis16497-3", ADIS16497_3 }, 1319 { } 1320 }; 1321 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1322 1323 static const struct of_device_id adis16480_of_match[] = { 1324 { .compatible = "adi,adis16375" }, 1325 { .compatible = "adi,adis16480" }, 1326 { .compatible = "adi,adis16485" }, 1327 { .compatible = "adi,adis16488" }, 1328 { .compatible = "adi,adis16490" }, 1329 { .compatible = "adi,adis16495-1" }, 1330 { .compatible = "adi,adis16495-2" }, 1331 { .compatible = "adi,adis16495-3" }, 1332 { .compatible = "adi,adis16497-1" }, 1333 { .compatible = "adi,adis16497-2" }, 1334 { .compatible = "adi,adis16497-3" }, 1335 { }, 1336 }; 1337 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1338 1339 static struct spi_driver adis16480_driver = { 1340 .driver = { 1341 .name = "adis16480", 1342 .of_match_table = adis16480_of_match, 1343 }, 1344 .id_table = adis16480_ids, 1345 .probe = adis16480_probe, 1346 .remove = adis16480_remove, 1347 }; 1348 module_spi_driver(adis16480_driver); 1349 1350 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1351 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1352 MODULE_LICENSE("GPL v2"); 1353