1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ADIS16475 IMU driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/kernel.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/imu/adis.h> 17 #include <linux/iio/sysfs.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/irq.h> 20 #include <linux/lcm.h> 21 #include <linux/math.h> 22 #include <linux/module.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/property.h> 25 #include <linux/spi/spi.h> 26 27 #define ADIS16475_REG_DIAG_STAT 0x02 28 #define ADIS16475_REG_X_GYRO_L 0x04 29 #define ADIS16475_REG_Y_GYRO_L 0x08 30 #define ADIS16475_REG_Z_GYRO_L 0x0C 31 #define ADIS16475_REG_X_ACCEL_L 0x10 32 #define ADIS16475_REG_Y_ACCEL_L 0x14 33 #define ADIS16475_REG_Z_ACCEL_L 0x18 34 #define ADIS16475_REG_TEMP_OUT 0x1c 35 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 36 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 37 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 38 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c 39 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 40 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 41 #define ADIS16475_REG_FILT_CTRL 0x5c 42 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) 43 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) 44 #define ADIS16475_REG_MSG_CTRL 0x60 45 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) 46 #define ADIS16475_MSG_CTRL_DR_POL(x) \ 47 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) 48 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) 49 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) 50 #define ADIS16475_REG_UP_SCALE 0x62 51 #define ADIS16475_REG_DEC_RATE 0x64 52 #define ADIS16475_REG_GLOB_CMD 0x68 53 #define ADIS16475_REG_FIRM_REV 0x6c 54 #define ADIS16475_REG_FIRM_DM 0x6e 55 #define ADIS16475_REG_FIRM_Y 0x70 56 #define ADIS16475_REG_PROD_ID 0x72 57 #define ADIS16475_REG_SERIAL_NUM 0x74 58 #define ADIS16475_REG_FLASH_CNT 0x7c 59 #define ADIS16500_BURST32_MASK BIT(9) 60 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 61 /* number of data elements in burst mode */ 62 #define ADIS16475_BURST32_MAX_DATA 32 63 #define ADIS16475_BURST_MAX_DATA 20 64 #define ADIS16475_MAX_SCAN_DATA 20 65 /* spi max speed in brust mode */ 66 #define ADIS16475_BURST_MAX_SPEED 1000000 67 #define ADIS16475_LSB_DEC_MASK BIT(0) 68 #define ADIS16475_LSB_FIR_MASK BIT(1) 69 70 enum { 71 ADIS16475_SYNC_DIRECT = 1, 72 ADIS16475_SYNC_SCALED, 73 ADIS16475_SYNC_OUTPUT, 74 ADIS16475_SYNC_PULSE = 5, 75 }; 76 77 struct adis16475_sync { 78 u16 sync_mode; 79 u16 min_rate; 80 u16 max_rate; 81 }; 82 83 struct adis16475_chip_info { 84 const struct iio_chan_spec *channels; 85 const struct adis16475_sync *sync; 86 const struct adis_data adis_data; 87 const char *name; 88 u32 num_channels; 89 u32 gyro_max_val; 90 u32 gyro_max_scale; 91 u32 accel_max_val; 92 u32 accel_max_scale; 93 u32 temp_scale; 94 u32 int_clk; 95 u16 max_dec; 96 u8 num_sync; 97 bool has_burst32; 98 }; 99 100 struct adis16475 { 101 const struct adis16475_chip_info *info; 102 struct adis adis; 103 u32 clk_freq; 104 bool burst32; 105 unsigned long lsb_flag; 106 u16 sync_mode; 107 /* Alignment needed for the timestamp */ 108 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); 109 }; 110 111 enum { 112 ADIS16475_SCAN_GYRO_X, 113 ADIS16475_SCAN_GYRO_Y, 114 ADIS16475_SCAN_GYRO_Z, 115 ADIS16475_SCAN_ACCEL_X, 116 ADIS16475_SCAN_ACCEL_Y, 117 ADIS16475_SCAN_ACCEL_Z, 118 ADIS16475_SCAN_TEMP, 119 ADIS16475_SCAN_DIAG_S_FLAGS, 120 ADIS16475_SCAN_CRC_FAILURE, 121 }; 122 123 static bool low_rate_allow; 124 module_param(low_rate_allow, bool, 0444); 125 MODULE_PARM_DESC(low_rate_allow, 126 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)"); 127 128 #ifdef CONFIG_DEBUG_FS 129 static ssize_t adis16475_show_firmware_revision(struct file *file, 130 char __user *userbuf, 131 size_t count, loff_t *ppos) 132 { 133 struct adis16475 *st = file->private_data; 134 char buf[7]; 135 size_t len; 136 u16 rev; 137 int ret; 138 139 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); 140 if (ret) 141 return ret; 142 143 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 144 145 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 146 } 147 148 static const struct file_operations adis16475_firmware_revision_fops = { 149 .open = simple_open, 150 .read = adis16475_show_firmware_revision, 151 .llseek = default_llseek, 152 .owner = THIS_MODULE, 153 }; 154 155 static ssize_t adis16475_show_firmware_date(struct file *file, 156 char __user *userbuf, 157 size_t count, loff_t *ppos) 158 { 159 struct adis16475 *st = file->private_data; 160 u16 md, year; 161 char buf[12]; 162 size_t len; 163 int ret; 164 165 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); 166 if (ret) 167 return ret; 168 169 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); 170 if (ret) 171 return ret; 172 173 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, 174 year); 175 176 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 177 } 178 179 static const struct file_operations adis16475_firmware_date_fops = { 180 .open = simple_open, 181 .read = adis16475_show_firmware_date, 182 .llseek = default_llseek, 183 .owner = THIS_MODULE, 184 }; 185 186 static int adis16475_show_serial_number(void *arg, u64 *val) 187 { 188 struct adis16475 *st = arg; 189 u16 serial; 190 int ret; 191 192 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); 193 if (ret) 194 return ret; 195 196 *val = serial; 197 198 return 0; 199 } 200 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, 201 adis16475_show_serial_number, NULL, "0x%.4llx\n"); 202 203 static int adis16475_show_product_id(void *arg, u64 *val) 204 { 205 struct adis16475 *st = arg; 206 u16 prod_id; 207 int ret; 208 209 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); 210 if (ret) 211 return ret; 212 213 *val = prod_id; 214 215 return 0; 216 } 217 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, 218 adis16475_show_product_id, NULL, "%llu\n"); 219 220 static int adis16475_show_flash_count(void *arg, u64 *val) 221 { 222 struct adis16475 *st = arg; 223 u32 flash_count; 224 int ret; 225 226 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, 227 &flash_count); 228 if (ret) 229 return ret; 230 231 *val = flash_count; 232 233 return 0; 234 } 235 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, 236 adis16475_show_flash_count, NULL, "%lld\n"); 237 238 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 239 { 240 struct adis16475 *st = iio_priv(indio_dev); 241 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 242 243 debugfs_create_file_unsafe("serial_number", 0400, 244 d, st, &adis16475_serial_number_fops); 245 debugfs_create_file_unsafe("product_id", 0400, 246 d, st, &adis16475_product_id_fops); 247 debugfs_create_file_unsafe("flash_count", 0400, 248 d, st, &adis16475_flash_count_fops); 249 debugfs_create_file("firmware_revision", 0400, 250 d, st, &adis16475_firmware_revision_fops); 251 debugfs_create_file("firmware_date", 0400, d, 252 st, &adis16475_firmware_date_fops); 253 } 254 #else 255 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 256 { 257 } 258 #endif 259 260 static int adis16475_get_freq(struct adis16475 *st, u32 *freq) 261 { 262 int ret; 263 u16 dec; 264 u32 sample_rate = st->clk_freq; 265 266 adis_dev_lock(&st->adis); 267 268 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 269 u16 sync_scale; 270 271 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale); 272 if (ret) 273 goto error; 274 275 sample_rate = st->clk_freq * sync_scale; 276 } 277 278 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); 279 if (ret) 280 goto error; 281 282 adis_dev_unlock(&st->adis); 283 284 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1); 285 286 return 0; 287 error: 288 adis_dev_unlock(&st->adis); 289 return ret; 290 } 291 292 static int adis16475_set_freq(struct adis16475 *st, const u32 freq) 293 { 294 u16 dec; 295 int ret; 296 u32 sample_rate = st->clk_freq; 297 298 if (!freq) 299 return -EINVAL; 300 301 adis_dev_lock(&st->adis); 302 /* 303 * When using sync scaled mode, the input clock needs to be scaled so that we have 304 * an IMU sample rate between (optimally) 1900 and 2100. After this, we can use the 305 * decimation filter to lower the sampling rate in order to get what the user wants. 306 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 307 * the input clock. Hence, calculating the sync_scale dynamically gives us better 308 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 309 * 1. lcm of the input clock and the desired output rate. 310 * 2. get the highest multiple of the previous result lower than the adis max rate. 311 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 312 * and DEC_RATE (to get the user output rate) 313 */ 314 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 315 unsigned long scaled_rate = lcm(st->clk_freq, freq); 316 int sync_scale; 317 318 /* 319 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 320 * solution. In this case, we get the highest multiple of the input clock 321 * lower than the IMU max sample rate. 322 */ 323 if (scaled_rate > 2100000) 324 scaled_rate = 2100000 / st->clk_freq * st->clk_freq; 325 else 326 scaled_rate = 2100000 / scaled_rate * scaled_rate; 327 328 /* 329 * This is not an hard requirement but it's not advised to run the IMU 330 * with a sample rate lower than 4000Hz due to possible undersampling 331 * issues. However, there are users that might really want to take the risk. 332 * Hence, we provide a module parameter for them. If set, we allow sample 333 * rates lower than 4KHz. By default, we won't allow this and we just roundup 334 * the rate to the next multiple of the input clock bigger than 4KHz. This 335 * is done like this as in some cases (when DEC_RATE is 0) might give 336 * us the closest value to the one desired by the user... 337 */ 338 if (scaled_rate < 1900000 && !low_rate_allow) 339 scaled_rate = roundup(1900000, st->clk_freq); 340 341 sync_scale = scaled_rate / st->clk_freq; 342 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale); 343 if (ret) 344 goto error; 345 346 sample_rate = scaled_rate; 347 } 348 349 dec = DIV_ROUND_CLOSEST(sample_rate, freq); 350 351 if (dec) 352 dec--; 353 354 if (dec > st->info->max_dec) 355 dec = st->info->max_dec; 356 357 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); 358 if (ret) 359 goto error; 360 361 /* 362 * If decimation is used, then gyro and accel data will have meaningful 363 * bits on the LSB registers. This info is used on the trigger handler. 364 */ 365 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); 366 367 return 0; 368 error: 369 adis_dev_unlock(&st->adis); 370 return ret; 371 } 372 373 /* The values are approximated. */ 374 static const u32 adis16475_3db_freqs[] = { 375 [0] = 720, /* Filter disabled, full BW (~720Hz) */ 376 [1] = 360, 377 [2] = 164, 378 [3] = 80, 379 [4] = 40, 380 [5] = 20, 381 [6] = 10, 382 }; 383 384 static int adis16475_get_filter(struct adis16475 *st, u32 *filter) 385 { 386 u16 filter_sz; 387 int ret; 388 const int mask = ADIS16475_FILT_CTRL_MASK; 389 390 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); 391 if (ret) 392 return ret; 393 394 *filter = adis16475_3db_freqs[filter_sz & mask]; 395 396 return 0; 397 } 398 399 static int adis16475_set_filter(struct adis16475 *st, const u32 filter) 400 { 401 int i = ARRAY_SIZE(adis16475_3db_freqs); 402 int ret; 403 404 while (--i) { 405 if (adis16475_3db_freqs[i] >= filter) 406 break; 407 } 408 409 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, 410 ADIS16475_FILT_CTRL(i)); 411 if (ret) 412 return ret; 413 414 /* 415 * If FIR is used, then gyro and accel data will have meaningful 416 * bits on the LSB registers. This info is used on the trigger handler. 417 */ 418 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); 419 420 return 0; 421 } 422 423 static const u32 adis16475_calib_regs[] = { 424 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, 425 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, 426 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, 427 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, 428 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, 429 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, 430 }; 431 432 static int adis16475_read_raw(struct iio_dev *indio_dev, 433 const struct iio_chan_spec *chan, 434 int *val, int *val2, long info) 435 { 436 struct adis16475 *st = iio_priv(indio_dev); 437 int ret; 438 u32 tmp; 439 440 switch (info) { 441 case IIO_CHAN_INFO_RAW: 442 return adis_single_conversion(indio_dev, chan, 0, val); 443 case IIO_CHAN_INFO_SCALE: 444 switch (chan->type) { 445 case IIO_ANGL_VEL: 446 *val = st->info->gyro_max_val; 447 *val2 = st->info->gyro_max_scale; 448 return IIO_VAL_FRACTIONAL; 449 case IIO_ACCEL: 450 *val = st->info->accel_max_val; 451 *val2 = st->info->accel_max_scale; 452 return IIO_VAL_FRACTIONAL; 453 case IIO_TEMP: 454 *val = st->info->temp_scale; 455 return IIO_VAL_INT; 456 default: 457 return -EINVAL; 458 } 459 case IIO_CHAN_INFO_CALIBBIAS: 460 ret = adis_read_reg_32(&st->adis, 461 adis16475_calib_regs[chan->scan_index], 462 val); 463 if (ret) 464 return ret; 465 466 return IIO_VAL_INT; 467 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 468 ret = adis16475_get_filter(st, val); 469 if (ret) 470 return ret; 471 472 return IIO_VAL_INT; 473 case IIO_CHAN_INFO_SAMP_FREQ: 474 ret = adis16475_get_freq(st, &tmp); 475 if (ret) 476 return ret; 477 478 *val = tmp / 1000; 479 *val2 = (tmp % 1000) * 1000; 480 return IIO_VAL_INT_PLUS_MICRO; 481 default: 482 return -EINVAL; 483 } 484 } 485 486 static int adis16475_write_raw(struct iio_dev *indio_dev, 487 const struct iio_chan_spec *chan, 488 int val, int val2, long info) 489 { 490 struct adis16475 *st = iio_priv(indio_dev); 491 u32 tmp; 492 493 switch (info) { 494 case IIO_CHAN_INFO_SAMP_FREQ: 495 tmp = val * 1000 + val2 / 1000; 496 return adis16475_set_freq(st, tmp); 497 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 498 return adis16475_set_filter(st, val); 499 case IIO_CHAN_INFO_CALIBBIAS: 500 return adis_write_reg_32(&st->adis, 501 adis16475_calib_regs[chan->scan_index], 502 val); 503 default: 504 return -EINVAL; 505 } 506 } 507 508 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ 509 { \ 510 .type = (_type), \ 511 .modified = 1, \ 512 .channel2 = (_mod), \ 513 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 514 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 515 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 516 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 517 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 518 .address = (_address), \ 519 .scan_index = (_si), \ 520 .scan_type = { \ 521 .sign = 's', \ 522 .realbits = (_r_bits), \ 523 .storagebits = (_s_bits), \ 524 .endianness = IIO_BE, \ 525 }, \ 526 } 527 528 #define ADIS16475_GYRO_CHANNEL(_mod) \ 529 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 530 ADIS16475_REG_ ## _mod ## _GYRO_L, \ 531 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) 532 533 #define ADIS16475_ACCEL_CHANNEL(_mod) \ 534 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 535 ADIS16475_REG_ ## _mod ## _ACCEL_L, \ 536 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) 537 538 #define ADIS16475_TEMP_CHANNEL() { \ 539 .type = IIO_TEMP, \ 540 .indexed = 1, \ 541 .channel = 0, \ 542 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 543 BIT(IIO_CHAN_INFO_SCALE), \ 544 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 545 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 546 .address = ADIS16475_REG_TEMP_OUT, \ 547 .scan_index = ADIS16475_SCAN_TEMP, \ 548 .scan_type = { \ 549 .sign = 's', \ 550 .realbits = 16, \ 551 .storagebits = 16, \ 552 .endianness = IIO_BE, \ 553 }, \ 554 } 555 556 static const struct iio_chan_spec adis16475_channels[] = { 557 ADIS16475_GYRO_CHANNEL(X), 558 ADIS16475_GYRO_CHANNEL(Y), 559 ADIS16475_GYRO_CHANNEL(Z), 560 ADIS16475_ACCEL_CHANNEL(X), 561 ADIS16475_ACCEL_CHANNEL(Y), 562 ADIS16475_ACCEL_CHANNEL(Z), 563 ADIS16475_TEMP_CHANNEL(), 564 IIO_CHAN_SOFT_TIMESTAMP(7) 565 }; 566 567 enum adis16475_variant { 568 ADIS16470, 569 ADIS16475_1, 570 ADIS16475_2, 571 ADIS16475_3, 572 ADIS16477_1, 573 ADIS16477_2, 574 ADIS16477_3, 575 ADIS16465_1, 576 ADIS16465_2, 577 ADIS16465_3, 578 ADIS16467_1, 579 ADIS16467_2, 580 ADIS16467_3, 581 ADIS16500, 582 ADIS16505_1, 583 ADIS16505_2, 584 ADIS16505_3, 585 ADIS16507_1, 586 ADIS16507_2, 587 ADIS16507_3, 588 }; 589 590 enum { 591 ADIS16475_DIAG_STAT_DATA_PATH = 1, 592 ADIS16475_DIAG_STAT_FLASH_MEM, 593 ADIS16475_DIAG_STAT_SPI, 594 ADIS16475_DIAG_STAT_STANDBY, 595 ADIS16475_DIAG_STAT_SENSOR, 596 ADIS16475_DIAG_STAT_MEMORY, 597 ADIS16475_DIAG_STAT_CLK, 598 }; 599 600 static const char * const adis16475_status_error_msgs[] = { 601 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", 602 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", 603 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", 604 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", 605 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", 606 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", 607 [ADIS16475_DIAG_STAT_CLK] = "Clock error", 608 }; 609 610 static int adis16475_enable_irq(struct adis *adis, bool enable) 611 { 612 /* 613 * There is no way to gate the data-ready signal internally inside the 614 * ADIS16475. We can only control it's polarity... 615 */ 616 if (enable) 617 enable_irq(adis->spi->irq); 618 else 619 disable_irq(adis->spi->irq); 620 621 return 0; 622 } 623 624 #define ADIS16475_DATA(_prod_id, _timeouts) \ 625 { \ 626 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ 627 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ 628 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ 629 .prod_id_reg = ADIS16475_REG_PROD_ID, \ 630 .prod_id = (_prod_id), \ 631 .self_test_mask = BIT(2), \ 632 .self_test_reg = ADIS16475_REG_GLOB_CMD, \ 633 .cs_change_delay = 16, \ 634 .read_delay = 5, \ 635 .write_delay = 5, \ 636 .status_error_msgs = adis16475_status_error_msgs, \ 637 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ 638 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ 639 BIT(ADIS16475_DIAG_STAT_SPI) | \ 640 BIT(ADIS16475_DIAG_STAT_STANDBY) | \ 641 BIT(ADIS16475_DIAG_STAT_SENSOR) | \ 642 BIT(ADIS16475_DIAG_STAT_MEMORY) | \ 643 BIT(ADIS16475_DIAG_STAT_CLK), \ 644 .enable_irq = adis16475_enable_irq, \ 645 .timeouts = (_timeouts), \ 646 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ 647 .burst_len = ADIS16475_BURST_MAX_DATA, \ 648 .burst_max_len = ADIS16475_BURST32_MAX_DATA \ 649 } 650 651 static const struct adis16475_sync adis16475_sync_mode[] = { 652 { ADIS16475_SYNC_OUTPUT }, 653 { ADIS16475_SYNC_DIRECT, 1900, 2100 }, 654 { ADIS16475_SYNC_SCALED, 1, 128 }, 655 { ADIS16475_SYNC_PULSE, 1000, 2100 }, 656 }; 657 658 static const struct adis_timeout adis16475_timeouts = { 659 .reset_ms = 200, 660 .sw_reset_ms = 200, 661 .self_test_ms = 20, 662 }; 663 664 static const struct adis_timeout adis1650x_timeouts = { 665 .reset_ms = 260, 666 .sw_reset_ms = 260, 667 .self_test_ms = 30, 668 }; 669 670 static const struct adis16475_chip_info adis16475_chip_info[] = { 671 [ADIS16470] = { 672 .name = "adis16470", 673 .num_channels = ARRAY_SIZE(adis16475_channels), 674 .channels = adis16475_channels, 675 .gyro_max_val = 1, 676 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 677 .accel_max_val = 1, 678 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 679 .temp_scale = 100, 680 .int_clk = 2000, 681 .max_dec = 1999, 682 .sync = adis16475_sync_mode, 683 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 684 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts), 685 }, 686 [ADIS16475_1] = { 687 .name = "adis16475-1", 688 .num_channels = ARRAY_SIZE(adis16475_channels), 689 .channels = adis16475_channels, 690 .gyro_max_val = 1, 691 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 692 .accel_max_val = 1, 693 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 694 .temp_scale = 100, 695 .int_clk = 2000, 696 .max_dec = 1999, 697 .sync = adis16475_sync_mode, 698 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 699 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 700 }, 701 [ADIS16475_2] = { 702 .name = "adis16475-2", 703 .num_channels = ARRAY_SIZE(adis16475_channels), 704 .channels = adis16475_channels, 705 .gyro_max_val = 1, 706 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 707 .accel_max_val = 1, 708 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 709 .temp_scale = 100, 710 .int_clk = 2000, 711 .max_dec = 1999, 712 .sync = adis16475_sync_mode, 713 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 714 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 715 }, 716 [ADIS16475_3] = { 717 .name = "adis16475-3", 718 .num_channels = ARRAY_SIZE(adis16475_channels), 719 .channels = adis16475_channels, 720 .gyro_max_val = 1, 721 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 722 .accel_max_val = 1, 723 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 724 .temp_scale = 100, 725 .int_clk = 2000, 726 .max_dec = 1999, 727 .sync = adis16475_sync_mode, 728 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 729 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 730 }, 731 [ADIS16477_1] = { 732 .name = "adis16477-1", 733 .num_channels = ARRAY_SIZE(adis16475_channels), 734 .channels = adis16475_channels, 735 .gyro_max_val = 1, 736 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 737 .accel_max_val = 1, 738 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 739 .temp_scale = 100, 740 .int_clk = 2000, 741 .max_dec = 1999, 742 .sync = adis16475_sync_mode, 743 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 744 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 745 }, 746 [ADIS16477_2] = { 747 .name = "adis16477-2", 748 .num_channels = ARRAY_SIZE(adis16475_channels), 749 .channels = adis16475_channels, 750 .gyro_max_val = 1, 751 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 752 .accel_max_val = 1, 753 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 754 .temp_scale = 100, 755 .int_clk = 2000, 756 .max_dec = 1999, 757 .sync = adis16475_sync_mode, 758 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 759 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 760 }, 761 [ADIS16477_3] = { 762 .name = "adis16477-3", 763 .num_channels = ARRAY_SIZE(adis16475_channels), 764 .channels = adis16475_channels, 765 .gyro_max_val = 1, 766 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 767 .accel_max_val = 1, 768 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 769 .temp_scale = 100, 770 .int_clk = 2000, 771 .max_dec = 1999, 772 .sync = adis16475_sync_mode, 773 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 774 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 775 }, 776 [ADIS16465_1] = { 777 .name = "adis16465-1", 778 .num_channels = ARRAY_SIZE(adis16475_channels), 779 .channels = adis16475_channels, 780 .gyro_max_val = 1, 781 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 782 .accel_max_val = 1, 783 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 784 .temp_scale = 100, 785 .int_clk = 2000, 786 .max_dec = 1999, 787 .sync = adis16475_sync_mode, 788 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 789 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 790 }, 791 [ADIS16465_2] = { 792 .name = "adis16465-2", 793 .num_channels = ARRAY_SIZE(adis16475_channels), 794 .channels = adis16475_channels, 795 .gyro_max_val = 1, 796 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 797 .accel_max_val = 1, 798 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 799 .temp_scale = 100, 800 .int_clk = 2000, 801 .max_dec = 1999, 802 .sync = adis16475_sync_mode, 803 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 804 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 805 }, 806 [ADIS16465_3] = { 807 .name = "adis16465-3", 808 .num_channels = ARRAY_SIZE(adis16475_channels), 809 .channels = adis16475_channels, 810 .gyro_max_val = 1, 811 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 812 .accel_max_val = 1, 813 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 814 .temp_scale = 100, 815 .int_clk = 2000, 816 .max_dec = 1999, 817 .sync = adis16475_sync_mode, 818 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 819 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 820 }, 821 [ADIS16467_1] = { 822 .name = "adis16467-1", 823 .num_channels = ARRAY_SIZE(adis16475_channels), 824 .channels = adis16475_channels, 825 .gyro_max_val = 1, 826 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 827 .accel_max_val = 1, 828 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 829 .temp_scale = 100, 830 .int_clk = 2000, 831 .max_dec = 1999, 832 .sync = adis16475_sync_mode, 833 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 834 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 835 }, 836 [ADIS16467_2] = { 837 .name = "adis16467-2", 838 .num_channels = ARRAY_SIZE(adis16475_channels), 839 .channels = adis16475_channels, 840 .gyro_max_val = 1, 841 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 842 .accel_max_val = 1, 843 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 844 .temp_scale = 100, 845 .int_clk = 2000, 846 .max_dec = 1999, 847 .sync = adis16475_sync_mode, 848 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 849 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 850 }, 851 [ADIS16467_3] = { 852 .name = "adis16467-3", 853 .num_channels = ARRAY_SIZE(adis16475_channels), 854 .channels = adis16475_channels, 855 .gyro_max_val = 1, 856 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 857 .accel_max_val = 1, 858 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 859 .temp_scale = 100, 860 .int_clk = 2000, 861 .max_dec = 1999, 862 .sync = adis16475_sync_mode, 863 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 864 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 865 }, 866 [ADIS16500] = { 867 .name = "adis16500", 868 .num_channels = ARRAY_SIZE(adis16475_channels), 869 .channels = adis16475_channels, 870 .gyro_max_val = 1, 871 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 872 .accel_max_val = 392, 873 .accel_max_scale = 32000 << 16, 874 .temp_scale = 100, 875 .int_clk = 2000, 876 .max_dec = 1999, 877 .sync = adis16475_sync_mode, 878 /* pulse sync not supported */ 879 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 880 .has_burst32 = true, 881 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), 882 }, 883 [ADIS16505_1] = { 884 .name = "adis16505-1", 885 .num_channels = ARRAY_SIZE(adis16475_channels), 886 .channels = adis16475_channels, 887 .gyro_max_val = 1, 888 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 889 .accel_max_val = 78, 890 .accel_max_scale = 32000 << 16, 891 .temp_scale = 100, 892 .int_clk = 2000, 893 .max_dec = 1999, 894 .sync = adis16475_sync_mode, 895 /* pulse sync not supported */ 896 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 897 .has_burst32 = true, 898 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 899 }, 900 [ADIS16505_2] = { 901 .name = "adis16505-2", 902 .num_channels = ARRAY_SIZE(adis16475_channels), 903 .channels = adis16475_channels, 904 .gyro_max_val = 1, 905 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 906 .accel_max_val = 78, 907 .accel_max_scale = 32000 << 16, 908 .temp_scale = 100, 909 .int_clk = 2000, 910 .max_dec = 1999, 911 .sync = adis16475_sync_mode, 912 /* pulse sync not supported */ 913 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 914 .has_burst32 = true, 915 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 916 }, 917 [ADIS16505_3] = { 918 .name = "adis16505-3", 919 .num_channels = ARRAY_SIZE(adis16475_channels), 920 .channels = adis16475_channels, 921 .gyro_max_val = 1, 922 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 923 .accel_max_val = 78, 924 .accel_max_scale = 32000 << 16, 925 .temp_scale = 100, 926 .int_clk = 2000, 927 .max_dec = 1999, 928 .sync = adis16475_sync_mode, 929 /* pulse sync not supported */ 930 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 931 .has_burst32 = true, 932 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 933 }, 934 [ADIS16507_1] = { 935 .name = "adis16507-1", 936 .num_channels = ARRAY_SIZE(adis16475_channels), 937 .channels = adis16475_channels, 938 .gyro_max_val = 1, 939 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 940 .accel_max_val = 392, 941 .accel_max_scale = 32000 << 16, 942 .temp_scale = 100, 943 .int_clk = 2000, 944 .max_dec = 1999, 945 .sync = adis16475_sync_mode, 946 /* pulse sync not supported */ 947 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 948 .has_burst32 = true, 949 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 950 }, 951 [ADIS16507_2] = { 952 .name = "adis16507-2", 953 .num_channels = ARRAY_SIZE(adis16475_channels), 954 .channels = adis16475_channels, 955 .gyro_max_val = 1, 956 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 957 .accel_max_val = 392, 958 .accel_max_scale = 32000 << 16, 959 .temp_scale = 100, 960 .int_clk = 2000, 961 .max_dec = 1999, 962 .sync = adis16475_sync_mode, 963 /* pulse sync not supported */ 964 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 965 .has_burst32 = true, 966 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 967 }, 968 [ADIS16507_3] = { 969 .name = "adis16507-3", 970 .num_channels = ARRAY_SIZE(adis16475_channels), 971 .channels = adis16475_channels, 972 .gyro_max_val = 1, 973 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 974 .accel_max_val = 392, 975 .accel_max_scale = 32000 << 16, 976 .temp_scale = 100, 977 .int_clk = 2000, 978 .max_dec = 1999, 979 .sync = adis16475_sync_mode, 980 /* pulse sync not supported */ 981 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 982 .has_burst32 = true, 983 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 984 }, 985 }; 986 987 static const struct iio_info adis16475_info = { 988 .read_raw = &adis16475_read_raw, 989 .write_raw = &adis16475_write_raw, 990 .update_scan_mode = adis_update_scan_mode, 991 .debugfs_reg_access = adis_debugfs_reg_access, 992 }; 993 994 static bool adis16475_validate_crc(const u8 *buffer, u16 crc, 995 const bool burst32) 996 { 997 int i; 998 /* extra 6 elements for low gyro and accel */ 999 const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA : 1000 ADIS16475_BURST_MAX_DATA; 1001 1002 for (i = 0; i < sz - 2; i++) 1003 crc -= buffer[i]; 1004 1005 return crc == 0; 1006 } 1007 1008 static void adis16475_burst32_check(struct adis16475 *st) 1009 { 1010 int ret; 1011 struct adis *adis = &st->adis; 1012 1013 if (!st->info->has_burst32) 1014 return; 1015 1016 if (st->lsb_flag && !st->burst32) { 1017 const u16 en = ADIS16500_BURST32(1); 1018 1019 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1020 ADIS16500_BURST32_MASK, en); 1021 if (ret) 1022 return; 1023 1024 st->burst32 = true; 1025 1026 /* 1027 * In 32-bit mode we need extra 2 bytes for all gyro 1028 * and accel channels. 1029 */ 1030 adis->burst_extra_len = 6 * sizeof(u16); 1031 adis->xfer[1].len += 6 * sizeof(u16); 1032 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", 1033 adis->xfer[1].len); 1034 1035 } else if (!st->lsb_flag && st->burst32) { 1036 const u16 en = ADIS16500_BURST32(0); 1037 1038 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1039 ADIS16500_BURST32_MASK, en); 1040 if (ret) 1041 return; 1042 1043 st->burst32 = false; 1044 1045 /* Remove the extra bits */ 1046 adis->burst_extra_len = 0; 1047 adis->xfer[1].len -= 6 * sizeof(u16); 1048 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", 1049 adis->xfer[1].len); 1050 } 1051 } 1052 1053 static irqreturn_t adis16475_trigger_handler(int irq, void *p) 1054 { 1055 struct iio_poll_func *pf = p; 1056 struct iio_dev *indio_dev = pf->indio_dev; 1057 struct adis16475 *st = iio_priv(indio_dev); 1058 struct adis *adis = &st->adis; 1059 int ret, bit, i = 0; 1060 __be16 *buffer; 1061 u16 crc; 1062 bool valid; 1063 /* offset until the first element after gyro and accel */ 1064 const u8 offset = st->burst32 ? 13 : 7; 1065 const u32 cached_spi_speed_hz = adis->spi->max_speed_hz; 1066 1067 adis->spi->max_speed_hz = ADIS16475_BURST_MAX_SPEED; 1068 1069 ret = spi_sync(adis->spi, &adis->msg); 1070 if (ret) 1071 return ret; 1072 1073 adis->spi->max_speed_hz = cached_spi_speed_hz; 1074 buffer = adis->buffer; 1075 1076 crc = be16_to_cpu(buffer[offset + 2]); 1077 valid = adis16475_validate_crc(adis->buffer, crc, st->burst32); 1078 if (!valid) { 1079 dev_err(&adis->spi->dev, "Invalid crc\n"); 1080 goto check_burst32; 1081 } 1082 1083 for_each_set_bit(bit, indio_dev->active_scan_mask, 1084 indio_dev->masklength) { 1085 /* 1086 * When burst mode is used, system flags is the first data 1087 * channel in the sequence, but the scan index is 7. 1088 */ 1089 switch (bit) { 1090 case ADIS16475_SCAN_TEMP: 1091 st->data[i++] = buffer[offset]; 1092 break; 1093 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1094 /* 1095 * The first 2 bytes on the received data are the 1096 * DIAG_STAT reg, hence the +1 offset here... 1097 */ 1098 if (st->burst32) { 1099 /* upper 16 */ 1100 st->data[i++] = buffer[bit * 2 + 2]; 1101 /* lower 16 */ 1102 st->data[i++] = buffer[bit * 2 + 1]; 1103 } else { 1104 st->data[i++] = buffer[bit + 1]; 1105 /* 1106 * Don't bother in doing the manual read if the 1107 * device supports burst32. burst32 will be 1108 * enabled in the next call to 1109 * adis16475_burst32_check()... 1110 */ 1111 if (st->lsb_flag && !st->info->has_burst32) { 1112 u16 val = 0; 1113 const u32 reg = ADIS16475_REG_X_GYRO_L + 1114 bit * 4; 1115 1116 adis_read_reg_16(adis, reg, &val); 1117 st->data[i++] = cpu_to_be16(val); 1118 } else { 1119 /* lower not used */ 1120 st->data[i++] = 0; 1121 } 1122 } 1123 break; 1124 } 1125 } 1126 1127 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1128 check_burst32: 1129 /* 1130 * We only check the burst mode at the end of the current capture since 1131 * it takes a full data ready cycle for the device to update the burst 1132 * array. 1133 */ 1134 adis16475_burst32_check(st); 1135 iio_trigger_notify_done(indio_dev->trig); 1136 1137 return IRQ_HANDLED; 1138 } 1139 1140 static void adis16475_disable_clk(void *data) 1141 { 1142 clk_disable_unprepare((struct clk *)data); 1143 } 1144 1145 static int adis16475_config_sync_mode(struct adis16475 *st) 1146 { 1147 int ret; 1148 struct device *dev = &st->adis.spi->dev; 1149 const struct adis16475_sync *sync; 1150 u32 sync_mode; 1151 1152 /* default to internal clk */ 1153 st->clk_freq = st->info->int_clk * 1000; 1154 1155 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); 1156 if (ret) 1157 return 0; 1158 1159 if (sync_mode >= st->info->num_sync) { 1160 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, 1161 st->info->name); 1162 return -EINVAL; 1163 } 1164 1165 sync = &st->info->sync[sync_mode]; 1166 st->sync_mode = sync->sync_mode; 1167 1168 /* All the other modes require external input signal */ 1169 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { 1170 struct clk *clk = devm_clk_get(dev, NULL); 1171 1172 if (IS_ERR(clk)) 1173 return PTR_ERR(clk); 1174 1175 ret = clk_prepare_enable(clk); 1176 if (ret) 1177 return ret; 1178 1179 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk); 1180 if (ret) 1181 return ret; 1182 1183 st->clk_freq = clk_get_rate(clk); 1184 if (st->clk_freq < sync->min_rate || 1185 st->clk_freq > sync->max_rate) { 1186 dev_err(dev, 1187 "Clk rate:%u not in a valid range:[%u %u]\n", 1188 st->clk_freq, sync->min_rate, sync->max_rate); 1189 return -EINVAL; 1190 } 1191 1192 if (sync->sync_mode == ADIS16475_SYNC_SCALED) { 1193 u16 up_scale; 1194 1195 /* 1196 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale. 1197 * Hence, default the IMU sample rate to the highest multiple of the input 1198 * clock lower than the IMU max sample rate. The optimal range is 1199 * 1900-2100 sps... 1200 */ 1201 up_scale = 2100 / st->clk_freq; 1202 1203 ret = __adis_write_reg_16(&st->adis, 1204 ADIS16475_REG_UP_SCALE, 1205 up_scale); 1206 if (ret) 1207 return ret; 1208 } 1209 1210 st->clk_freq *= 1000; 1211 } 1212 /* 1213 * Keep in mind that the mask for the clk modes in adis1650* 1214 * chips is different (1100 instead of 11100). However, we 1215 * are not configuring BIT(4) in these chips and the default 1216 * value is 0, so we are fine in doing the below operations. 1217 * I'm keeping this for simplicity and avoiding extra variables 1218 * in chip_info. 1219 */ 1220 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1221 ADIS16475_SYNC_MODE_MASK, sync->sync_mode); 1222 if (ret) 1223 return ret; 1224 1225 usleep_range(250, 260); 1226 1227 return 0; 1228 } 1229 1230 static int adis16475_config_irq_pin(struct adis16475 *st) 1231 { 1232 int ret; 1233 struct irq_data *desc; 1234 u32 irq_type; 1235 u16 val = 0; 1236 u8 polarity; 1237 struct spi_device *spi = st->adis.spi; 1238 1239 desc = irq_get_irq_data(spi->irq); 1240 if (!desc) { 1241 dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq); 1242 return -EINVAL; 1243 } 1244 /* 1245 * It is possible to configure the data ready polarity. Furthermore, we 1246 * need to update the adis struct if we want data ready as active low. 1247 */ 1248 irq_type = irqd_get_trigger_type(desc); 1249 if (irq_type == IRQ_TYPE_EDGE_RISING) { 1250 polarity = 1; 1251 st->adis.irq_flag = IRQF_TRIGGER_RISING; 1252 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1253 polarity = 0; 1254 st->adis.irq_flag = IRQF_TRIGGER_FALLING; 1255 } else { 1256 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1257 irq_type); 1258 return -EINVAL; 1259 } 1260 1261 /* We cannot mask the interrupt so ensure it's not enabled at request */ 1262 st->adis.irq_flag |= IRQF_NO_AUTOEN; 1263 1264 val = ADIS16475_MSG_CTRL_DR_POL(polarity); 1265 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1266 ADIS16475_MSG_CTRL_DR_POL_MASK, val); 1267 if (ret) 1268 return ret; 1269 /* 1270 * There is a delay writing to any bits written to the MSC_CTRL 1271 * register. It should not be bigger than 200us, so 250 should be more 1272 * than enough! 1273 */ 1274 usleep_range(250, 260); 1275 1276 return 0; 1277 } 1278 1279 static const struct of_device_id adis16475_of_match[] = { 1280 { .compatible = "adi,adis16470", 1281 .data = &adis16475_chip_info[ADIS16470] }, 1282 { .compatible = "adi,adis16475-1", 1283 .data = &adis16475_chip_info[ADIS16475_1] }, 1284 { .compatible = "adi,adis16475-2", 1285 .data = &adis16475_chip_info[ADIS16475_2] }, 1286 { .compatible = "adi,adis16475-3", 1287 .data = &adis16475_chip_info[ADIS16475_3] }, 1288 { .compatible = "adi,adis16477-1", 1289 .data = &adis16475_chip_info[ADIS16477_1] }, 1290 { .compatible = "adi,adis16477-2", 1291 .data = &adis16475_chip_info[ADIS16477_2] }, 1292 { .compatible = "adi,adis16477-3", 1293 .data = &adis16475_chip_info[ADIS16477_3] }, 1294 { .compatible = "adi,adis16465-1", 1295 .data = &adis16475_chip_info[ADIS16465_1] }, 1296 { .compatible = "adi,adis16465-2", 1297 .data = &adis16475_chip_info[ADIS16465_2] }, 1298 { .compatible = "adi,adis16465-3", 1299 .data = &adis16475_chip_info[ADIS16465_3] }, 1300 { .compatible = "adi,adis16467-1", 1301 .data = &adis16475_chip_info[ADIS16467_1] }, 1302 { .compatible = "adi,adis16467-2", 1303 .data = &adis16475_chip_info[ADIS16467_2] }, 1304 { .compatible = "adi,adis16467-3", 1305 .data = &adis16475_chip_info[ADIS16467_3] }, 1306 { .compatible = "adi,adis16500", 1307 .data = &adis16475_chip_info[ADIS16500] }, 1308 { .compatible = "adi,adis16505-1", 1309 .data = &adis16475_chip_info[ADIS16505_1] }, 1310 { .compatible = "adi,adis16505-2", 1311 .data = &adis16475_chip_info[ADIS16505_2] }, 1312 { .compatible = "adi,adis16505-3", 1313 .data = &adis16475_chip_info[ADIS16505_3] }, 1314 { .compatible = "adi,adis16507-1", 1315 .data = &adis16475_chip_info[ADIS16507_1] }, 1316 { .compatible = "adi,adis16507-2", 1317 .data = &adis16475_chip_info[ADIS16507_2] }, 1318 { .compatible = "adi,adis16507-3", 1319 .data = &adis16475_chip_info[ADIS16507_3] }, 1320 { }, 1321 }; 1322 MODULE_DEVICE_TABLE(of, adis16475_of_match); 1323 1324 static int adis16475_probe(struct spi_device *spi) 1325 { 1326 struct iio_dev *indio_dev; 1327 struct adis16475 *st; 1328 int ret; 1329 1330 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1331 if (!indio_dev) 1332 return -ENOMEM; 1333 1334 st = iio_priv(indio_dev); 1335 spi_set_drvdata(spi, indio_dev); 1336 1337 st->info = device_get_match_data(&spi->dev); 1338 if (!st->info) 1339 return -EINVAL; 1340 1341 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); 1342 if (ret) 1343 return ret; 1344 1345 indio_dev->name = st->info->name; 1346 indio_dev->channels = st->info->channels; 1347 indio_dev->num_channels = st->info->num_channels; 1348 indio_dev->info = &adis16475_info; 1349 indio_dev->modes = INDIO_DIRECT_MODE; 1350 1351 ret = __adis_initial_startup(&st->adis); 1352 if (ret) 1353 return ret; 1354 1355 ret = adis16475_config_irq_pin(st); 1356 if (ret) 1357 return ret; 1358 1359 ret = adis16475_config_sync_mode(st); 1360 if (ret) 1361 return ret; 1362 1363 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1364 adis16475_trigger_handler); 1365 if (ret) 1366 return ret; 1367 1368 ret = devm_iio_device_register(&spi->dev, indio_dev); 1369 if (ret) 1370 return ret; 1371 1372 adis16475_debugfs_init(indio_dev); 1373 1374 return 0; 1375 } 1376 1377 static struct spi_driver adis16475_driver = { 1378 .driver = { 1379 .name = "adis16475", 1380 .of_match_table = adis16475_of_match, 1381 }, 1382 .probe = adis16475_probe, 1383 }; 1384 module_spi_driver(adis16475_driver); 1385 1386 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1387 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); 1388 MODULE_LICENSE("GPL"); 1389