1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ADIS16475 IMU driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/kernel.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/imu/adis.h> 17 #include <linux/iio/sysfs.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/property.h> 23 #include <linux/spi/spi.h> 24 25 #define ADIS16475_REG_DIAG_STAT 0x02 26 #define ADIS16475_REG_X_GYRO_L 0x04 27 #define ADIS16475_REG_Y_GYRO_L 0x08 28 #define ADIS16475_REG_Z_GYRO_L 0x0C 29 #define ADIS16475_REG_X_ACCEL_L 0x10 30 #define ADIS16475_REG_Y_ACCEL_L 0x14 31 #define ADIS16475_REG_Z_ACCEL_L 0x18 32 #define ADIS16475_REG_TEMP_OUT 0x1c 33 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 34 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 35 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 36 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c 37 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 38 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 39 #define ADIS16475_REG_FILT_CTRL 0x5c 40 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) 41 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) 42 #define ADIS16475_REG_MSG_CTRL 0x60 43 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) 44 #define ADIS16475_MSG_CTRL_DR_POL(x) \ 45 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) 46 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) 47 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) 48 #define ADIS16475_REG_UP_SCALE 0x62 49 #define ADIS16475_REG_DEC_RATE 0x64 50 #define ADIS16475_REG_GLOB_CMD 0x68 51 #define ADIS16475_REG_FIRM_REV 0x6c 52 #define ADIS16475_REG_FIRM_DM 0x6e 53 #define ADIS16475_REG_FIRM_Y 0x70 54 #define ADIS16475_REG_PROD_ID 0x72 55 #define ADIS16475_REG_SERIAL_NUM 0x74 56 #define ADIS16475_REG_FLASH_CNT 0x7c 57 #define ADIS16500_BURST32_MASK BIT(9) 58 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 59 /* number of data elements in burst mode */ 60 #define ADIS16475_BURST32_MAX_DATA 32 61 #define ADIS16475_BURST_MAX_DATA 20 62 #define ADIS16475_MAX_SCAN_DATA 20 63 /* spi max speed in brust mode */ 64 #define ADIS16475_BURST_MAX_SPEED 1000000 65 #define ADIS16475_LSB_DEC_MASK BIT(0) 66 #define ADIS16475_LSB_FIR_MASK BIT(1) 67 68 enum { 69 ADIS16475_SYNC_DIRECT = 1, 70 ADIS16475_SYNC_SCALED, 71 ADIS16475_SYNC_OUTPUT, 72 ADIS16475_SYNC_PULSE = 5, 73 }; 74 75 struct adis16475_sync { 76 u16 sync_mode; 77 u16 min_rate; 78 u16 max_rate; 79 }; 80 81 struct adis16475_chip_info { 82 const struct iio_chan_spec *channels; 83 const struct adis16475_sync *sync; 84 const struct adis_data adis_data; 85 const char *name; 86 u32 num_channels; 87 u32 gyro_max_val; 88 u32 gyro_max_scale; 89 u32 accel_max_val; 90 u32 accel_max_scale; 91 u32 temp_scale; 92 u32 int_clk; 93 u16 max_dec; 94 u8 num_sync; 95 bool has_burst32; 96 }; 97 98 struct adis16475 { 99 const struct adis16475_chip_info *info; 100 struct adis adis; 101 u32 clk_freq; 102 bool burst32; 103 unsigned long lsb_flag; 104 /* Alignment needed for the timestamp */ 105 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); 106 }; 107 108 enum { 109 ADIS16475_SCAN_GYRO_X, 110 ADIS16475_SCAN_GYRO_Y, 111 ADIS16475_SCAN_GYRO_Z, 112 ADIS16475_SCAN_ACCEL_X, 113 ADIS16475_SCAN_ACCEL_Y, 114 ADIS16475_SCAN_ACCEL_Z, 115 ADIS16475_SCAN_TEMP, 116 ADIS16475_SCAN_DIAG_S_FLAGS, 117 ADIS16475_SCAN_CRC_FAILURE, 118 }; 119 120 #ifdef CONFIG_DEBUG_FS 121 static ssize_t adis16475_show_firmware_revision(struct file *file, 122 char __user *userbuf, 123 size_t count, loff_t *ppos) 124 { 125 struct adis16475 *st = file->private_data; 126 char buf[7]; 127 size_t len; 128 u16 rev; 129 int ret; 130 131 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); 132 if (ret) 133 return ret; 134 135 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 136 137 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 138 } 139 140 static const struct file_operations adis16475_firmware_revision_fops = { 141 .open = simple_open, 142 .read = adis16475_show_firmware_revision, 143 .llseek = default_llseek, 144 .owner = THIS_MODULE, 145 }; 146 147 static ssize_t adis16475_show_firmware_date(struct file *file, 148 char __user *userbuf, 149 size_t count, loff_t *ppos) 150 { 151 struct adis16475 *st = file->private_data; 152 u16 md, year; 153 char buf[12]; 154 size_t len; 155 int ret; 156 157 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); 158 if (ret) 159 return ret; 160 161 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); 162 if (ret) 163 return ret; 164 165 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, 166 year); 167 168 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 169 } 170 171 static const struct file_operations adis16475_firmware_date_fops = { 172 .open = simple_open, 173 .read = adis16475_show_firmware_date, 174 .llseek = default_llseek, 175 .owner = THIS_MODULE, 176 }; 177 178 static int adis16475_show_serial_number(void *arg, u64 *val) 179 { 180 struct adis16475 *st = arg; 181 u16 serial; 182 int ret; 183 184 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); 185 if (ret) 186 return ret; 187 188 *val = serial; 189 190 return 0; 191 } 192 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, 193 adis16475_show_serial_number, NULL, "0x%.4llx\n"); 194 195 static int adis16475_show_product_id(void *arg, u64 *val) 196 { 197 struct adis16475 *st = arg; 198 u16 prod_id; 199 int ret; 200 201 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); 202 if (ret) 203 return ret; 204 205 *val = prod_id; 206 207 return 0; 208 } 209 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, 210 adis16475_show_product_id, NULL, "%llu\n"); 211 212 static int adis16475_show_flash_count(void *arg, u64 *val) 213 { 214 struct adis16475 *st = arg; 215 u32 flash_count; 216 int ret; 217 218 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, 219 &flash_count); 220 if (ret) 221 return ret; 222 223 *val = flash_count; 224 225 return 0; 226 } 227 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, 228 adis16475_show_flash_count, NULL, "%lld\n"); 229 230 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 231 { 232 struct adis16475 *st = iio_priv(indio_dev); 233 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 234 235 debugfs_create_file_unsafe("serial_number", 0400, 236 d, st, &adis16475_serial_number_fops); 237 debugfs_create_file_unsafe("product_id", 0400, 238 d, st, &adis16475_product_id_fops); 239 debugfs_create_file_unsafe("flash_count", 0400, 240 d, st, &adis16475_flash_count_fops); 241 debugfs_create_file("firmware_revision", 0400, 242 d, st, &adis16475_firmware_revision_fops); 243 debugfs_create_file("firmware_date", 0400, d, 244 st, &adis16475_firmware_date_fops); 245 } 246 #else 247 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 248 { 249 } 250 #endif 251 252 static int adis16475_get_freq(struct adis16475 *st, u32 *freq) 253 { 254 int ret; 255 u16 dec; 256 257 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); 258 if (ret) 259 return -EINVAL; 260 261 *freq = DIV_ROUND_CLOSEST(st->clk_freq, dec + 1); 262 263 return 0; 264 } 265 266 static int adis16475_set_freq(struct adis16475 *st, const u32 freq) 267 { 268 u16 dec; 269 int ret; 270 271 if (!freq) 272 return -EINVAL; 273 274 dec = DIV_ROUND_CLOSEST(st->clk_freq, freq); 275 276 if (dec) 277 dec--; 278 279 if (dec > st->info->max_dec) 280 dec = st->info->max_dec; 281 282 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); 283 if (ret) 284 return ret; 285 286 /* 287 * If decimation is used, then gyro and accel data will have meaningful 288 * bits on the LSB registers. This info is used on the trigger handler. 289 */ 290 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); 291 292 return 0; 293 } 294 295 /* The values are approximated. */ 296 static const u32 adis16475_3db_freqs[] = { 297 [0] = 720, /* Filter disabled, full BW (~720Hz) */ 298 [1] = 360, 299 [2] = 164, 300 [3] = 80, 301 [4] = 40, 302 [5] = 20, 303 [6] = 10, 304 }; 305 306 static int adis16475_get_filter(struct adis16475 *st, u32 *filter) 307 { 308 u16 filter_sz; 309 int ret; 310 const int mask = ADIS16475_FILT_CTRL_MASK; 311 312 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); 313 if (ret) 314 return ret; 315 316 *filter = adis16475_3db_freqs[filter_sz & mask]; 317 318 return 0; 319 } 320 321 static int adis16475_set_filter(struct adis16475 *st, const u32 filter) 322 { 323 int i = ARRAY_SIZE(adis16475_3db_freqs); 324 int ret; 325 326 while (--i) { 327 if (adis16475_3db_freqs[i] >= filter) 328 break; 329 } 330 331 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, 332 ADIS16475_FILT_CTRL(i)); 333 if (ret) 334 return ret; 335 336 /* 337 * If FIR is used, then gyro and accel data will have meaningful 338 * bits on the LSB registers. This info is used on the trigger handler. 339 */ 340 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); 341 342 return 0; 343 } 344 345 static const u32 adis16475_calib_regs[] = { 346 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, 347 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, 348 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, 349 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, 350 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, 351 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, 352 }; 353 354 static int adis16475_read_raw(struct iio_dev *indio_dev, 355 const struct iio_chan_spec *chan, 356 int *val, int *val2, long info) 357 { 358 struct adis16475 *st = iio_priv(indio_dev); 359 int ret; 360 u32 tmp; 361 362 switch (info) { 363 case IIO_CHAN_INFO_RAW: 364 return adis_single_conversion(indio_dev, chan, 0, val); 365 case IIO_CHAN_INFO_SCALE: 366 switch (chan->type) { 367 case IIO_ANGL_VEL: 368 *val = st->info->gyro_max_val; 369 *val2 = st->info->gyro_max_scale; 370 return IIO_VAL_FRACTIONAL; 371 case IIO_ACCEL: 372 *val = st->info->accel_max_val; 373 *val2 = st->info->accel_max_scale; 374 return IIO_VAL_FRACTIONAL; 375 case IIO_TEMP: 376 *val = st->info->temp_scale; 377 return IIO_VAL_INT; 378 default: 379 return -EINVAL; 380 } 381 case IIO_CHAN_INFO_CALIBBIAS: 382 ret = adis_read_reg_32(&st->adis, 383 adis16475_calib_regs[chan->scan_index], 384 val); 385 if (ret) 386 return ret; 387 388 return IIO_VAL_INT; 389 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 390 ret = adis16475_get_filter(st, val); 391 if (ret) 392 return ret; 393 394 return IIO_VAL_INT; 395 case IIO_CHAN_INFO_SAMP_FREQ: 396 ret = adis16475_get_freq(st, &tmp); 397 if (ret) 398 return ret; 399 400 *val = tmp / 1000; 401 *val2 = (tmp % 1000) * 1000; 402 return IIO_VAL_INT_PLUS_MICRO; 403 default: 404 return -EINVAL; 405 } 406 } 407 408 static int adis16475_write_raw(struct iio_dev *indio_dev, 409 const struct iio_chan_spec *chan, 410 int val, int val2, long info) 411 { 412 struct adis16475 *st = iio_priv(indio_dev); 413 u32 tmp; 414 415 switch (info) { 416 case IIO_CHAN_INFO_SAMP_FREQ: 417 tmp = val * 1000 + val2 / 1000; 418 return adis16475_set_freq(st, tmp); 419 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 420 return adis16475_set_filter(st, val); 421 case IIO_CHAN_INFO_CALIBBIAS: 422 return adis_write_reg_32(&st->adis, 423 adis16475_calib_regs[chan->scan_index], 424 val); 425 default: 426 return -EINVAL; 427 } 428 } 429 430 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ 431 { \ 432 .type = (_type), \ 433 .modified = 1, \ 434 .channel2 = (_mod), \ 435 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 436 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 437 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 438 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 439 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 440 .address = (_address), \ 441 .scan_index = (_si), \ 442 .scan_type = { \ 443 .sign = 's', \ 444 .realbits = (_r_bits), \ 445 .storagebits = (_s_bits), \ 446 .endianness = IIO_BE, \ 447 }, \ 448 } 449 450 #define ADIS16475_GYRO_CHANNEL(_mod) \ 451 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 452 ADIS16475_REG_ ## _mod ## _GYRO_L, \ 453 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) 454 455 #define ADIS16475_ACCEL_CHANNEL(_mod) \ 456 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 457 ADIS16475_REG_ ## _mod ## _ACCEL_L, \ 458 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) 459 460 #define ADIS16475_TEMP_CHANNEL() { \ 461 .type = IIO_TEMP, \ 462 .indexed = 1, \ 463 .channel = 0, \ 464 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 465 BIT(IIO_CHAN_INFO_SCALE), \ 466 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 467 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 468 .address = ADIS16475_REG_TEMP_OUT, \ 469 .scan_index = ADIS16475_SCAN_TEMP, \ 470 .scan_type = { \ 471 .sign = 's', \ 472 .realbits = 16, \ 473 .storagebits = 16, \ 474 .endianness = IIO_BE, \ 475 }, \ 476 } 477 478 static const struct iio_chan_spec adis16475_channels[] = { 479 ADIS16475_GYRO_CHANNEL(X), 480 ADIS16475_GYRO_CHANNEL(Y), 481 ADIS16475_GYRO_CHANNEL(Z), 482 ADIS16475_ACCEL_CHANNEL(X), 483 ADIS16475_ACCEL_CHANNEL(Y), 484 ADIS16475_ACCEL_CHANNEL(Z), 485 ADIS16475_TEMP_CHANNEL(), 486 IIO_CHAN_SOFT_TIMESTAMP(7) 487 }; 488 489 enum adis16475_variant { 490 ADIS16470, 491 ADIS16475_1, 492 ADIS16475_2, 493 ADIS16475_3, 494 ADIS16477_1, 495 ADIS16477_2, 496 ADIS16477_3, 497 ADIS16465_1, 498 ADIS16465_2, 499 ADIS16465_3, 500 ADIS16467_1, 501 ADIS16467_2, 502 ADIS16467_3, 503 ADIS16500, 504 ADIS16505_1, 505 ADIS16505_2, 506 ADIS16505_3, 507 ADIS16507_1, 508 ADIS16507_2, 509 ADIS16507_3, 510 }; 511 512 enum { 513 ADIS16475_DIAG_STAT_DATA_PATH = 1, 514 ADIS16475_DIAG_STAT_FLASH_MEM, 515 ADIS16475_DIAG_STAT_SPI, 516 ADIS16475_DIAG_STAT_STANDBY, 517 ADIS16475_DIAG_STAT_SENSOR, 518 ADIS16475_DIAG_STAT_MEMORY, 519 ADIS16475_DIAG_STAT_CLK, 520 }; 521 522 static const char * const adis16475_status_error_msgs[] = { 523 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", 524 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", 525 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", 526 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", 527 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", 528 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", 529 [ADIS16475_DIAG_STAT_CLK] = "Clock error", 530 }; 531 532 static int adis16475_enable_irq(struct adis *adis, bool enable) 533 { 534 /* 535 * There is no way to gate the data-ready signal internally inside the 536 * ADIS16475. We can only control it's polarity... 537 */ 538 if (enable) 539 enable_irq(adis->spi->irq); 540 else 541 disable_irq(adis->spi->irq); 542 543 return 0; 544 } 545 546 #define ADIS16475_DATA(_prod_id, _timeouts) \ 547 { \ 548 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ 549 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ 550 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ 551 .prod_id_reg = ADIS16475_REG_PROD_ID, \ 552 .prod_id = (_prod_id), \ 553 .self_test_mask = BIT(2), \ 554 .self_test_reg = ADIS16475_REG_GLOB_CMD, \ 555 .cs_change_delay = 16, \ 556 .read_delay = 5, \ 557 .write_delay = 5, \ 558 .status_error_msgs = adis16475_status_error_msgs, \ 559 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ 560 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ 561 BIT(ADIS16475_DIAG_STAT_SPI) | \ 562 BIT(ADIS16475_DIAG_STAT_STANDBY) | \ 563 BIT(ADIS16475_DIAG_STAT_SENSOR) | \ 564 BIT(ADIS16475_DIAG_STAT_MEMORY) | \ 565 BIT(ADIS16475_DIAG_STAT_CLK), \ 566 .enable_irq = adis16475_enable_irq, \ 567 .timeouts = (_timeouts), \ 568 } 569 570 static const struct adis16475_sync adis16475_sync_mode[] = { 571 { ADIS16475_SYNC_OUTPUT }, 572 { ADIS16475_SYNC_DIRECT, 1900, 2100 }, 573 { ADIS16475_SYNC_SCALED, 1, 128 }, 574 { ADIS16475_SYNC_PULSE, 1000, 2100 }, 575 }; 576 577 static const struct adis_timeout adis16475_timeouts = { 578 .reset_ms = 200, 579 .sw_reset_ms = 200, 580 .self_test_ms = 20, 581 }; 582 583 static const struct adis_timeout adis1650x_timeouts = { 584 .reset_ms = 260, 585 .sw_reset_ms = 260, 586 .self_test_ms = 30, 587 }; 588 589 static const struct adis16475_chip_info adis16475_chip_info[] = { 590 [ADIS16470] = { 591 .name = "adis16470", 592 .num_channels = ARRAY_SIZE(adis16475_channels), 593 .channels = adis16475_channels, 594 .gyro_max_val = 1, 595 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 596 .accel_max_val = 1, 597 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 598 .temp_scale = 100, 599 .int_clk = 2000, 600 .max_dec = 1999, 601 .sync = adis16475_sync_mode, 602 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 603 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts), 604 }, 605 [ADIS16475_1] = { 606 .name = "adis16475-1", 607 .num_channels = ARRAY_SIZE(adis16475_channels), 608 .channels = adis16475_channels, 609 .gyro_max_val = 1, 610 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 611 .accel_max_val = 1, 612 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 613 .temp_scale = 100, 614 .int_clk = 2000, 615 .max_dec = 1999, 616 .sync = adis16475_sync_mode, 617 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 618 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 619 }, 620 [ADIS16475_2] = { 621 .name = "adis16475-2", 622 .num_channels = ARRAY_SIZE(adis16475_channels), 623 .channels = adis16475_channels, 624 .gyro_max_val = 1, 625 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 626 .accel_max_val = 1, 627 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 628 .temp_scale = 100, 629 .int_clk = 2000, 630 .max_dec = 1999, 631 .sync = adis16475_sync_mode, 632 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 633 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 634 }, 635 [ADIS16475_3] = { 636 .name = "adis16475-3", 637 .num_channels = ARRAY_SIZE(adis16475_channels), 638 .channels = adis16475_channels, 639 .gyro_max_val = 1, 640 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 641 .accel_max_val = 1, 642 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 643 .temp_scale = 100, 644 .int_clk = 2000, 645 .max_dec = 1999, 646 .sync = adis16475_sync_mode, 647 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 648 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 649 }, 650 [ADIS16477_1] = { 651 .name = "adis16477-1", 652 .num_channels = ARRAY_SIZE(adis16475_channels), 653 .channels = adis16475_channels, 654 .gyro_max_val = 1, 655 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 656 .accel_max_val = 1, 657 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 658 .temp_scale = 100, 659 .int_clk = 2000, 660 .max_dec = 1999, 661 .sync = adis16475_sync_mode, 662 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 663 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 664 }, 665 [ADIS16477_2] = { 666 .name = "adis16477-2", 667 .num_channels = ARRAY_SIZE(adis16475_channels), 668 .channels = adis16475_channels, 669 .gyro_max_val = 1, 670 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 671 .accel_max_val = 1, 672 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 673 .temp_scale = 100, 674 .int_clk = 2000, 675 .max_dec = 1999, 676 .sync = adis16475_sync_mode, 677 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 678 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 679 }, 680 [ADIS16477_3] = { 681 .name = "adis16477-3", 682 .num_channels = ARRAY_SIZE(adis16475_channels), 683 .channels = adis16475_channels, 684 .gyro_max_val = 1, 685 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 686 .accel_max_val = 1, 687 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 688 .temp_scale = 100, 689 .int_clk = 2000, 690 .max_dec = 1999, 691 .sync = adis16475_sync_mode, 692 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 693 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 694 }, 695 [ADIS16465_1] = { 696 .name = "adis16465-1", 697 .num_channels = ARRAY_SIZE(adis16475_channels), 698 .channels = adis16475_channels, 699 .gyro_max_val = 1, 700 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 701 .accel_max_val = 1, 702 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 703 .temp_scale = 100, 704 .int_clk = 2000, 705 .max_dec = 1999, 706 .sync = adis16475_sync_mode, 707 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 708 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 709 }, 710 [ADIS16465_2] = { 711 .name = "adis16465-2", 712 .num_channels = ARRAY_SIZE(adis16475_channels), 713 .channels = adis16475_channels, 714 .gyro_max_val = 1, 715 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 716 .accel_max_val = 1, 717 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 718 .temp_scale = 100, 719 .int_clk = 2000, 720 .max_dec = 1999, 721 .sync = adis16475_sync_mode, 722 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 723 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 724 }, 725 [ADIS16465_3] = { 726 .name = "adis16465-3", 727 .num_channels = ARRAY_SIZE(adis16475_channels), 728 .channels = adis16475_channels, 729 .gyro_max_val = 1, 730 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 731 .accel_max_val = 1, 732 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 733 .temp_scale = 100, 734 .int_clk = 2000, 735 .max_dec = 1999, 736 .sync = adis16475_sync_mode, 737 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 738 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 739 }, 740 [ADIS16467_1] = { 741 .name = "adis16467-1", 742 .num_channels = ARRAY_SIZE(adis16475_channels), 743 .channels = adis16475_channels, 744 .gyro_max_val = 1, 745 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 746 .accel_max_val = 1, 747 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 748 .temp_scale = 100, 749 .int_clk = 2000, 750 .max_dec = 1999, 751 .sync = adis16475_sync_mode, 752 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 753 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 754 }, 755 [ADIS16467_2] = { 756 .name = "adis16467-2", 757 .num_channels = ARRAY_SIZE(adis16475_channels), 758 .channels = adis16475_channels, 759 .gyro_max_val = 1, 760 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 761 .accel_max_val = 1, 762 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 763 .temp_scale = 100, 764 .int_clk = 2000, 765 .max_dec = 1999, 766 .sync = adis16475_sync_mode, 767 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 768 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 769 }, 770 [ADIS16467_3] = { 771 .name = "adis16467-3", 772 .num_channels = ARRAY_SIZE(adis16475_channels), 773 .channels = adis16475_channels, 774 .gyro_max_val = 1, 775 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 776 .accel_max_val = 1, 777 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 778 .temp_scale = 100, 779 .int_clk = 2000, 780 .max_dec = 1999, 781 .sync = adis16475_sync_mode, 782 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 783 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 784 }, 785 [ADIS16500] = { 786 .name = "adis16500", 787 .num_channels = ARRAY_SIZE(adis16475_channels), 788 .channels = adis16475_channels, 789 .gyro_max_val = 1, 790 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 791 .accel_max_val = 392, 792 .accel_max_scale = 32000 << 16, 793 .temp_scale = 100, 794 .int_clk = 2000, 795 .max_dec = 1999, 796 .sync = adis16475_sync_mode, 797 /* pulse sync not supported */ 798 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 799 .has_burst32 = true, 800 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), 801 }, 802 [ADIS16505_1] = { 803 .name = "adis16505-1", 804 .num_channels = ARRAY_SIZE(adis16475_channels), 805 .channels = adis16475_channels, 806 .gyro_max_val = 1, 807 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 808 .accel_max_val = 78, 809 .accel_max_scale = 32000 << 16, 810 .temp_scale = 100, 811 .int_clk = 2000, 812 .max_dec = 1999, 813 .sync = adis16475_sync_mode, 814 /* pulse sync not supported */ 815 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 816 .has_burst32 = true, 817 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 818 }, 819 [ADIS16505_2] = { 820 .name = "adis16505-2", 821 .num_channels = ARRAY_SIZE(adis16475_channels), 822 .channels = adis16475_channels, 823 .gyro_max_val = 1, 824 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 825 .accel_max_val = 78, 826 .accel_max_scale = 32000 << 16, 827 .temp_scale = 100, 828 .int_clk = 2000, 829 .max_dec = 1999, 830 .sync = adis16475_sync_mode, 831 /* pulse sync not supported */ 832 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 833 .has_burst32 = true, 834 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 835 }, 836 [ADIS16505_3] = { 837 .name = "adis16505-3", 838 .num_channels = ARRAY_SIZE(adis16475_channels), 839 .channels = adis16475_channels, 840 .gyro_max_val = 1, 841 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 842 .accel_max_val = 78, 843 .accel_max_scale = 32000 << 16, 844 .temp_scale = 100, 845 .int_clk = 2000, 846 .max_dec = 1999, 847 .sync = adis16475_sync_mode, 848 /* pulse sync not supported */ 849 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 850 .has_burst32 = true, 851 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 852 }, 853 [ADIS16507_1] = { 854 .name = "adis16507-1", 855 .num_channels = ARRAY_SIZE(adis16475_channels), 856 .channels = adis16475_channels, 857 .gyro_max_val = 1, 858 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 859 .accel_max_val = 392, 860 .accel_max_scale = 32000 << 16, 861 .temp_scale = 100, 862 .int_clk = 2000, 863 .max_dec = 1999, 864 .sync = adis16475_sync_mode, 865 /* pulse sync not supported */ 866 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 867 .has_burst32 = true, 868 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 869 }, 870 [ADIS16507_2] = { 871 .name = "adis16507-2", 872 .num_channels = ARRAY_SIZE(adis16475_channels), 873 .channels = adis16475_channels, 874 .gyro_max_val = 1, 875 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 876 .accel_max_val = 392, 877 .accel_max_scale = 32000 << 16, 878 .temp_scale = 100, 879 .int_clk = 2000, 880 .max_dec = 1999, 881 .sync = adis16475_sync_mode, 882 /* pulse sync not supported */ 883 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 884 .has_burst32 = true, 885 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 886 }, 887 [ADIS16507_3] = { 888 .name = "adis16507-3", 889 .num_channels = ARRAY_SIZE(adis16475_channels), 890 .channels = adis16475_channels, 891 .gyro_max_val = 1, 892 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 893 .accel_max_val = 392, 894 .accel_max_scale = 32000 << 16, 895 .temp_scale = 100, 896 .int_clk = 2000, 897 .max_dec = 1999, 898 .sync = adis16475_sync_mode, 899 /* pulse sync not supported */ 900 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 901 .has_burst32 = true, 902 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 903 }, 904 }; 905 906 static const struct iio_info adis16475_info = { 907 .read_raw = &adis16475_read_raw, 908 .write_raw = &adis16475_write_raw, 909 .update_scan_mode = adis_update_scan_mode, 910 .debugfs_reg_access = adis_debugfs_reg_access, 911 }; 912 913 static struct adis_burst adis16475_burst = { 914 .en = true, 915 .reg_cmd = ADIS16475_REG_GLOB_CMD, 916 /* 917 * adis_update_scan_mode_burst() sets the burst length in respect with 918 * the number of channels and allocates 16 bits for each. However, 919 * adis1647x devices also need space for DIAG_STAT, DATA_CNTR or 920 * TIME_STAMP (depending on the clock mode but for us these bytes are 921 * don't care...) and CRC. 922 */ 923 .extra_len = 3 * sizeof(u16), 924 .burst_max_len = ADIS16475_BURST32_MAX_DATA, 925 }; 926 927 static bool adis16475_validate_crc(const u8 *buffer, u16 crc, 928 const bool burst32) 929 { 930 int i; 931 /* extra 6 elements for low gyro and accel */ 932 const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA : 933 ADIS16475_BURST_MAX_DATA; 934 935 for (i = 0; i < sz - 2; i++) 936 crc -= buffer[i]; 937 938 return crc == 0; 939 } 940 941 static void adis16475_burst32_check(struct adis16475 *st) 942 { 943 int ret; 944 struct adis *adis = &st->adis; 945 946 if (!st->info->has_burst32) 947 return; 948 949 if (st->lsb_flag && !st->burst32) { 950 const u16 en = ADIS16500_BURST32(1); 951 952 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 953 ADIS16500_BURST32_MASK, en); 954 if (ret) 955 return; 956 957 st->burst32 = true; 958 959 /* 960 * In 32-bit mode we need extra 2 bytes for all gyro 961 * and accel channels. 962 */ 963 adis->burst_extra_len = 6 * sizeof(u16); 964 adis->xfer[1].len += 6 * sizeof(u16); 965 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", 966 adis->xfer[1].len); 967 968 } else if (!st->lsb_flag && st->burst32) { 969 const u16 en = ADIS16500_BURST32(0); 970 971 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 972 ADIS16500_BURST32_MASK, en); 973 if (ret) 974 return; 975 976 st->burst32 = false; 977 978 /* Remove the extra bits */ 979 adis->burst_extra_len = 0; 980 adis->xfer[1].len -= 6 * sizeof(u16); 981 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", 982 adis->xfer[1].len); 983 } 984 } 985 986 static irqreturn_t adis16475_trigger_handler(int irq, void *p) 987 { 988 struct iio_poll_func *pf = p; 989 struct iio_dev *indio_dev = pf->indio_dev; 990 struct adis16475 *st = iio_priv(indio_dev); 991 struct adis *adis = &st->adis; 992 int ret, bit, i = 0; 993 __be16 *buffer; 994 u16 crc; 995 bool valid; 996 /* offset until the first element after gyro and accel */ 997 const u8 offset = st->burst32 ? 13 : 7; 998 const u32 cached_spi_speed_hz = adis->spi->max_speed_hz; 999 1000 adis->spi->max_speed_hz = ADIS16475_BURST_MAX_SPEED; 1001 1002 ret = spi_sync(adis->spi, &adis->msg); 1003 if (ret) 1004 return ret; 1005 1006 adis->spi->max_speed_hz = cached_spi_speed_hz; 1007 buffer = adis->buffer; 1008 1009 crc = be16_to_cpu(buffer[offset + 2]); 1010 valid = adis16475_validate_crc(adis->buffer, crc, st->burst32); 1011 if (!valid) { 1012 dev_err(&adis->spi->dev, "Invalid crc\n"); 1013 goto check_burst32; 1014 } 1015 1016 for_each_set_bit(bit, indio_dev->active_scan_mask, 1017 indio_dev->masklength) { 1018 /* 1019 * When burst mode is used, system flags is the first data 1020 * channel in the sequence, but the scan index is 7. 1021 */ 1022 switch (bit) { 1023 case ADIS16475_SCAN_TEMP: 1024 st->data[i++] = buffer[offset]; 1025 break; 1026 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1027 /* 1028 * The first 2 bytes on the received data are the 1029 * DIAG_STAT reg, hence the +1 offset here... 1030 */ 1031 if (st->burst32) { 1032 /* upper 16 */ 1033 st->data[i++] = buffer[bit * 2 + 2]; 1034 /* lower 16 */ 1035 st->data[i++] = buffer[bit * 2 + 1]; 1036 } else { 1037 st->data[i++] = buffer[bit + 1]; 1038 /* 1039 * Don't bother in doing the manual read if the 1040 * device supports burst32. burst32 will be 1041 * enabled in the next call to 1042 * adis16475_burst32_check()... 1043 */ 1044 if (st->lsb_flag && !st->info->has_burst32) { 1045 u16 val = 0; 1046 const u32 reg = ADIS16475_REG_X_GYRO_L + 1047 bit * 4; 1048 1049 adis_read_reg_16(adis, reg, &val); 1050 st->data[i++] = cpu_to_be16(val); 1051 } else { 1052 /* lower not used */ 1053 st->data[i++] = 0; 1054 } 1055 } 1056 break; 1057 } 1058 } 1059 1060 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1061 check_burst32: 1062 /* 1063 * We only check the burst mode at the end of the current capture since 1064 * it takes a full data ready cycle for the device to update the burst 1065 * array. 1066 */ 1067 adis16475_burst32_check(st); 1068 iio_trigger_notify_done(indio_dev->trig); 1069 1070 return IRQ_HANDLED; 1071 } 1072 1073 static void adis16475_disable_clk(void *data) 1074 { 1075 clk_disable_unprepare((struct clk *)data); 1076 } 1077 1078 static int adis16475_config_sync_mode(struct adis16475 *st) 1079 { 1080 int ret; 1081 struct device *dev = &st->adis.spi->dev; 1082 const struct adis16475_sync *sync; 1083 u32 sync_mode; 1084 1085 /* default to internal clk */ 1086 st->clk_freq = st->info->int_clk * 1000; 1087 1088 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); 1089 if (ret) 1090 return 0; 1091 1092 if (sync_mode >= st->info->num_sync) { 1093 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, 1094 st->info->name); 1095 return -EINVAL; 1096 } 1097 1098 sync = &st->info->sync[sync_mode]; 1099 1100 /* All the other modes require external input signal */ 1101 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { 1102 struct clk *clk = devm_clk_get(dev, NULL); 1103 1104 if (IS_ERR(clk)) 1105 return PTR_ERR(clk); 1106 1107 ret = clk_prepare_enable(clk); 1108 if (ret) 1109 return ret; 1110 1111 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk); 1112 if (ret) 1113 return ret; 1114 1115 st->clk_freq = clk_get_rate(clk); 1116 if (st->clk_freq < sync->min_rate || 1117 st->clk_freq > sync->max_rate) { 1118 dev_err(dev, 1119 "Clk rate:%u not in a valid range:[%u %u]\n", 1120 st->clk_freq, sync->min_rate, sync->max_rate); 1121 return -EINVAL; 1122 } 1123 1124 if (sync->sync_mode == ADIS16475_SYNC_SCALED) { 1125 u16 up_scale; 1126 u32 scaled_out_freq = 0; 1127 /* 1128 * If we are in scaled mode, we must have an up_scale. 1129 * In scaled mode the allowable input clock range is 1130 * 1 Hz to 128 Hz, and the allowable output range is 1131 * 1900 to 2100 Hz. Hence, a scale must be given to 1132 * get the allowable output. 1133 */ 1134 ret = device_property_read_u32(dev, 1135 "adi,scaled-output-hz", 1136 &scaled_out_freq); 1137 if (ret) { 1138 dev_err(dev, "adi,scaled-output-hz must be given when in scaled sync mode"); 1139 return -EINVAL; 1140 } else if (scaled_out_freq < 1900 || 1141 scaled_out_freq > 2100) { 1142 dev_err(dev, "Invalid value: %u for adi,scaled-output-hz", 1143 scaled_out_freq); 1144 return -EINVAL; 1145 } 1146 1147 up_scale = DIV_ROUND_CLOSEST(scaled_out_freq, 1148 st->clk_freq); 1149 1150 ret = __adis_write_reg_16(&st->adis, 1151 ADIS16475_REG_UP_SCALE, 1152 up_scale); 1153 if (ret) 1154 return ret; 1155 1156 st->clk_freq = scaled_out_freq; 1157 } 1158 1159 st->clk_freq *= 1000; 1160 } 1161 /* 1162 * Keep in mind that the mask for the clk modes in adis1650* 1163 * chips is different (1100 instead of 11100). However, we 1164 * are not configuring BIT(4) in these chips and the default 1165 * value is 0, so we are fine in doing the below operations. 1166 * I'm keeping this for simplicity and avoiding extra variables 1167 * in chip_info. 1168 */ 1169 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1170 ADIS16475_SYNC_MODE_MASK, sync->sync_mode); 1171 if (ret) 1172 return ret; 1173 1174 usleep_range(250, 260); 1175 1176 return 0; 1177 } 1178 1179 static int adis16475_config_irq_pin(struct adis16475 *st) 1180 { 1181 int ret; 1182 struct irq_data *desc; 1183 u32 irq_type; 1184 u16 val = 0; 1185 u8 polarity; 1186 struct spi_device *spi = st->adis.spi; 1187 1188 desc = irq_get_irq_data(spi->irq); 1189 if (!desc) { 1190 dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq); 1191 return -EINVAL; 1192 } 1193 /* 1194 * It is possible to configure the data ready polarity. Furthermore, we 1195 * need to update the adis struct if we want data ready as active low. 1196 */ 1197 irq_type = irqd_get_trigger_type(desc); 1198 if (irq_type == IRQ_TYPE_EDGE_RISING) { 1199 polarity = 1; 1200 st->adis.irq_flag = IRQF_TRIGGER_RISING; 1201 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1202 polarity = 0; 1203 st->adis.irq_flag = IRQF_TRIGGER_FALLING; 1204 } else { 1205 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1206 irq_type); 1207 return -EINVAL; 1208 } 1209 1210 val = ADIS16475_MSG_CTRL_DR_POL(polarity); 1211 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1212 ADIS16475_MSG_CTRL_DR_POL_MASK, val); 1213 if (ret) 1214 return ret; 1215 /* 1216 * There is a delay writing to any bits written to the MSC_CTRL 1217 * register. It should not be bigger than 200us, so 250 should be more 1218 * than enough! 1219 */ 1220 usleep_range(250, 260); 1221 1222 return 0; 1223 } 1224 1225 static const struct of_device_id adis16475_of_match[] = { 1226 { .compatible = "adi,adis16470", 1227 .data = &adis16475_chip_info[ADIS16470] }, 1228 { .compatible = "adi,adis16475-1", 1229 .data = &adis16475_chip_info[ADIS16475_1] }, 1230 { .compatible = "adi,adis16475-2", 1231 .data = &adis16475_chip_info[ADIS16475_2] }, 1232 { .compatible = "adi,adis16475-3", 1233 .data = &adis16475_chip_info[ADIS16475_3] }, 1234 { .compatible = "adi,adis16477-1", 1235 .data = &adis16475_chip_info[ADIS16477_1] }, 1236 { .compatible = "adi,adis16477-2", 1237 .data = &adis16475_chip_info[ADIS16477_2] }, 1238 { .compatible = "adi,adis16477-3", 1239 .data = &adis16475_chip_info[ADIS16477_3] }, 1240 { .compatible = "adi,adis16465-1", 1241 .data = &adis16475_chip_info[ADIS16465_1] }, 1242 { .compatible = "adi,adis16465-2", 1243 .data = &adis16475_chip_info[ADIS16465_2] }, 1244 { .compatible = "adi,adis16465-3", 1245 .data = &adis16475_chip_info[ADIS16465_3] }, 1246 { .compatible = "adi,adis16467-1", 1247 .data = &adis16475_chip_info[ADIS16467_1] }, 1248 { .compatible = "adi,adis16467-2", 1249 .data = &adis16475_chip_info[ADIS16467_2] }, 1250 { .compatible = "adi,adis16467-3", 1251 .data = &adis16475_chip_info[ADIS16467_3] }, 1252 { .compatible = "adi,adis16500", 1253 .data = &adis16475_chip_info[ADIS16500] }, 1254 { .compatible = "adi,adis16505-1", 1255 .data = &adis16475_chip_info[ADIS16505_1] }, 1256 { .compatible = "adi,adis16505-2", 1257 .data = &adis16475_chip_info[ADIS16505_2] }, 1258 { .compatible = "adi,adis16505-3", 1259 .data = &adis16475_chip_info[ADIS16505_3] }, 1260 { .compatible = "adi,adis16507-1", 1261 .data = &adis16475_chip_info[ADIS16507_1] }, 1262 { .compatible = "adi,adis16507-2", 1263 .data = &adis16475_chip_info[ADIS16507_2] }, 1264 { .compatible = "adi,adis16507-3", 1265 .data = &adis16475_chip_info[ADIS16507_3] }, 1266 { }, 1267 }; 1268 MODULE_DEVICE_TABLE(of, adis16475_of_match); 1269 1270 static int adis16475_probe(struct spi_device *spi) 1271 { 1272 struct iio_dev *indio_dev; 1273 struct adis16475 *st; 1274 int ret; 1275 1276 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1277 if (!indio_dev) 1278 return -ENOMEM; 1279 1280 st = iio_priv(indio_dev); 1281 spi_set_drvdata(spi, indio_dev); 1282 st->adis.burst = &adis16475_burst; 1283 1284 st->info = device_get_match_data(&spi->dev); 1285 if (!st->info) 1286 return -EINVAL; 1287 1288 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); 1289 if (ret) 1290 return ret; 1291 1292 indio_dev->name = st->info->name; 1293 indio_dev->channels = st->info->channels; 1294 indio_dev->num_channels = st->info->num_channels; 1295 indio_dev->info = &adis16475_info; 1296 indio_dev->modes = INDIO_DIRECT_MODE; 1297 1298 ret = __adis_initial_startup(&st->adis); 1299 if (ret) 1300 return ret; 1301 1302 ret = adis16475_config_irq_pin(st); 1303 if (ret) 1304 return ret; 1305 1306 ret = adis16475_config_sync_mode(st); 1307 if (ret) 1308 return ret; 1309 1310 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1311 adis16475_trigger_handler); 1312 if (ret) 1313 return ret; 1314 1315 adis16475_enable_irq(&st->adis, false); 1316 1317 ret = devm_iio_device_register(&spi->dev, indio_dev); 1318 if (ret) 1319 return ret; 1320 1321 adis16475_debugfs_init(indio_dev); 1322 1323 return 0; 1324 } 1325 1326 static struct spi_driver adis16475_driver = { 1327 .driver = { 1328 .name = "adis16475", 1329 .of_match_table = adis16475_of_match, 1330 }, 1331 .probe = adis16475_probe, 1332 }; 1333 module_spi_driver(adis16475_driver); 1334 1335 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1336 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); 1337 MODULE_LICENSE("GPL"); 1338