1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ADIS16475 IMU driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/kernel.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/imu/adis.h> 17 #include <linux/iio/trigger_consumer.h> 18 #include <linux/irq.h> 19 #include <linux/lcm.h> 20 #include <linux/math.h> 21 #include <linux/module.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/property.h> 24 #include <linux/spi/spi.h> 25 26 #define ADIS16475_REG_DIAG_STAT 0x02 27 #define ADIS16475_REG_X_GYRO_L 0x04 28 #define ADIS16475_REG_Y_GYRO_L 0x08 29 #define ADIS16475_REG_Z_GYRO_L 0x0C 30 #define ADIS16475_REG_X_ACCEL_L 0x10 31 #define ADIS16475_REG_Y_ACCEL_L 0x14 32 #define ADIS16475_REG_Z_ACCEL_L 0x18 33 #define ADIS16475_REG_TEMP_OUT 0x1c 34 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 35 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 36 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 37 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c 38 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 39 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 40 #define ADIS16475_REG_FILT_CTRL 0x5c 41 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) 42 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) 43 #define ADIS16475_REG_MSG_CTRL 0x60 44 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) 45 #define ADIS16475_MSG_CTRL_DR_POL(x) \ 46 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) 47 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) 48 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) 49 #define ADIS16475_REG_UP_SCALE 0x62 50 #define ADIS16475_REG_DEC_RATE 0x64 51 #define ADIS16475_REG_GLOB_CMD 0x68 52 #define ADIS16475_REG_FIRM_REV 0x6c 53 #define ADIS16475_REG_FIRM_DM 0x6e 54 #define ADIS16475_REG_FIRM_Y 0x70 55 #define ADIS16475_REG_PROD_ID 0x72 56 #define ADIS16475_REG_SERIAL_NUM 0x74 57 #define ADIS16475_REG_FLASH_CNT 0x7c 58 #define ADIS16500_BURST32_MASK BIT(9) 59 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 60 /* number of data elements in burst mode */ 61 #define ADIS16475_BURST32_MAX_DATA 32 62 #define ADIS16475_BURST_MAX_DATA 20 63 #define ADIS16475_MAX_SCAN_DATA 20 64 /* spi max speed in brust mode */ 65 #define ADIS16475_BURST_MAX_SPEED 1000000 66 #define ADIS16475_LSB_DEC_MASK BIT(0) 67 #define ADIS16475_LSB_FIR_MASK BIT(1) 68 69 enum { 70 ADIS16475_SYNC_DIRECT = 1, 71 ADIS16475_SYNC_SCALED, 72 ADIS16475_SYNC_OUTPUT, 73 ADIS16475_SYNC_PULSE = 5, 74 }; 75 76 struct adis16475_sync { 77 u16 sync_mode; 78 u16 min_rate; 79 u16 max_rate; 80 }; 81 82 struct adis16475_chip_info { 83 const struct iio_chan_spec *channels; 84 const struct adis16475_sync *sync; 85 const struct adis_data adis_data; 86 const char *name; 87 u32 num_channels; 88 u32 gyro_max_val; 89 u32 gyro_max_scale; 90 u32 accel_max_val; 91 u32 accel_max_scale; 92 u32 temp_scale; 93 u32 int_clk; 94 u16 max_dec; 95 u8 num_sync; 96 bool has_burst32; 97 }; 98 99 struct adis16475 { 100 const struct adis16475_chip_info *info; 101 struct adis adis; 102 u32 clk_freq; 103 bool burst32; 104 unsigned long lsb_flag; 105 u16 sync_mode; 106 /* Alignment needed for the timestamp */ 107 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); 108 }; 109 110 enum { 111 ADIS16475_SCAN_GYRO_X, 112 ADIS16475_SCAN_GYRO_Y, 113 ADIS16475_SCAN_GYRO_Z, 114 ADIS16475_SCAN_ACCEL_X, 115 ADIS16475_SCAN_ACCEL_Y, 116 ADIS16475_SCAN_ACCEL_Z, 117 ADIS16475_SCAN_TEMP, 118 ADIS16475_SCAN_DIAG_S_FLAGS, 119 ADIS16475_SCAN_CRC_FAILURE, 120 }; 121 122 static bool low_rate_allow; 123 module_param(low_rate_allow, bool, 0444); 124 MODULE_PARM_DESC(low_rate_allow, 125 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)"); 126 127 #ifdef CONFIG_DEBUG_FS 128 static ssize_t adis16475_show_firmware_revision(struct file *file, 129 char __user *userbuf, 130 size_t count, loff_t *ppos) 131 { 132 struct adis16475 *st = file->private_data; 133 char buf[7]; 134 size_t len; 135 u16 rev; 136 int ret; 137 138 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); 139 if (ret) 140 return ret; 141 142 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 143 144 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 145 } 146 147 static const struct file_operations adis16475_firmware_revision_fops = { 148 .open = simple_open, 149 .read = adis16475_show_firmware_revision, 150 .llseek = default_llseek, 151 .owner = THIS_MODULE, 152 }; 153 154 static ssize_t adis16475_show_firmware_date(struct file *file, 155 char __user *userbuf, 156 size_t count, loff_t *ppos) 157 { 158 struct adis16475 *st = file->private_data; 159 u16 md, year; 160 char buf[12]; 161 size_t len; 162 int ret; 163 164 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); 165 if (ret) 166 return ret; 167 168 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); 169 if (ret) 170 return ret; 171 172 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, 173 year); 174 175 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 176 } 177 178 static const struct file_operations adis16475_firmware_date_fops = { 179 .open = simple_open, 180 .read = adis16475_show_firmware_date, 181 .llseek = default_llseek, 182 .owner = THIS_MODULE, 183 }; 184 185 static int adis16475_show_serial_number(void *arg, u64 *val) 186 { 187 struct adis16475 *st = arg; 188 u16 serial; 189 int ret; 190 191 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); 192 if (ret) 193 return ret; 194 195 *val = serial; 196 197 return 0; 198 } 199 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, 200 adis16475_show_serial_number, NULL, "0x%.4llx\n"); 201 202 static int adis16475_show_product_id(void *arg, u64 *val) 203 { 204 struct adis16475 *st = arg; 205 u16 prod_id; 206 int ret; 207 208 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); 209 if (ret) 210 return ret; 211 212 *val = prod_id; 213 214 return 0; 215 } 216 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, 217 adis16475_show_product_id, NULL, "%llu\n"); 218 219 static int adis16475_show_flash_count(void *arg, u64 *val) 220 { 221 struct adis16475 *st = arg; 222 u32 flash_count; 223 int ret; 224 225 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, 226 &flash_count); 227 if (ret) 228 return ret; 229 230 *val = flash_count; 231 232 return 0; 233 } 234 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, 235 adis16475_show_flash_count, NULL, "%lld\n"); 236 237 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 238 { 239 struct adis16475 *st = iio_priv(indio_dev); 240 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 241 242 debugfs_create_file_unsafe("serial_number", 0400, 243 d, st, &adis16475_serial_number_fops); 244 debugfs_create_file_unsafe("product_id", 0400, 245 d, st, &adis16475_product_id_fops); 246 debugfs_create_file_unsafe("flash_count", 0400, 247 d, st, &adis16475_flash_count_fops); 248 debugfs_create_file("firmware_revision", 0400, 249 d, st, &adis16475_firmware_revision_fops); 250 debugfs_create_file("firmware_date", 0400, d, 251 st, &adis16475_firmware_date_fops); 252 } 253 #else 254 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 255 { 256 } 257 #endif 258 259 static int adis16475_get_freq(struct adis16475 *st, u32 *freq) 260 { 261 int ret; 262 u16 dec; 263 u32 sample_rate = st->clk_freq; 264 265 adis_dev_lock(&st->adis); 266 267 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 268 u16 sync_scale; 269 270 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale); 271 if (ret) 272 goto error; 273 274 sample_rate = st->clk_freq * sync_scale; 275 } 276 277 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); 278 if (ret) 279 goto error; 280 281 adis_dev_unlock(&st->adis); 282 283 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1); 284 285 return 0; 286 error: 287 adis_dev_unlock(&st->adis); 288 return ret; 289 } 290 291 static int adis16475_set_freq(struct adis16475 *st, const u32 freq) 292 { 293 u16 dec; 294 int ret; 295 u32 sample_rate = st->clk_freq; 296 297 if (!freq) 298 return -EINVAL; 299 300 adis_dev_lock(&st->adis); 301 /* 302 * When using sync scaled mode, the input clock needs to be scaled so that we have 303 * an IMU sample rate between (optimally) 1900 and 2100. After this, we can use the 304 * decimation filter to lower the sampling rate in order to get what the user wants. 305 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 306 * the input clock. Hence, calculating the sync_scale dynamically gives us better 307 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 308 * 1. lcm of the input clock and the desired output rate. 309 * 2. get the highest multiple of the previous result lower than the adis max rate. 310 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 311 * and DEC_RATE (to get the user output rate) 312 */ 313 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 314 unsigned long scaled_rate = lcm(st->clk_freq, freq); 315 int sync_scale; 316 317 /* 318 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 319 * solution. In this case, we get the highest multiple of the input clock 320 * lower than the IMU max sample rate. 321 */ 322 if (scaled_rate > 2100000) 323 scaled_rate = 2100000 / st->clk_freq * st->clk_freq; 324 else 325 scaled_rate = 2100000 / scaled_rate * scaled_rate; 326 327 /* 328 * This is not an hard requirement but it's not advised to run the IMU 329 * with a sample rate lower than 4000Hz due to possible undersampling 330 * issues. However, there are users that might really want to take the risk. 331 * Hence, we provide a module parameter for them. If set, we allow sample 332 * rates lower than 4KHz. By default, we won't allow this and we just roundup 333 * the rate to the next multiple of the input clock bigger than 4KHz. This 334 * is done like this as in some cases (when DEC_RATE is 0) might give 335 * us the closest value to the one desired by the user... 336 */ 337 if (scaled_rate < 1900000 && !low_rate_allow) 338 scaled_rate = roundup(1900000, st->clk_freq); 339 340 sync_scale = scaled_rate / st->clk_freq; 341 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale); 342 if (ret) 343 goto error; 344 345 sample_rate = scaled_rate; 346 } 347 348 dec = DIV_ROUND_CLOSEST(sample_rate, freq); 349 350 if (dec) 351 dec--; 352 353 if (dec > st->info->max_dec) 354 dec = st->info->max_dec; 355 356 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); 357 if (ret) 358 goto error; 359 360 /* 361 * If decimation is used, then gyro and accel data will have meaningful 362 * bits on the LSB registers. This info is used on the trigger handler. 363 */ 364 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); 365 366 return 0; 367 error: 368 adis_dev_unlock(&st->adis); 369 return ret; 370 } 371 372 /* The values are approximated. */ 373 static const u32 adis16475_3db_freqs[] = { 374 [0] = 720, /* Filter disabled, full BW (~720Hz) */ 375 [1] = 360, 376 [2] = 164, 377 [3] = 80, 378 [4] = 40, 379 [5] = 20, 380 [6] = 10, 381 }; 382 383 static int adis16475_get_filter(struct adis16475 *st, u32 *filter) 384 { 385 u16 filter_sz; 386 int ret; 387 const int mask = ADIS16475_FILT_CTRL_MASK; 388 389 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); 390 if (ret) 391 return ret; 392 393 *filter = adis16475_3db_freqs[filter_sz & mask]; 394 395 return 0; 396 } 397 398 static int adis16475_set_filter(struct adis16475 *st, const u32 filter) 399 { 400 int i = ARRAY_SIZE(adis16475_3db_freqs); 401 int ret; 402 403 while (--i) { 404 if (adis16475_3db_freqs[i] >= filter) 405 break; 406 } 407 408 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, 409 ADIS16475_FILT_CTRL(i)); 410 if (ret) 411 return ret; 412 413 /* 414 * If FIR is used, then gyro and accel data will have meaningful 415 * bits on the LSB registers. This info is used on the trigger handler. 416 */ 417 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); 418 419 return 0; 420 } 421 422 static const u32 adis16475_calib_regs[] = { 423 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, 424 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, 425 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, 426 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, 427 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, 428 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, 429 }; 430 431 static int adis16475_read_raw(struct iio_dev *indio_dev, 432 const struct iio_chan_spec *chan, 433 int *val, int *val2, long info) 434 { 435 struct adis16475 *st = iio_priv(indio_dev); 436 int ret; 437 u32 tmp; 438 439 switch (info) { 440 case IIO_CHAN_INFO_RAW: 441 return adis_single_conversion(indio_dev, chan, 0, val); 442 case IIO_CHAN_INFO_SCALE: 443 switch (chan->type) { 444 case IIO_ANGL_VEL: 445 *val = st->info->gyro_max_val; 446 *val2 = st->info->gyro_max_scale; 447 return IIO_VAL_FRACTIONAL; 448 case IIO_ACCEL: 449 *val = st->info->accel_max_val; 450 *val2 = st->info->accel_max_scale; 451 return IIO_VAL_FRACTIONAL; 452 case IIO_TEMP: 453 *val = st->info->temp_scale; 454 return IIO_VAL_INT; 455 default: 456 return -EINVAL; 457 } 458 case IIO_CHAN_INFO_CALIBBIAS: 459 ret = adis_read_reg_32(&st->adis, 460 adis16475_calib_regs[chan->scan_index], 461 val); 462 if (ret) 463 return ret; 464 465 return IIO_VAL_INT; 466 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 467 ret = adis16475_get_filter(st, val); 468 if (ret) 469 return ret; 470 471 return IIO_VAL_INT; 472 case IIO_CHAN_INFO_SAMP_FREQ: 473 ret = adis16475_get_freq(st, &tmp); 474 if (ret) 475 return ret; 476 477 *val = tmp / 1000; 478 *val2 = (tmp % 1000) * 1000; 479 return IIO_VAL_INT_PLUS_MICRO; 480 default: 481 return -EINVAL; 482 } 483 } 484 485 static int adis16475_write_raw(struct iio_dev *indio_dev, 486 const struct iio_chan_spec *chan, 487 int val, int val2, long info) 488 { 489 struct adis16475 *st = iio_priv(indio_dev); 490 u32 tmp; 491 492 switch (info) { 493 case IIO_CHAN_INFO_SAMP_FREQ: 494 tmp = val * 1000 + val2 / 1000; 495 return adis16475_set_freq(st, tmp); 496 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 497 return adis16475_set_filter(st, val); 498 case IIO_CHAN_INFO_CALIBBIAS: 499 return adis_write_reg_32(&st->adis, 500 adis16475_calib_regs[chan->scan_index], 501 val); 502 default: 503 return -EINVAL; 504 } 505 } 506 507 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ 508 { \ 509 .type = (_type), \ 510 .modified = 1, \ 511 .channel2 = (_mod), \ 512 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 513 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 514 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 515 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 516 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 517 .address = (_address), \ 518 .scan_index = (_si), \ 519 .scan_type = { \ 520 .sign = 's', \ 521 .realbits = (_r_bits), \ 522 .storagebits = (_s_bits), \ 523 .endianness = IIO_BE, \ 524 }, \ 525 } 526 527 #define ADIS16475_GYRO_CHANNEL(_mod) \ 528 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 529 ADIS16475_REG_ ## _mod ## _GYRO_L, \ 530 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) 531 532 #define ADIS16475_ACCEL_CHANNEL(_mod) \ 533 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 534 ADIS16475_REG_ ## _mod ## _ACCEL_L, \ 535 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) 536 537 #define ADIS16475_TEMP_CHANNEL() { \ 538 .type = IIO_TEMP, \ 539 .indexed = 1, \ 540 .channel = 0, \ 541 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 542 BIT(IIO_CHAN_INFO_SCALE), \ 543 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 544 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 545 .address = ADIS16475_REG_TEMP_OUT, \ 546 .scan_index = ADIS16475_SCAN_TEMP, \ 547 .scan_type = { \ 548 .sign = 's', \ 549 .realbits = 16, \ 550 .storagebits = 16, \ 551 .endianness = IIO_BE, \ 552 }, \ 553 } 554 555 static const struct iio_chan_spec adis16475_channels[] = { 556 ADIS16475_GYRO_CHANNEL(X), 557 ADIS16475_GYRO_CHANNEL(Y), 558 ADIS16475_GYRO_CHANNEL(Z), 559 ADIS16475_ACCEL_CHANNEL(X), 560 ADIS16475_ACCEL_CHANNEL(Y), 561 ADIS16475_ACCEL_CHANNEL(Z), 562 ADIS16475_TEMP_CHANNEL(), 563 IIO_CHAN_SOFT_TIMESTAMP(7) 564 }; 565 566 enum adis16475_variant { 567 ADIS16470, 568 ADIS16475_1, 569 ADIS16475_2, 570 ADIS16475_3, 571 ADIS16477_1, 572 ADIS16477_2, 573 ADIS16477_3, 574 ADIS16465_1, 575 ADIS16465_2, 576 ADIS16465_3, 577 ADIS16467_1, 578 ADIS16467_2, 579 ADIS16467_3, 580 ADIS16500, 581 ADIS16505_1, 582 ADIS16505_2, 583 ADIS16505_3, 584 ADIS16507_1, 585 ADIS16507_2, 586 ADIS16507_3, 587 }; 588 589 enum { 590 ADIS16475_DIAG_STAT_DATA_PATH = 1, 591 ADIS16475_DIAG_STAT_FLASH_MEM, 592 ADIS16475_DIAG_STAT_SPI, 593 ADIS16475_DIAG_STAT_STANDBY, 594 ADIS16475_DIAG_STAT_SENSOR, 595 ADIS16475_DIAG_STAT_MEMORY, 596 ADIS16475_DIAG_STAT_CLK, 597 }; 598 599 static const char * const adis16475_status_error_msgs[] = { 600 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", 601 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", 602 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", 603 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", 604 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", 605 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", 606 [ADIS16475_DIAG_STAT_CLK] = "Clock error", 607 }; 608 609 static int adis16475_enable_irq(struct adis *adis, bool enable) 610 { 611 /* 612 * There is no way to gate the data-ready signal internally inside the 613 * ADIS16475. We can only control it's polarity... 614 */ 615 if (enable) 616 enable_irq(adis->spi->irq); 617 else 618 disable_irq(adis->spi->irq); 619 620 return 0; 621 } 622 623 #define ADIS16475_DATA(_prod_id, _timeouts) \ 624 { \ 625 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ 626 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ 627 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ 628 .prod_id_reg = ADIS16475_REG_PROD_ID, \ 629 .prod_id = (_prod_id), \ 630 .self_test_mask = BIT(2), \ 631 .self_test_reg = ADIS16475_REG_GLOB_CMD, \ 632 .cs_change_delay = 16, \ 633 .read_delay = 5, \ 634 .write_delay = 5, \ 635 .status_error_msgs = adis16475_status_error_msgs, \ 636 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ 637 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ 638 BIT(ADIS16475_DIAG_STAT_SPI) | \ 639 BIT(ADIS16475_DIAG_STAT_STANDBY) | \ 640 BIT(ADIS16475_DIAG_STAT_SENSOR) | \ 641 BIT(ADIS16475_DIAG_STAT_MEMORY) | \ 642 BIT(ADIS16475_DIAG_STAT_CLK), \ 643 .enable_irq = adis16475_enable_irq, \ 644 .timeouts = (_timeouts), \ 645 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ 646 .burst_len = ADIS16475_BURST_MAX_DATA, \ 647 .burst_max_len = ADIS16475_BURST32_MAX_DATA, \ 648 .burst_max_speed_hz = ADIS16475_BURST_MAX_SPEED \ 649 } 650 651 static const struct adis16475_sync adis16475_sync_mode[] = { 652 { ADIS16475_SYNC_OUTPUT }, 653 { ADIS16475_SYNC_DIRECT, 1900, 2100 }, 654 { ADIS16475_SYNC_SCALED, 1, 128 }, 655 { ADIS16475_SYNC_PULSE, 1000, 2100 }, 656 }; 657 658 static const struct adis_timeout adis16475_timeouts = { 659 .reset_ms = 200, 660 .sw_reset_ms = 200, 661 .self_test_ms = 20, 662 }; 663 664 static const struct adis_timeout adis1650x_timeouts = { 665 .reset_ms = 260, 666 .sw_reset_ms = 260, 667 .self_test_ms = 30, 668 }; 669 670 static const struct adis16475_chip_info adis16475_chip_info[] = { 671 [ADIS16470] = { 672 .name = "adis16470", 673 .num_channels = ARRAY_SIZE(adis16475_channels), 674 .channels = adis16475_channels, 675 .gyro_max_val = 1, 676 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 677 .accel_max_val = 1, 678 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 679 .temp_scale = 100, 680 .int_clk = 2000, 681 .max_dec = 1999, 682 .sync = adis16475_sync_mode, 683 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 684 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts), 685 }, 686 [ADIS16475_1] = { 687 .name = "adis16475-1", 688 .num_channels = ARRAY_SIZE(adis16475_channels), 689 .channels = adis16475_channels, 690 .gyro_max_val = 1, 691 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 692 .accel_max_val = 1, 693 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 694 .temp_scale = 100, 695 .int_clk = 2000, 696 .max_dec = 1999, 697 .sync = adis16475_sync_mode, 698 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 699 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 700 }, 701 [ADIS16475_2] = { 702 .name = "adis16475-2", 703 .num_channels = ARRAY_SIZE(adis16475_channels), 704 .channels = adis16475_channels, 705 .gyro_max_val = 1, 706 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 707 .accel_max_val = 1, 708 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 709 .temp_scale = 100, 710 .int_clk = 2000, 711 .max_dec = 1999, 712 .sync = adis16475_sync_mode, 713 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 714 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 715 }, 716 [ADIS16475_3] = { 717 .name = "adis16475-3", 718 .num_channels = ARRAY_SIZE(adis16475_channels), 719 .channels = adis16475_channels, 720 .gyro_max_val = 1, 721 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 722 .accel_max_val = 1, 723 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 724 .temp_scale = 100, 725 .int_clk = 2000, 726 .max_dec = 1999, 727 .sync = adis16475_sync_mode, 728 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 729 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), 730 }, 731 [ADIS16477_1] = { 732 .name = "adis16477-1", 733 .num_channels = ARRAY_SIZE(adis16475_channels), 734 .channels = adis16475_channels, 735 .gyro_max_val = 1, 736 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 737 .accel_max_val = 1, 738 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 739 .temp_scale = 100, 740 .int_clk = 2000, 741 .max_dec = 1999, 742 .sync = adis16475_sync_mode, 743 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 744 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 745 }, 746 [ADIS16477_2] = { 747 .name = "adis16477-2", 748 .num_channels = ARRAY_SIZE(adis16475_channels), 749 .channels = adis16475_channels, 750 .gyro_max_val = 1, 751 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 752 .accel_max_val = 1, 753 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 754 .temp_scale = 100, 755 .int_clk = 2000, 756 .max_dec = 1999, 757 .sync = adis16475_sync_mode, 758 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 759 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 760 }, 761 [ADIS16477_3] = { 762 .name = "adis16477-3", 763 .num_channels = ARRAY_SIZE(adis16475_channels), 764 .channels = adis16475_channels, 765 .gyro_max_val = 1, 766 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 767 .accel_max_val = 1, 768 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 769 .temp_scale = 100, 770 .int_clk = 2000, 771 .max_dec = 1999, 772 .sync = adis16475_sync_mode, 773 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 774 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 775 }, 776 [ADIS16465_1] = { 777 .name = "adis16465-1", 778 .num_channels = ARRAY_SIZE(adis16475_channels), 779 .channels = adis16475_channels, 780 .gyro_max_val = 1, 781 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 782 .accel_max_val = 1, 783 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 784 .temp_scale = 100, 785 .int_clk = 2000, 786 .max_dec = 1999, 787 .sync = adis16475_sync_mode, 788 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 789 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 790 }, 791 [ADIS16465_2] = { 792 .name = "adis16465-2", 793 .num_channels = ARRAY_SIZE(adis16475_channels), 794 .channels = adis16475_channels, 795 .gyro_max_val = 1, 796 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 797 .accel_max_val = 1, 798 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 799 .temp_scale = 100, 800 .int_clk = 2000, 801 .max_dec = 1999, 802 .sync = adis16475_sync_mode, 803 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 804 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 805 }, 806 [ADIS16465_3] = { 807 .name = "adis16465-3", 808 .num_channels = ARRAY_SIZE(adis16475_channels), 809 .channels = adis16475_channels, 810 .gyro_max_val = 1, 811 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 812 .accel_max_val = 1, 813 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 814 .temp_scale = 100, 815 .int_clk = 2000, 816 .max_dec = 1999, 817 .sync = adis16475_sync_mode, 818 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 819 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), 820 }, 821 [ADIS16467_1] = { 822 .name = "adis16467-1", 823 .num_channels = ARRAY_SIZE(adis16475_channels), 824 .channels = adis16475_channels, 825 .gyro_max_val = 1, 826 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 827 .accel_max_val = 1, 828 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 829 .temp_scale = 100, 830 .int_clk = 2000, 831 .max_dec = 1999, 832 .sync = adis16475_sync_mode, 833 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 834 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 835 }, 836 [ADIS16467_2] = { 837 .name = "adis16467-2", 838 .num_channels = ARRAY_SIZE(adis16475_channels), 839 .channels = adis16475_channels, 840 .gyro_max_val = 1, 841 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 842 .accel_max_val = 1, 843 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 844 .temp_scale = 100, 845 .int_clk = 2000, 846 .max_dec = 1999, 847 .sync = adis16475_sync_mode, 848 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 849 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 850 }, 851 [ADIS16467_3] = { 852 .name = "adis16467-3", 853 .num_channels = ARRAY_SIZE(adis16475_channels), 854 .channels = adis16475_channels, 855 .gyro_max_val = 1, 856 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 857 .accel_max_val = 1, 858 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 859 .temp_scale = 100, 860 .int_clk = 2000, 861 .max_dec = 1999, 862 .sync = adis16475_sync_mode, 863 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 864 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), 865 }, 866 [ADIS16500] = { 867 .name = "adis16500", 868 .num_channels = ARRAY_SIZE(adis16475_channels), 869 .channels = adis16475_channels, 870 .gyro_max_val = 1, 871 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 872 .accel_max_val = 392, 873 .accel_max_scale = 32000 << 16, 874 .temp_scale = 100, 875 .int_clk = 2000, 876 .max_dec = 1999, 877 .sync = adis16475_sync_mode, 878 /* pulse sync not supported */ 879 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 880 .has_burst32 = true, 881 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), 882 }, 883 [ADIS16505_1] = { 884 .name = "adis16505-1", 885 .num_channels = ARRAY_SIZE(adis16475_channels), 886 .channels = adis16475_channels, 887 .gyro_max_val = 1, 888 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 889 .accel_max_val = 78, 890 .accel_max_scale = 32000 << 16, 891 .temp_scale = 100, 892 .int_clk = 2000, 893 .max_dec = 1999, 894 .sync = adis16475_sync_mode, 895 /* pulse sync not supported */ 896 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 897 .has_burst32 = true, 898 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 899 }, 900 [ADIS16505_2] = { 901 .name = "adis16505-2", 902 .num_channels = ARRAY_SIZE(adis16475_channels), 903 .channels = adis16475_channels, 904 .gyro_max_val = 1, 905 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 906 .accel_max_val = 78, 907 .accel_max_scale = 32000 << 16, 908 .temp_scale = 100, 909 .int_clk = 2000, 910 .max_dec = 1999, 911 .sync = adis16475_sync_mode, 912 /* pulse sync not supported */ 913 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 914 .has_burst32 = true, 915 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 916 }, 917 [ADIS16505_3] = { 918 .name = "adis16505-3", 919 .num_channels = ARRAY_SIZE(adis16475_channels), 920 .channels = adis16475_channels, 921 .gyro_max_val = 1, 922 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 923 .accel_max_val = 78, 924 .accel_max_scale = 32000 << 16, 925 .temp_scale = 100, 926 .int_clk = 2000, 927 .max_dec = 1999, 928 .sync = adis16475_sync_mode, 929 /* pulse sync not supported */ 930 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 931 .has_burst32 = true, 932 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 933 }, 934 [ADIS16507_1] = { 935 .name = "adis16507-1", 936 .num_channels = ARRAY_SIZE(adis16475_channels), 937 .channels = adis16475_channels, 938 .gyro_max_val = 1, 939 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 940 .accel_max_val = 392, 941 .accel_max_scale = 32000 << 16, 942 .temp_scale = 100, 943 .int_clk = 2000, 944 .max_dec = 1999, 945 .sync = adis16475_sync_mode, 946 /* pulse sync not supported */ 947 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 948 .has_burst32 = true, 949 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 950 }, 951 [ADIS16507_2] = { 952 .name = "adis16507-2", 953 .num_channels = ARRAY_SIZE(adis16475_channels), 954 .channels = adis16475_channels, 955 .gyro_max_val = 1, 956 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 957 .accel_max_val = 392, 958 .accel_max_scale = 32000 << 16, 959 .temp_scale = 100, 960 .int_clk = 2000, 961 .max_dec = 1999, 962 .sync = adis16475_sync_mode, 963 /* pulse sync not supported */ 964 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 965 .has_burst32 = true, 966 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 967 }, 968 [ADIS16507_3] = { 969 .name = "adis16507-3", 970 .num_channels = ARRAY_SIZE(adis16475_channels), 971 .channels = adis16475_channels, 972 .gyro_max_val = 1, 973 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 974 .accel_max_val = 392, 975 .accel_max_scale = 32000 << 16, 976 .temp_scale = 100, 977 .int_clk = 2000, 978 .max_dec = 1999, 979 .sync = adis16475_sync_mode, 980 /* pulse sync not supported */ 981 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 982 .has_burst32 = true, 983 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 984 }, 985 }; 986 987 static const struct iio_info adis16475_info = { 988 .read_raw = &adis16475_read_raw, 989 .write_raw = &adis16475_write_raw, 990 .update_scan_mode = adis_update_scan_mode, 991 .debugfs_reg_access = adis_debugfs_reg_access, 992 }; 993 994 static bool adis16475_validate_crc(const u8 *buffer, u16 crc, 995 const bool burst32) 996 { 997 int i; 998 /* extra 6 elements for low gyro and accel */ 999 const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA : 1000 ADIS16475_BURST_MAX_DATA; 1001 1002 for (i = 0; i < sz - 2; i++) 1003 crc -= buffer[i]; 1004 1005 return crc == 0; 1006 } 1007 1008 static void adis16475_burst32_check(struct adis16475 *st) 1009 { 1010 int ret; 1011 struct adis *adis = &st->adis; 1012 1013 if (!st->info->has_burst32) 1014 return; 1015 1016 if (st->lsb_flag && !st->burst32) { 1017 const u16 en = ADIS16500_BURST32(1); 1018 1019 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1020 ADIS16500_BURST32_MASK, en); 1021 if (ret) 1022 return; 1023 1024 st->burst32 = true; 1025 1026 /* 1027 * In 32-bit mode we need extra 2 bytes for all gyro 1028 * and accel channels. 1029 */ 1030 adis->burst_extra_len = 6 * sizeof(u16); 1031 adis->xfer[1].len += 6 * sizeof(u16); 1032 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", 1033 adis->xfer[1].len); 1034 1035 } else if (!st->lsb_flag && st->burst32) { 1036 const u16 en = ADIS16500_BURST32(0); 1037 1038 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1039 ADIS16500_BURST32_MASK, en); 1040 if (ret) 1041 return; 1042 1043 st->burst32 = false; 1044 1045 /* Remove the extra bits */ 1046 adis->burst_extra_len = 0; 1047 adis->xfer[1].len -= 6 * sizeof(u16); 1048 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", 1049 adis->xfer[1].len); 1050 } 1051 } 1052 1053 static irqreturn_t adis16475_trigger_handler(int irq, void *p) 1054 { 1055 struct iio_poll_func *pf = p; 1056 struct iio_dev *indio_dev = pf->indio_dev; 1057 struct adis16475 *st = iio_priv(indio_dev); 1058 struct adis *adis = &st->adis; 1059 int ret, bit, i = 0; 1060 __be16 *buffer; 1061 u16 crc; 1062 bool valid; 1063 /* offset until the first element after gyro and accel */ 1064 const u8 offset = st->burst32 ? 13 : 7; 1065 1066 ret = spi_sync(adis->spi, &adis->msg); 1067 if (ret) 1068 goto check_burst32; 1069 1070 buffer = adis->buffer; 1071 1072 crc = be16_to_cpu(buffer[offset + 2]); 1073 valid = adis16475_validate_crc(adis->buffer, crc, st->burst32); 1074 if (!valid) { 1075 dev_err(&adis->spi->dev, "Invalid crc\n"); 1076 goto check_burst32; 1077 } 1078 1079 for_each_set_bit(bit, indio_dev->active_scan_mask, 1080 indio_dev->masklength) { 1081 /* 1082 * When burst mode is used, system flags is the first data 1083 * channel in the sequence, but the scan index is 7. 1084 */ 1085 switch (bit) { 1086 case ADIS16475_SCAN_TEMP: 1087 st->data[i++] = buffer[offset]; 1088 break; 1089 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1090 /* 1091 * The first 2 bytes on the received data are the 1092 * DIAG_STAT reg, hence the +1 offset here... 1093 */ 1094 if (st->burst32) { 1095 /* upper 16 */ 1096 st->data[i++] = buffer[bit * 2 + 2]; 1097 /* lower 16 */ 1098 st->data[i++] = buffer[bit * 2 + 1]; 1099 } else { 1100 st->data[i++] = buffer[bit + 1]; 1101 /* 1102 * Don't bother in doing the manual read if the 1103 * device supports burst32. burst32 will be 1104 * enabled in the next call to 1105 * adis16475_burst32_check()... 1106 */ 1107 if (st->lsb_flag && !st->info->has_burst32) { 1108 u16 val = 0; 1109 const u32 reg = ADIS16475_REG_X_GYRO_L + 1110 bit * 4; 1111 1112 adis_read_reg_16(adis, reg, &val); 1113 st->data[i++] = cpu_to_be16(val); 1114 } else { 1115 /* lower not used */ 1116 st->data[i++] = 0; 1117 } 1118 } 1119 break; 1120 } 1121 } 1122 1123 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1124 check_burst32: 1125 /* 1126 * We only check the burst mode at the end of the current capture since 1127 * it takes a full data ready cycle for the device to update the burst 1128 * array. 1129 */ 1130 adis16475_burst32_check(st); 1131 iio_trigger_notify_done(indio_dev->trig); 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 static void adis16475_disable_clk(void *data) 1137 { 1138 clk_disable_unprepare((struct clk *)data); 1139 } 1140 1141 static int adis16475_config_sync_mode(struct adis16475 *st) 1142 { 1143 int ret; 1144 struct device *dev = &st->adis.spi->dev; 1145 const struct adis16475_sync *sync; 1146 u32 sync_mode; 1147 1148 /* default to internal clk */ 1149 st->clk_freq = st->info->int_clk * 1000; 1150 1151 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); 1152 if (ret) 1153 return 0; 1154 1155 if (sync_mode >= st->info->num_sync) { 1156 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, 1157 st->info->name); 1158 return -EINVAL; 1159 } 1160 1161 sync = &st->info->sync[sync_mode]; 1162 st->sync_mode = sync->sync_mode; 1163 1164 /* All the other modes require external input signal */ 1165 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { 1166 struct clk *clk = devm_clk_get(dev, NULL); 1167 1168 if (IS_ERR(clk)) 1169 return PTR_ERR(clk); 1170 1171 ret = clk_prepare_enable(clk); 1172 if (ret) 1173 return ret; 1174 1175 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk); 1176 if (ret) 1177 return ret; 1178 1179 st->clk_freq = clk_get_rate(clk); 1180 if (st->clk_freq < sync->min_rate || 1181 st->clk_freq > sync->max_rate) { 1182 dev_err(dev, 1183 "Clk rate:%u not in a valid range:[%u %u]\n", 1184 st->clk_freq, sync->min_rate, sync->max_rate); 1185 return -EINVAL; 1186 } 1187 1188 if (sync->sync_mode == ADIS16475_SYNC_SCALED) { 1189 u16 up_scale; 1190 1191 /* 1192 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale. 1193 * Hence, default the IMU sample rate to the highest multiple of the input 1194 * clock lower than the IMU max sample rate. The optimal range is 1195 * 1900-2100 sps... 1196 */ 1197 up_scale = 2100 / st->clk_freq; 1198 1199 ret = __adis_write_reg_16(&st->adis, 1200 ADIS16475_REG_UP_SCALE, 1201 up_scale); 1202 if (ret) 1203 return ret; 1204 } 1205 1206 st->clk_freq *= 1000; 1207 } 1208 /* 1209 * Keep in mind that the mask for the clk modes in adis1650* 1210 * chips is different (1100 instead of 11100). However, we 1211 * are not configuring BIT(4) in these chips and the default 1212 * value is 0, so we are fine in doing the below operations. 1213 * I'm keeping this for simplicity and avoiding extra variables 1214 * in chip_info. 1215 */ 1216 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1217 ADIS16475_SYNC_MODE_MASK, sync->sync_mode); 1218 if (ret) 1219 return ret; 1220 1221 usleep_range(250, 260); 1222 1223 return 0; 1224 } 1225 1226 static int adis16475_config_irq_pin(struct adis16475 *st) 1227 { 1228 int ret; 1229 struct irq_data *desc; 1230 u32 irq_type; 1231 u16 val = 0; 1232 u8 polarity; 1233 struct spi_device *spi = st->adis.spi; 1234 1235 desc = irq_get_irq_data(spi->irq); 1236 if (!desc) { 1237 dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq); 1238 return -EINVAL; 1239 } 1240 /* 1241 * It is possible to configure the data ready polarity. Furthermore, we 1242 * need to update the adis struct if we want data ready as active low. 1243 */ 1244 irq_type = irqd_get_trigger_type(desc); 1245 if (irq_type == IRQ_TYPE_EDGE_RISING) { 1246 polarity = 1; 1247 st->adis.irq_flag = IRQF_TRIGGER_RISING; 1248 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1249 polarity = 0; 1250 st->adis.irq_flag = IRQF_TRIGGER_FALLING; 1251 } else { 1252 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1253 irq_type); 1254 return -EINVAL; 1255 } 1256 1257 /* We cannot mask the interrupt so ensure it's not enabled at request */ 1258 st->adis.irq_flag |= IRQF_NO_AUTOEN; 1259 1260 val = ADIS16475_MSG_CTRL_DR_POL(polarity); 1261 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1262 ADIS16475_MSG_CTRL_DR_POL_MASK, val); 1263 if (ret) 1264 return ret; 1265 /* 1266 * There is a delay writing to any bits written to the MSC_CTRL 1267 * register. It should not be bigger than 200us, so 250 should be more 1268 * than enough! 1269 */ 1270 usleep_range(250, 260); 1271 1272 return 0; 1273 } 1274 1275 static const struct of_device_id adis16475_of_match[] = { 1276 { .compatible = "adi,adis16470", 1277 .data = &adis16475_chip_info[ADIS16470] }, 1278 { .compatible = "adi,adis16475-1", 1279 .data = &adis16475_chip_info[ADIS16475_1] }, 1280 { .compatible = "adi,adis16475-2", 1281 .data = &adis16475_chip_info[ADIS16475_2] }, 1282 { .compatible = "adi,adis16475-3", 1283 .data = &adis16475_chip_info[ADIS16475_3] }, 1284 { .compatible = "adi,adis16477-1", 1285 .data = &adis16475_chip_info[ADIS16477_1] }, 1286 { .compatible = "adi,adis16477-2", 1287 .data = &adis16475_chip_info[ADIS16477_2] }, 1288 { .compatible = "adi,adis16477-3", 1289 .data = &adis16475_chip_info[ADIS16477_3] }, 1290 { .compatible = "adi,adis16465-1", 1291 .data = &adis16475_chip_info[ADIS16465_1] }, 1292 { .compatible = "adi,adis16465-2", 1293 .data = &adis16475_chip_info[ADIS16465_2] }, 1294 { .compatible = "adi,adis16465-3", 1295 .data = &adis16475_chip_info[ADIS16465_3] }, 1296 { .compatible = "adi,adis16467-1", 1297 .data = &adis16475_chip_info[ADIS16467_1] }, 1298 { .compatible = "adi,adis16467-2", 1299 .data = &adis16475_chip_info[ADIS16467_2] }, 1300 { .compatible = "adi,adis16467-3", 1301 .data = &adis16475_chip_info[ADIS16467_3] }, 1302 { .compatible = "adi,adis16500", 1303 .data = &adis16475_chip_info[ADIS16500] }, 1304 { .compatible = "adi,adis16505-1", 1305 .data = &adis16475_chip_info[ADIS16505_1] }, 1306 { .compatible = "adi,adis16505-2", 1307 .data = &adis16475_chip_info[ADIS16505_2] }, 1308 { .compatible = "adi,adis16505-3", 1309 .data = &adis16475_chip_info[ADIS16505_3] }, 1310 { .compatible = "adi,adis16507-1", 1311 .data = &adis16475_chip_info[ADIS16507_1] }, 1312 { .compatible = "adi,adis16507-2", 1313 .data = &adis16475_chip_info[ADIS16507_2] }, 1314 { .compatible = "adi,adis16507-3", 1315 .data = &adis16475_chip_info[ADIS16507_3] }, 1316 { }, 1317 }; 1318 MODULE_DEVICE_TABLE(of, adis16475_of_match); 1319 1320 static int adis16475_probe(struct spi_device *spi) 1321 { 1322 struct iio_dev *indio_dev; 1323 struct adis16475 *st; 1324 int ret; 1325 1326 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1327 if (!indio_dev) 1328 return -ENOMEM; 1329 1330 st = iio_priv(indio_dev); 1331 1332 st->info = device_get_match_data(&spi->dev); 1333 if (!st->info) 1334 return -EINVAL; 1335 1336 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); 1337 if (ret) 1338 return ret; 1339 1340 indio_dev->name = st->info->name; 1341 indio_dev->channels = st->info->channels; 1342 indio_dev->num_channels = st->info->num_channels; 1343 indio_dev->info = &adis16475_info; 1344 indio_dev->modes = INDIO_DIRECT_MODE; 1345 1346 ret = __adis_initial_startup(&st->adis); 1347 if (ret) 1348 return ret; 1349 1350 ret = adis16475_config_irq_pin(st); 1351 if (ret) 1352 return ret; 1353 1354 ret = adis16475_config_sync_mode(st); 1355 if (ret) 1356 return ret; 1357 1358 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1359 adis16475_trigger_handler); 1360 if (ret) 1361 return ret; 1362 1363 ret = devm_iio_device_register(&spi->dev, indio_dev); 1364 if (ret) 1365 return ret; 1366 1367 adis16475_debugfs_init(indio_dev); 1368 1369 return 0; 1370 } 1371 1372 static struct spi_driver adis16475_driver = { 1373 .driver = { 1374 .name = "adis16475", 1375 .of_match_table = adis16475_of_match, 1376 }, 1377 .probe = adis16475_probe, 1378 }; 1379 module_spi_driver(adis16475_driver); 1380 1381 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1382 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); 1383 MODULE_LICENSE("GPL"); 1384