1 /* 2 * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor 3 * 4 * Copyright (C) 2017 Matt Ranostay <matt@ranostay.consulting> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * TODO: proximity power saving feature 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/err.h> 24 #include <linux/irq.h> 25 #include <linux/i2c.h> 26 #include <linux/mutex.h> 27 #include <linux/of.h> 28 #include <linux/regmap.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/buffer.h> 31 #include <linux/iio/kfifo_buf.h> 32 33 #define MAX30102_REGMAP_NAME "max30102_regmap" 34 #define MAX30102_DRV_NAME "max30102" 35 36 #define MAX30102_REG_INT_STATUS 0x00 37 #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0) 38 #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4) 39 #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5) 40 #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6) 41 #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7) 42 43 #define MAX30102_REG_INT_ENABLE 0x02 44 #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4) 45 #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5) 46 #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6) 47 #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7) 48 #define MAX30102_REG_INT_ENABLE_MASK 0xf0 49 #define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4 50 51 #define MAX30102_REG_FIFO_WR_PTR 0x04 52 #define MAX30102_REG_FIFO_OVR_CTR 0x05 53 #define MAX30102_REG_FIFO_RD_PTR 0x06 54 #define MAX30102_REG_FIFO_DATA 0x07 55 #define MAX30102_REG_FIFO_DATA_ENTRY_LEN 6 56 57 #define MAX30102_REG_FIFO_CONFIG 0x08 58 #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1) 59 #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5 60 #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0) 61 62 #define MAX30102_REG_MODE_CONFIG 0x09 63 #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */ 64 #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */ 65 #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */ 66 #define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0) 67 #define MAX30102_REG_MODE_CONFIG_PWR BIT(7) 68 69 #define MAX30102_REG_SPO2_CONFIG 0x0a 70 #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03 71 #define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03 72 #define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07 73 #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2 74 #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0) 75 #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5 76 77 #define MAX30102_REG_RED_LED_CONFIG 0x0c 78 #define MAX30102_REG_IR_LED_CONFIG 0x0d 79 80 #define MAX30102_REG_TEMP_CONFIG 0x21 81 #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0) 82 83 #define MAX30102_REG_TEMP_INTEGER 0x1f 84 #define MAX30102_REG_TEMP_FRACTION 0x20 85 86 struct max30102_data { 87 struct i2c_client *client; 88 struct iio_dev *indio_dev; 89 struct mutex lock; 90 struct regmap *regmap; 91 92 u8 buffer[8]; 93 __be32 processed_buffer[2]; /* 2 x 18-bit (padded to 32-bits) */ 94 }; 95 96 static const struct regmap_config max30102_regmap_config = { 97 .name = MAX30102_REGMAP_NAME, 98 99 .reg_bits = 8, 100 .val_bits = 8, 101 }; 102 103 static const unsigned long max30102_scan_masks[] = {0x3, 0}; 104 105 static const struct iio_chan_spec max30102_channels[] = { 106 { 107 .type = IIO_INTENSITY, 108 .channel2 = IIO_MOD_LIGHT_RED, 109 .modified = 1, 110 111 .scan_index = 0, 112 .scan_type = { 113 .sign = 'u', 114 .shift = 8, 115 .realbits = 18, 116 .storagebits = 32, 117 .endianness = IIO_BE, 118 }, 119 }, 120 { 121 .type = IIO_INTENSITY, 122 .channel2 = IIO_MOD_LIGHT_IR, 123 .modified = 1, 124 125 .scan_index = 1, 126 .scan_type = { 127 .sign = 'u', 128 .shift = 8, 129 .realbits = 18, 130 .storagebits = 32, 131 .endianness = IIO_BE, 132 }, 133 }, 134 { 135 .type = IIO_TEMP, 136 .info_mask_separate = 137 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 138 .scan_index = -1, 139 }, 140 }; 141 142 static int max30102_set_powermode(struct max30102_data *data, bool state) 143 { 144 return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG, 145 MAX30102_REG_MODE_CONFIG_PWR, 146 state ? 0 : MAX30102_REG_MODE_CONFIG_PWR); 147 } 148 149 static int max30102_buffer_postenable(struct iio_dev *indio_dev) 150 { 151 struct max30102_data *data = iio_priv(indio_dev); 152 153 return max30102_set_powermode(data, true); 154 } 155 156 static int max30102_buffer_predisable(struct iio_dev *indio_dev) 157 { 158 struct max30102_data *data = iio_priv(indio_dev); 159 160 return max30102_set_powermode(data, false); 161 } 162 163 static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = { 164 .postenable = max30102_buffer_postenable, 165 .predisable = max30102_buffer_predisable, 166 }; 167 168 static inline int max30102_fifo_count(struct max30102_data *data) 169 { 170 unsigned int val; 171 int ret; 172 173 ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val); 174 if (ret) 175 return ret; 176 177 /* FIFO has one sample slot left */ 178 if (val & MAX30102_REG_INT_STATUS_FIFO_RDY) 179 return 1; 180 181 return 0; 182 } 183 184 static int max30102_read_measurement(struct max30102_data *data) 185 { 186 int ret; 187 u8 *buffer = (u8 *) &data->buffer; 188 189 ret = i2c_smbus_read_i2c_block_data(data->client, 190 MAX30102_REG_FIFO_DATA, 191 MAX30102_REG_FIFO_DATA_ENTRY_LEN, 192 buffer); 193 194 memcpy(&data->processed_buffer[0], &buffer[0], 3); 195 memcpy(&data->processed_buffer[1], &buffer[3], 3); 196 197 return (ret == MAX30102_REG_FIFO_DATA_ENTRY_LEN) ? 0 : -EINVAL; 198 } 199 200 static irqreturn_t max30102_interrupt_handler(int irq, void *private) 201 { 202 struct iio_dev *indio_dev = private; 203 struct max30102_data *data = iio_priv(indio_dev); 204 int ret, cnt = 0; 205 206 mutex_lock(&data->lock); 207 208 while (cnt || (cnt = max30102_fifo_count(data)) > 0) { 209 ret = max30102_read_measurement(data); 210 if (ret) 211 break; 212 213 iio_push_to_buffers(data->indio_dev, data->processed_buffer); 214 cnt--; 215 } 216 217 mutex_unlock(&data->lock); 218 219 return IRQ_HANDLED; 220 } 221 222 static int max30102_get_current_idx(unsigned int val, int *reg) 223 { 224 /* each step is 0.200 mA */ 225 *reg = val / 200; 226 227 return *reg > 0xff ? -EINVAL : 0; 228 } 229 230 static int max30102_led_init(struct max30102_data *data) 231 { 232 struct device *dev = &data->client->dev; 233 struct device_node *np = dev->of_node; 234 unsigned int val; 235 int reg, ret; 236 237 ret = of_property_read_u32(np, "maxim,red-led-current-microamp", &val); 238 if (ret) { 239 dev_info(dev, "no red-led-current-microamp set\n"); 240 241 /* Default to 7 mA RED LED */ 242 val = 7000; 243 } 244 245 ret = max30102_get_current_idx(val, ®); 246 if (ret) { 247 dev_err(dev, "invalid RED LED current setting %d\n", val); 248 return ret; 249 } 250 251 ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg); 252 if (ret) 253 return ret; 254 255 ret = of_property_read_u32(np, "maxim,ir-led-current-microamp", &val); 256 if (ret) { 257 dev_info(dev, "no ir-led-current-microamp set\n"); 258 259 /* Default to 7 mA IR LED */ 260 val = 7000; 261 } 262 263 ret = max30102_get_current_idx(val, ®); 264 if (ret) { 265 dev_err(dev, "invalid IR LED current setting %d\n", val); 266 return ret; 267 } 268 269 return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg); 270 } 271 272 static int max30102_chip_init(struct max30102_data *data) 273 { 274 int ret; 275 276 /* setup LED current settings */ 277 ret = max30102_led_init(data); 278 if (ret) 279 return ret; 280 281 /* enable 18-bit HR + SPO2 readings at 400Hz */ 282 ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG, 283 (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS 284 << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) | 285 (MAX30102_REG_SPO2_CONFIG_SR_400HZ 286 << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) | 287 MAX30102_REG_SPO2_CONFIG_PULSE_411_US); 288 if (ret) 289 return ret; 290 291 /* enable HR + SPO2 mode */ 292 ret = regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG, 293 MAX30102_REG_MODE_CONFIG_MODE_MASK, 294 MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2); 295 if (ret) 296 return ret; 297 298 /* average 4 samples + generate FIFO interrupt */ 299 ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG, 300 (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES 301 << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) | 302 MAX30102_REG_FIFO_CONFIG_AFULL); 303 if (ret) 304 return ret; 305 306 /* enable FIFO interrupt */ 307 return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE, 308 MAX30102_REG_INT_ENABLE_MASK, 309 MAX30102_REG_INT_ENABLE_FIFO_EN); 310 } 311 312 static int max30102_read_temp(struct max30102_data *data, int *val) 313 { 314 int ret; 315 unsigned int reg; 316 317 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, ®); 318 if (ret < 0) 319 return ret; 320 *val = reg << 4; 321 322 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, ®); 323 if (ret < 0) 324 return ret; 325 326 *val |= reg & 0xf; 327 *val = sign_extend32(*val, 11); 328 329 return 0; 330 } 331 332 static int max30102_get_temp(struct max30102_data *data, int *val) 333 { 334 int ret; 335 336 /* start acquisition */ 337 ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG, 338 MAX30102_REG_TEMP_CONFIG_TEMP_EN, 339 MAX30102_REG_TEMP_CONFIG_TEMP_EN); 340 if (ret) 341 return ret; 342 343 msleep(35); 344 345 return max30102_read_temp(data, val); 346 } 347 348 static int max30102_read_raw(struct iio_dev *indio_dev, 349 struct iio_chan_spec const *chan, 350 int *val, int *val2, long mask) 351 { 352 struct max30102_data *data = iio_priv(indio_dev); 353 int ret = -EINVAL; 354 355 switch (mask) { 356 case IIO_CHAN_INFO_RAW: 357 /* 358 * Temperature reading can only be acquired while engine 359 * is running 360 */ 361 mutex_lock(&indio_dev->mlock); 362 363 if (!iio_buffer_enabled(indio_dev)) 364 ret = -EBUSY; 365 else { 366 ret = max30102_get_temp(data, val); 367 if (!ret) 368 ret = IIO_VAL_INT; 369 } 370 371 mutex_unlock(&indio_dev->mlock); 372 break; 373 case IIO_CHAN_INFO_SCALE: 374 *val = 1; /* 0.0625 */ 375 *val2 = 16; 376 ret = IIO_VAL_FRACTIONAL; 377 break; 378 } 379 380 return ret; 381 } 382 383 static const struct iio_info max30102_info = { 384 .read_raw = max30102_read_raw, 385 }; 386 387 static int max30102_probe(struct i2c_client *client, 388 const struct i2c_device_id *id) 389 { 390 struct max30102_data *data; 391 struct iio_buffer *buffer; 392 struct iio_dev *indio_dev; 393 int ret; 394 395 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 396 if (!indio_dev) 397 return -ENOMEM; 398 399 buffer = devm_iio_kfifo_allocate(&client->dev); 400 if (!buffer) 401 return -ENOMEM; 402 403 iio_device_attach_buffer(indio_dev, buffer); 404 405 indio_dev->name = MAX30102_DRV_NAME; 406 indio_dev->channels = max30102_channels; 407 indio_dev->info = &max30102_info; 408 indio_dev->num_channels = ARRAY_SIZE(max30102_channels); 409 indio_dev->available_scan_masks = max30102_scan_masks; 410 indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE); 411 indio_dev->setup_ops = &max30102_buffer_setup_ops; 412 indio_dev->dev.parent = &client->dev; 413 414 data = iio_priv(indio_dev); 415 data->indio_dev = indio_dev; 416 data->client = client; 417 418 mutex_init(&data->lock); 419 i2c_set_clientdata(client, indio_dev); 420 421 data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config); 422 if (IS_ERR(data->regmap)) { 423 dev_err(&client->dev, "regmap initialization failed\n"); 424 return PTR_ERR(data->regmap); 425 } 426 427 ret = max30102_set_powermode(data, false); 428 if (ret) 429 return ret; 430 431 ret = max30102_chip_init(data); 432 if (ret) 433 return ret; 434 435 if (client->irq <= 0) { 436 dev_err(&client->dev, "no valid irq defined\n"); 437 return -EINVAL; 438 } 439 440 ret = devm_request_threaded_irq(&client->dev, client->irq, 441 NULL, max30102_interrupt_handler, 442 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 443 "max30102_irq", indio_dev); 444 if (ret) { 445 dev_err(&client->dev, "request irq (%d) failed\n", client->irq); 446 return ret; 447 } 448 449 return iio_device_register(indio_dev); 450 } 451 452 static int max30102_remove(struct i2c_client *client) 453 { 454 struct iio_dev *indio_dev = i2c_get_clientdata(client); 455 struct max30102_data *data = iio_priv(indio_dev); 456 457 iio_device_unregister(indio_dev); 458 max30102_set_powermode(data, false); 459 460 return 0; 461 } 462 463 static const struct i2c_device_id max30102_id[] = { 464 { "max30102", 0 }, 465 {} 466 }; 467 MODULE_DEVICE_TABLE(i2c, max30102_id); 468 469 static const struct of_device_id max30102_dt_ids[] = { 470 { .compatible = "maxim,max30102" }, 471 { } 472 }; 473 MODULE_DEVICE_TABLE(of, max30102_dt_ids); 474 475 static struct i2c_driver max30102_driver = { 476 .driver = { 477 .name = MAX30102_DRV_NAME, 478 .of_match_table = of_match_ptr(max30102_dt_ids), 479 }, 480 .probe = max30102_probe, 481 .remove = max30102_remove, 482 .id_table = max30102_id, 483 }; 484 module_i2c_driver(max30102_driver); 485 486 MODULE_AUTHOR("Matt Ranostay <matt@ranostay.consulting>"); 487 MODULE_DESCRIPTION("MAX30102 heart rate and pulse oximeter sensor"); 488 MODULE_LICENSE("GPL"); 489