1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/random.h> 31 #include <linux/slab.h> 32 33 #include "mpu3050.h" 34 35 #define MPU3050_CHIP_ID 0x68 36 #define MPU3050_CHIP_ID_MASK 0x7E 37 38 /* 39 * Register map: anything suffixed *_H is a big-endian high byte and always 40 * followed by the corresponding low byte (*_L) even though these are not 41 * explicitly included in the register definitions. 42 */ 43 #define MPU3050_CHIP_ID_REG 0x00 44 #define MPU3050_PRODUCT_ID_REG 0x01 45 #define MPU3050_XG_OFFS_TC 0x05 46 #define MPU3050_YG_OFFS_TC 0x08 47 #define MPU3050_ZG_OFFS_TC 0x0B 48 #define MPU3050_X_OFFS_USR_H 0x0C 49 #define MPU3050_Y_OFFS_USR_H 0x0E 50 #define MPU3050_Z_OFFS_USR_H 0x10 51 #define MPU3050_FIFO_EN 0x12 52 #define MPU3050_AUX_VDDIO 0x13 53 #define MPU3050_SLV_ADDR 0x14 54 #define MPU3050_SMPLRT_DIV 0x15 55 #define MPU3050_DLPF_FS_SYNC 0x16 56 #define MPU3050_INT_CFG 0x17 57 #define MPU3050_AUX_ADDR 0x18 58 #define MPU3050_INT_STATUS 0x1A 59 #define MPU3050_TEMP_H 0x1B 60 #define MPU3050_XOUT_H 0x1D 61 #define MPU3050_YOUT_H 0x1F 62 #define MPU3050_ZOUT_H 0x21 63 #define MPU3050_DMP_CFG1 0x35 64 #define MPU3050_DMP_CFG2 0x36 65 #define MPU3050_BANK_SEL 0x37 66 #define MPU3050_MEM_START_ADDR 0x38 67 #define MPU3050_MEM_R_W 0x39 68 #define MPU3050_FIFO_COUNT_H 0x3A 69 #define MPU3050_FIFO_R 0x3C 70 #define MPU3050_USR_CTRL 0x3D 71 #define MPU3050_PWR_MGM 0x3E 72 73 /* MPU memory bank read options */ 74 #define MPU3050_MEM_PRFTCH BIT(5) 75 #define MPU3050_MEM_USER_BANK BIT(4) 76 /* Bits 8-11 select memory bank */ 77 #define MPU3050_MEM_RAM_BANK_0 0 78 #define MPU3050_MEM_RAM_BANK_1 1 79 #define MPU3050_MEM_RAM_BANK_2 2 80 #define MPU3050_MEM_RAM_BANK_3 3 81 #define MPU3050_MEM_OTP_BANK_0 4 82 83 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 84 85 /* Register bits */ 86 87 /* FIFO Enable */ 88 #define MPU3050_FIFO_EN_FOOTER BIT(0) 89 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 90 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 91 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 92 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 93 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 94 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 95 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 96 97 /* 98 * Digital Low Pass filter (DLPF) 99 * Full Scale (FS) 100 * and Synchronization 101 */ 102 #define MPU3050_EXT_SYNC_NONE 0x00 103 #define MPU3050_EXT_SYNC_TEMP 0x20 104 #define MPU3050_EXT_SYNC_GYROX 0x40 105 #define MPU3050_EXT_SYNC_GYROY 0x60 106 #define MPU3050_EXT_SYNC_GYROZ 0x80 107 #define MPU3050_EXT_SYNC_ACCELX 0xA0 108 #define MPU3050_EXT_SYNC_ACCELY 0xC0 109 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 110 #define MPU3050_EXT_SYNC_MASK 0xE0 111 #define MPU3050_EXT_SYNC_SHIFT 5 112 113 #define MPU3050_FS_250DPS 0x00 114 #define MPU3050_FS_500DPS 0x08 115 #define MPU3050_FS_1000DPS 0x10 116 #define MPU3050_FS_2000DPS 0x18 117 #define MPU3050_FS_MASK 0x18 118 #define MPU3050_FS_SHIFT 3 119 120 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 121 #define MPU3050_DLPF_CFG_188HZ 0x01 122 #define MPU3050_DLPF_CFG_98HZ 0x02 123 #define MPU3050_DLPF_CFG_42HZ 0x03 124 #define MPU3050_DLPF_CFG_20HZ 0x04 125 #define MPU3050_DLPF_CFG_10HZ 0x05 126 #define MPU3050_DLPF_CFG_5HZ 0x06 127 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 128 #define MPU3050_DLPF_CFG_MASK 0x07 129 #define MPU3050_DLPF_CFG_SHIFT 0 130 131 /* Interrupt config */ 132 #define MPU3050_INT_RAW_RDY_EN BIT(0) 133 #define MPU3050_INT_DMP_DONE_EN BIT(1) 134 #define MPU3050_INT_MPU_RDY_EN BIT(2) 135 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 136 #define MPU3050_INT_LATCH_EN BIT(5) 137 #define MPU3050_INT_OPEN BIT(6) 138 #define MPU3050_INT_ACTL BIT(7) 139 /* Interrupt status */ 140 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 141 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 142 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 143 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 144 /* USR_CTRL */ 145 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 146 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 147 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 148 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 149 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 150 /* PWR_MGM */ 151 #define MPU3050_PWR_MGM_PLL_X 0x01 152 #define MPU3050_PWR_MGM_PLL_Y 0x02 153 #define MPU3050_PWR_MGM_PLL_Z 0x03 154 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 155 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 156 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 157 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 158 #define MPU3050_PWR_MGM_SLEEP BIT(6) 159 #define MPU3050_PWR_MGM_RESET BIT(7) 160 #define MPU3050_PWR_MGM_MASK 0xff 161 162 /* 163 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 164 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 165 * in two's complement. 166 */ 167 static unsigned int mpu3050_fs_precision[] = { 168 IIO_DEGREE_TO_RAD(250), 169 IIO_DEGREE_TO_RAD(500), 170 IIO_DEGREE_TO_RAD(1000), 171 IIO_DEGREE_TO_RAD(2000) 172 }; 173 174 /* 175 * Regulator names 176 */ 177 static const char mpu3050_reg_vdd[] = "vdd"; 178 static const char mpu3050_reg_vlogic[] = "vlogic"; 179 180 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 181 { 182 unsigned int freq; 183 184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 185 freq = 8000; 186 else 187 freq = 1000; 188 freq /= (mpu3050->divisor + 1); 189 190 return freq; 191 } 192 193 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 194 { 195 __be16 raw_val[3]; 196 int ret; 197 int i; 198 199 /* Reset */ 200 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 201 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 202 if (ret) 203 return ret; 204 205 /* Turn on the Z-axis PLL */ 206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 207 MPU3050_PWR_MGM_CLKSEL_MASK, 208 MPU3050_PWR_MGM_PLL_Z); 209 if (ret) 210 return ret; 211 212 /* Write calibration offset registers */ 213 for (i = 0; i < 3; i++) 214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 215 216 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 217 sizeof(raw_val)); 218 if (ret) 219 return ret; 220 221 /* Set low pass filter (sample rate), sync and full scale */ 222 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 223 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 224 mpu3050->fullscale << MPU3050_FS_SHIFT | 225 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 226 if (ret) 227 return ret; 228 229 /* Set up sampling frequency */ 230 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 231 if (ret) 232 return ret; 233 234 /* 235 * Max 50 ms start-up time after setting DLPF_FS_SYNC 236 * according to the data sheet, then wait for the next sample 237 * at this frequency T = 1000/f ms. 238 */ 239 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 240 241 return 0; 242 } 243 244 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 245 { 246 int ret; 247 u8 divisor; 248 enum mpu3050_lpf lpf; 249 250 lpf = mpu3050->lpf; 251 divisor = mpu3050->divisor; 252 253 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 254 mpu3050->divisor = 0; /* Divide by 1 */ 255 ret = mpu3050_start_sampling(mpu3050); 256 257 mpu3050->lpf = lpf; 258 mpu3050->divisor = divisor; 259 260 return ret; 261 } 262 263 static int mpu3050_read_raw(struct iio_dev *indio_dev, 264 struct iio_chan_spec const *chan, 265 int *val, int *val2, 266 long mask) 267 { 268 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 269 int ret; 270 __be16 raw_val; 271 272 switch (mask) { 273 case IIO_CHAN_INFO_OFFSET: 274 switch (chan->type) { 275 case IIO_TEMP: 276 /* 277 * The temperature scaling is (x+23000)/280 Celsius 278 * for the "best fit straight line" temperature range 279 * of -30C..85C. The 23000 includes room temperature 280 * offset of +35C, 280 is the precision scale and x is 281 * the 16-bit signed integer reported by hardware. 282 * 283 * Temperature value itself represents temperature of 284 * the sensor die. 285 */ 286 *val = 23000; 287 return IIO_VAL_INT; 288 default: 289 return -EINVAL; 290 } 291 case IIO_CHAN_INFO_CALIBBIAS: 292 switch (chan->type) { 293 case IIO_ANGL_VEL: 294 *val = mpu3050->calibration[chan->scan_index-1]; 295 return IIO_VAL_INT; 296 default: 297 return -EINVAL; 298 } 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *val = mpu3050_get_freq(mpu3050); 301 return IIO_VAL_INT; 302 case IIO_CHAN_INFO_SCALE: 303 switch (chan->type) { 304 case IIO_TEMP: 305 /* Millidegrees, see about temperature scaling above */ 306 *val = 1000; 307 *val2 = 280; 308 return IIO_VAL_FRACTIONAL; 309 case IIO_ANGL_VEL: 310 /* 311 * Convert to the corresponding full scale in 312 * radians. All 16 bits are used with sign to 313 * span the available scale: to account for the one 314 * missing value if we multiply by 1/S16_MAX, instead 315 * multiply with 2/U16_MAX. 316 */ 317 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 318 *val2 = U16_MAX; 319 return IIO_VAL_FRACTIONAL; 320 default: 321 return -EINVAL; 322 } 323 case IIO_CHAN_INFO_RAW: 324 /* Resume device */ 325 pm_runtime_get_sync(mpu3050->dev); 326 mutex_lock(&mpu3050->lock); 327 328 ret = mpu3050_set_8khz_samplerate(mpu3050); 329 if (ret) 330 goto out_read_raw_unlock; 331 332 switch (chan->type) { 333 case IIO_TEMP: 334 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 335 &raw_val, sizeof(raw_val)); 336 if (ret) { 337 dev_err(mpu3050->dev, 338 "error reading temperature\n"); 339 goto out_read_raw_unlock; 340 } 341 342 *val = (s16)be16_to_cpu(raw_val); 343 ret = IIO_VAL_INT; 344 345 goto out_read_raw_unlock; 346 case IIO_ANGL_VEL: 347 ret = regmap_bulk_read(mpu3050->map, 348 MPU3050_AXIS_REGS(chan->scan_index-1), 349 &raw_val, 350 sizeof(raw_val)); 351 if (ret) { 352 dev_err(mpu3050->dev, 353 "error reading axis data\n"); 354 goto out_read_raw_unlock; 355 } 356 357 *val = be16_to_cpu(raw_val); 358 ret = IIO_VAL_INT; 359 360 goto out_read_raw_unlock; 361 default: 362 ret = -EINVAL; 363 goto out_read_raw_unlock; 364 } 365 default: 366 break; 367 } 368 369 return -EINVAL; 370 371 out_read_raw_unlock: 372 mutex_unlock(&mpu3050->lock); 373 pm_runtime_mark_last_busy(mpu3050->dev); 374 pm_runtime_put_autosuspend(mpu3050->dev); 375 376 return ret; 377 } 378 379 static int mpu3050_write_raw(struct iio_dev *indio_dev, 380 const struct iio_chan_spec *chan, 381 int val, int val2, long mask) 382 { 383 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 384 /* 385 * Couldn't figure out a way to precalculate these at compile time. 386 */ 387 unsigned int fs250 = 388 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 389 U16_MAX); 390 unsigned int fs500 = 391 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 392 U16_MAX); 393 unsigned int fs1000 = 394 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 395 U16_MAX); 396 unsigned int fs2000 = 397 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 398 U16_MAX); 399 400 switch (mask) { 401 case IIO_CHAN_INFO_CALIBBIAS: 402 if (chan->type != IIO_ANGL_VEL) 403 return -EINVAL; 404 mpu3050->calibration[chan->scan_index-1] = val; 405 return 0; 406 case IIO_CHAN_INFO_SAMP_FREQ: 407 /* 408 * The max samplerate is 8000 Hz, the minimum 409 * 1000 / 256 ~= 4 Hz 410 */ 411 if (val < 4 || val > 8000) 412 return -EINVAL; 413 414 /* 415 * Above 1000 Hz we must turn off the digital low pass filter 416 * so we get a base frequency of 8kHz to the divider 417 */ 418 if (val > 1000) { 419 mpu3050->lpf = LPF_256_HZ_NOLPF; 420 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 421 return 0; 422 } 423 424 mpu3050->lpf = LPF_188_HZ; 425 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 426 return 0; 427 case IIO_CHAN_INFO_SCALE: 428 if (chan->type != IIO_ANGL_VEL) 429 return -EINVAL; 430 /* 431 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 432 * which means we need to round to the closest radians 433 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 434 * rad/s. The scale is then for the 16 bits used to cover 435 * it 2/(2^16) of that. 436 */ 437 438 /* Just too large, set the max range */ 439 if (val != 0) { 440 mpu3050->fullscale = FS_2000_DPS; 441 return 0; 442 } 443 444 /* 445 * Now we're dealing with fractions below zero in millirad/s 446 * do some integer interpolation and match with the closest 447 * fullscale in the table. 448 */ 449 if (val2 <= fs250 || 450 val2 < ((fs500 + fs250) / 2)) 451 mpu3050->fullscale = FS_250_DPS; 452 else if (val2 <= fs500 || 453 val2 < ((fs1000 + fs500) / 2)) 454 mpu3050->fullscale = FS_500_DPS; 455 else if (val2 <= fs1000 || 456 val2 < ((fs2000 + fs1000) / 2)) 457 mpu3050->fullscale = FS_1000_DPS; 458 else 459 /* Catch-all */ 460 mpu3050->fullscale = FS_2000_DPS; 461 return 0; 462 default: 463 break; 464 } 465 466 return -EINVAL; 467 } 468 469 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 470 { 471 const struct iio_poll_func *pf = p; 472 struct iio_dev *indio_dev = pf->indio_dev; 473 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 474 int ret; 475 struct { 476 __be16 chans[4]; 477 s64 timestamp __aligned(8); 478 } scan; 479 s64 timestamp; 480 unsigned int datums_from_fifo = 0; 481 482 /* 483 * If we're using the hardware trigger, get the precise timestamp from 484 * the top half of the threaded IRQ handler. Otherwise get the 485 * timestamp here so it will be close in time to the actual values 486 * read from the registers. 487 */ 488 if (iio_trigger_using_own(indio_dev)) 489 timestamp = mpu3050->hw_timestamp; 490 else 491 timestamp = iio_get_time_ns(indio_dev); 492 493 mutex_lock(&mpu3050->lock); 494 495 /* Using the hardware IRQ trigger? Check the buffer then. */ 496 if (mpu3050->hw_irq_trigger) { 497 __be16 raw_fifocnt; 498 u16 fifocnt; 499 /* X, Y, Z + temperature */ 500 unsigned int bytes_per_datum = 8; 501 bool fifo_overflow = false; 502 503 ret = regmap_bulk_read(mpu3050->map, 504 MPU3050_FIFO_COUNT_H, 505 &raw_fifocnt, 506 sizeof(raw_fifocnt)); 507 if (ret) 508 goto out_trigger_unlock; 509 fifocnt = be16_to_cpu(raw_fifocnt); 510 511 if (fifocnt == 512) { 512 dev_info(mpu3050->dev, 513 "FIFO overflow! Emptying and resetting FIFO\n"); 514 fifo_overflow = true; 515 /* Reset and enable the FIFO */ 516 ret = regmap_update_bits(mpu3050->map, 517 MPU3050_USR_CTRL, 518 MPU3050_USR_CTRL_FIFO_EN | 519 MPU3050_USR_CTRL_FIFO_RST, 520 MPU3050_USR_CTRL_FIFO_EN | 521 MPU3050_USR_CTRL_FIFO_RST); 522 if (ret) { 523 dev_info(mpu3050->dev, "error resetting FIFO\n"); 524 goto out_trigger_unlock; 525 } 526 mpu3050->pending_fifo_footer = false; 527 } 528 529 if (fifocnt) 530 dev_dbg(mpu3050->dev, 531 "%d bytes in the FIFO\n", 532 fifocnt); 533 534 while (!fifo_overflow && fifocnt > bytes_per_datum) { 535 unsigned int toread; 536 unsigned int offset; 537 __be16 fifo_values[5]; 538 539 /* 540 * If there is a FIFO footer in the pipe, first clear 541 * that out. This follows the complex algorithm in the 542 * datasheet that states that you may never leave the 543 * FIFO empty after the first reading: you have to 544 * always leave two footer bytes in it. The footer is 545 * in practice just two zero bytes. 546 */ 547 if (mpu3050->pending_fifo_footer) { 548 toread = bytes_per_datum + 2; 549 offset = 0; 550 } else { 551 toread = bytes_per_datum; 552 offset = 1; 553 /* Put in some dummy value */ 554 fifo_values[0] = cpu_to_be16(0xAAAA); 555 } 556 557 ret = regmap_bulk_read(mpu3050->map, 558 MPU3050_FIFO_R, 559 &fifo_values[offset], 560 toread); 561 if (ret) 562 goto out_trigger_unlock; 563 564 dev_dbg(mpu3050->dev, 565 "%04x %04x %04x %04x %04x\n", 566 fifo_values[0], 567 fifo_values[1], 568 fifo_values[2], 569 fifo_values[3], 570 fifo_values[4]); 571 572 /* Index past the footer (fifo_values[0]) and push */ 573 iio_push_to_buffers_with_ts_unaligned(indio_dev, 574 &fifo_values[1], 575 sizeof(__be16) * 4, 576 timestamp); 577 578 fifocnt -= toread; 579 datums_from_fifo++; 580 mpu3050->pending_fifo_footer = true; 581 582 /* 583 * If we're emptying the FIFO, just make sure to 584 * check if something new appeared. 585 */ 586 if (fifocnt < bytes_per_datum) { 587 ret = regmap_bulk_read(mpu3050->map, 588 MPU3050_FIFO_COUNT_H, 589 &raw_fifocnt, 590 sizeof(raw_fifocnt)); 591 if (ret) 592 goto out_trigger_unlock; 593 fifocnt = be16_to_cpu(raw_fifocnt); 594 } 595 596 if (fifocnt < bytes_per_datum) 597 dev_dbg(mpu3050->dev, 598 "%d bytes left in the FIFO\n", 599 fifocnt); 600 601 /* 602 * At this point, the timestamp that triggered the 603 * hardware interrupt is no longer valid for what 604 * we are reading (the interrupt likely fired for 605 * the value on the top of the FIFO), so set the 606 * timestamp to zero and let userspace deal with it. 607 */ 608 timestamp = 0; 609 } 610 } 611 612 /* 613 * If we picked some datums from the FIFO that's enough, else 614 * fall through and just read from the current value registers. 615 * This happens in two cases: 616 * 617 * - We are using some other trigger (external, like an HRTimer) 618 * than the sensor's own sample generator. In this case the 619 * sensor is just set to the max sampling frequency and we give 620 * the trigger a copy of the latest value every time we get here. 621 * 622 * - The hardware trigger is active but unused and we actually use 623 * another trigger which calls here with a frequency higher 624 * than what the device provides data. We will then just read 625 * duplicate values directly from the hardware registers. 626 */ 627 if (datums_from_fifo) { 628 dev_dbg(mpu3050->dev, 629 "read %d datums from the FIFO\n", 630 datums_from_fifo); 631 goto out_trigger_unlock; 632 } 633 634 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans, 635 sizeof(scan.chans)); 636 if (ret) { 637 dev_err(mpu3050->dev, 638 "error reading axis data\n"); 639 goto out_trigger_unlock; 640 } 641 642 iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp); 643 644 out_trigger_unlock: 645 mutex_unlock(&mpu3050->lock); 646 iio_trigger_notify_done(indio_dev->trig); 647 648 return IRQ_HANDLED; 649 } 650 651 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 652 { 653 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 654 655 pm_runtime_get_sync(mpu3050->dev); 656 657 /* Unless we have OUR trigger active, run at full speed */ 658 if (!mpu3050->hw_irq_trigger) 659 return mpu3050_set_8khz_samplerate(mpu3050); 660 661 return 0; 662 } 663 664 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 665 { 666 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 667 668 pm_runtime_mark_last_busy(mpu3050->dev); 669 pm_runtime_put_autosuspend(mpu3050->dev); 670 671 return 0; 672 } 673 674 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 675 .preenable = mpu3050_buffer_preenable, 676 .postdisable = mpu3050_buffer_postdisable, 677 }; 678 679 static const struct iio_mount_matrix * 680 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 681 const struct iio_chan_spec *chan) 682 { 683 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 684 685 return &mpu3050->orientation; 686 } 687 688 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 689 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 690 { }, 691 }; 692 693 #define MPU3050_AXIS_CHANNEL(axis, index) \ 694 { \ 695 .type = IIO_ANGL_VEL, \ 696 .modified = 1, \ 697 .channel2 = IIO_MOD_##axis, \ 698 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 699 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 700 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 701 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 702 .ext_info = mpu3050_ext_info, \ 703 .scan_index = index, \ 704 .scan_type = { \ 705 .sign = 's', \ 706 .realbits = 16, \ 707 .storagebits = 16, \ 708 .endianness = IIO_BE, \ 709 }, \ 710 } 711 712 static const struct iio_chan_spec mpu3050_channels[] = { 713 { 714 .type = IIO_TEMP, 715 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 716 BIT(IIO_CHAN_INFO_SCALE) | 717 BIT(IIO_CHAN_INFO_OFFSET), 718 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 719 .scan_index = 0, 720 .scan_type = { 721 .sign = 's', 722 .realbits = 16, 723 .storagebits = 16, 724 .endianness = IIO_BE, 725 }, 726 }, 727 MPU3050_AXIS_CHANNEL(X, 1), 728 MPU3050_AXIS_CHANNEL(Y, 2), 729 MPU3050_AXIS_CHANNEL(Z, 3), 730 IIO_CHAN_SOFT_TIMESTAMP(4), 731 }; 732 733 /* Four channels apart from timestamp, scan mask = 0x0f */ 734 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 735 736 /* 737 * These are just the hardcoded factors resulting from the more elaborate 738 * calculations done with fractions in the scale raw get/set functions. 739 */ 740 static IIO_CONST_ATTR(anglevel_scale_available, 741 "0.000122070 " 742 "0.000274658 " 743 "0.000518798 " 744 "0.001068115"); 745 746 static struct attribute *mpu3050_attributes[] = { 747 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 748 NULL, 749 }; 750 751 static const struct attribute_group mpu3050_attribute_group = { 752 .attrs = mpu3050_attributes, 753 }; 754 755 static const struct iio_info mpu3050_info = { 756 .read_raw = mpu3050_read_raw, 757 .write_raw = mpu3050_write_raw, 758 .attrs = &mpu3050_attribute_group, 759 }; 760 761 /** 762 * mpu3050_read_mem() - read MPU-3050 internal memory 763 * @mpu3050: device to read from 764 * @bank: target bank 765 * @addr: target address 766 * @len: number of bytes 767 * @buf: the buffer to store the read bytes in 768 */ 769 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 770 u8 bank, 771 u8 addr, 772 u8 len, 773 u8 *buf) 774 { 775 int ret; 776 777 ret = regmap_write(mpu3050->map, 778 MPU3050_BANK_SEL, 779 bank); 780 if (ret) 781 return ret; 782 783 ret = regmap_write(mpu3050->map, 784 MPU3050_MEM_START_ADDR, 785 addr); 786 if (ret) 787 return ret; 788 789 return regmap_bulk_read(mpu3050->map, 790 MPU3050_MEM_R_W, 791 buf, 792 len); 793 } 794 795 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 796 { 797 int ret; 798 __le64 otp_le; 799 u64 otp; 800 801 /* Reset */ 802 ret = regmap_update_bits(mpu3050->map, 803 MPU3050_PWR_MGM, 804 MPU3050_PWR_MGM_RESET, 805 MPU3050_PWR_MGM_RESET); 806 if (ret) 807 return ret; 808 809 /* Turn on the PLL */ 810 ret = regmap_update_bits(mpu3050->map, 811 MPU3050_PWR_MGM, 812 MPU3050_PWR_MGM_CLKSEL_MASK, 813 MPU3050_PWR_MGM_PLL_Z); 814 if (ret) 815 return ret; 816 817 /* Disable IRQs */ 818 ret = regmap_write(mpu3050->map, 819 MPU3050_INT_CFG, 820 0); 821 if (ret) 822 return ret; 823 824 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 825 ret = mpu3050_read_mem(mpu3050, 826 (MPU3050_MEM_PRFTCH | 827 MPU3050_MEM_USER_BANK | 828 MPU3050_MEM_OTP_BANK_0), 829 0, 830 sizeof(otp_le), 831 (u8 *)&otp_le); 832 if (ret) 833 return ret; 834 835 /* This is device-unique data so it goes into the entropy pool */ 836 add_device_randomness(&otp_le, sizeof(otp_le)); 837 838 otp = le64_to_cpu(otp_le); 839 840 dev_info(mpu3050->dev, 841 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 842 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 843 /* Die ID, bits 0-12 */ 844 FIELD_GET(GENMASK_ULL(12, 0), otp), 845 /* Wafer ID, bits 13-17 */ 846 FIELD_GET(GENMASK_ULL(17, 13), otp), 847 /* A lot ID, bits 18-33 */ 848 FIELD_GET(GENMASK_ULL(33, 18), otp), 849 /* W lot ID, bits 34-45 */ 850 FIELD_GET(GENMASK_ULL(45, 34), otp), 851 /* WP ID, bits 47-49 */ 852 FIELD_GET(GENMASK_ULL(49, 47), otp), 853 /* rev ID, bits 50-55 */ 854 FIELD_GET(GENMASK_ULL(55, 50), otp)); 855 856 return 0; 857 } 858 859 static int mpu3050_power_up(struct mpu3050 *mpu3050) 860 { 861 int ret; 862 863 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 864 if (ret) { 865 dev_err(mpu3050->dev, "cannot enable regulators\n"); 866 return ret; 867 } 868 /* 869 * 20-100 ms start-up time for register read/write according to 870 * the datasheet, be on the safe side and wait 200 ms. 871 */ 872 msleep(200); 873 874 /* Take device out of sleep mode */ 875 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 876 MPU3050_PWR_MGM_SLEEP, 0); 877 if (ret) { 878 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 879 dev_err(mpu3050->dev, "error setting power mode\n"); 880 return ret; 881 } 882 usleep_range(10000, 20000); 883 884 return 0; 885 } 886 887 static int mpu3050_power_down(struct mpu3050 *mpu3050) 888 { 889 int ret; 890 891 /* 892 * Put MPU-3050 into sleep mode before cutting regulators. 893 * This is important, because we may not be the sole user 894 * of the regulator so the power may stay on after this, and 895 * then we would be wasting power unless we go to sleep mode 896 * first. 897 */ 898 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 899 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 900 if (ret) 901 dev_err(mpu3050->dev, "error putting to sleep\n"); 902 903 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 904 if (ret) 905 dev_err(mpu3050->dev, "error disabling regulators\n"); 906 907 return 0; 908 } 909 910 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 911 { 912 struct iio_trigger *trig = p; 913 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 914 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 915 916 if (!mpu3050->hw_irq_trigger) 917 return IRQ_NONE; 918 919 /* Get the time stamp as close in time as possible */ 920 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 921 922 return IRQ_WAKE_THREAD; 923 } 924 925 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 926 { 927 struct iio_trigger *trig = p; 928 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 929 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 930 unsigned int val; 931 int ret; 932 933 /* ACK IRQ and check if it was from us */ 934 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 935 if (ret) { 936 dev_err(mpu3050->dev, "error reading IRQ status\n"); 937 return IRQ_HANDLED; 938 } 939 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 940 return IRQ_NONE; 941 942 iio_trigger_poll_nested(p); 943 944 return IRQ_HANDLED; 945 } 946 947 /** 948 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 949 * @trig: trigger instance 950 * @enable: true if trigger should be enabled, false to disable 951 */ 952 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 953 bool enable) 954 { 955 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 956 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 957 unsigned int val; 958 int ret; 959 960 /* Disabling trigger: disable interrupt and return */ 961 if (!enable) { 962 /* Disable all interrupts */ 963 ret = regmap_write(mpu3050->map, 964 MPU3050_INT_CFG, 965 0); 966 if (ret) 967 dev_err(mpu3050->dev, "error disabling IRQ\n"); 968 969 /* Clear IRQ flag */ 970 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 971 if (ret) 972 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 973 974 /* Disable all things in the FIFO and reset it */ 975 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 976 if (ret) 977 dev_err(mpu3050->dev, "error disabling FIFO\n"); 978 979 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 980 MPU3050_USR_CTRL_FIFO_RST); 981 if (ret) 982 dev_err(mpu3050->dev, "error resetting FIFO\n"); 983 984 pm_runtime_mark_last_busy(mpu3050->dev); 985 pm_runtime_put_autosuspend(mpu3050->dev); 986 mpu3050->hw_irq_trigger = false; 987 988 return 0; 989 } else { 990 /* Else we're enabling the trigger from this point */ 991 pm_runtime_get_sync(mpu3050->dev); 992 mpu3050->hw_irq_trigger = true; 993 994 /* Disable all things in the FIFO */ 995 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 996 if (ret) 997 return ret; 998 999 /* Reset and enable the FIFO */ 1000 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 1001 MPU3050_USR_CTRL_FIFO_EN | 1002 MPU3050_USR_CTRL_FIFO_RST, 1003 MPU3050_USR_CTRL_FIFO_EN | 1004 MPU3050_USR_CTRL_FIFO_RST); 1005 if (ret) 1006 return ret; 1007 1008 mpu3050->pending_fifo_footer = false; 1009 1010 /* Turn on the FIFO for temp+X+Y+Z */ 1011 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1012 MPU3050_FIFO_EN_TEMP_OUT | 1013 MPU3050_FIFO_EN_GYRO_XOUT | 1014 MPU3050_FIFO_EN_GYRO_YOUT | 1015 MPU3050_FIFO_EN_GYRO_ZOUT | 1016 MPU3050_FIFO_EN_FOOTER); 1017 if (ret) 1018 return ret; 1019 1020 /* Configure the sample engine */ 1021 ret = mpu3050_start_sampling(mpu3050); 1022 if (ret) 1023 return ret; 1024 1025 /* Clear IRQ flag */ 1026 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1027 if (ret) 1028 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1029 1030 /* Give us interrupts whenever there is new data ready */ 1031 val = MPU3050_INT_RAW_RDY_EN; 1032 1033 if (mpu3050->irq_actl) 1034 val |= MPU3050_INT_ACTL; 1035 if (mpu3050->irq_latch) 1036 val |= MPU3050_INT_LATCH_EN; 1037 if (mpu3050->irq_opendrain) 1038 val |= MPU3050_INT_OPEN; 1039 1040 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1049 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1050 }; 1051 1052 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1053 { 1054 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1055 struct device *dev = mpu3050->dev; 1056 unsigned long irq_trig; 1057 int ret; 1058 1059 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1060 "%s-dev%d", 1061 indio_dev->name, 1062 iio_device_id(indio_dev)); 1063 if (!mpu3050->trig) 1064 return -ENOMEM; 1065 1066 /* Check if IRQ is open drain */ 1067 mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain"); 1068 1069 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1070 /* 1071 * Configure the interrupt generator hardware to supply whatever 1072 * the interrupt is configured for, edges low/high level low/high, 1073 * we can provide it all. 1074 */ 1075 switch (irq_trig) { 1076 case IRQF_TRIGGER_RISING: 1077 dev_info(&indio_dev->dev, 1078 "pulse interrupts on the rising edge\n"); 1079 break; 1080 case IRQF_TRIGGER_FALLING: 1081 mpu3050->irq_actl = true; 1082 dev_info(&indio_dev->dev, 1083 "pulse interrupts on the falling edge\n"); 1084 break; 1085 case IRQF_TRIGGER_HIGH: 1086 mpu3050->irq_latch = true; 1087 dev_info(&indio_dev->dev, 1088 "interrupts active high level\n"); 1089 /* 1090 * With level IRQs, we mask the IRQ until it is processed, 1091 * but with edge IRQs (pulses) we can queue several interrupts 1092 * in the top half. 1093 */ 1094 irq_trig |= IRQF_ONESHOT; 1095 break; 1096 case IRQF_TRIGGER_LOW: 1097 mpu3050->irq_latch = true; 1098 mpu3050->irq_actl = true; 1099 irq_trig |= IRQF_ONESHOT; 1100 dev_info(&indio_dev->dev, 1101 "interrupts active low level\n"); 1102 break; 1103 default: 1104 /* This is the most preferred mode, if possible */ 1105 dev_err(&indio_dev->dev, 1106 "unsupported IRQ trigger specified (%lx), enforce " 1107 "rising edge\n", irq_trig); 1108 irq_trig = IRQF_TRIGGER_RISING; 1109 break; 1110 } 1111 1112 /* An open drain line can be shared with several devices */ 1113 if (mpu3050->irq_opendrain) 1114 irq_trig |= IRQF_SHARED; 1115 1116 ret = request_threaded_irq(irq, 1117 mpu3050_irq_handler, 1118 mpu3050_irq_thread, 1119 irq_trig, 1120 mpu3050->trig->name, 1121 mpu3050->trig); 1122 if (ret) { 1123 dev_err(dev, "can't get IRQ %d, error %d\n", irq, ret); 1124 return ret; 1125 } 1126 1127 mpu3050->irq = irq; 1128 mpu3050->trig->dev.parent = dev; 1129 mpu3050->trig->ops = &mpu3050_trigger_ops; 1130 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1131 1132 ret = iio_trigger_register(mpu3050->trig); 1133 if (ret) 1134 return ret; 1135 1136 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1137 1138 return 0; 1139 } 1140 1141 int mpu3050_common_probe(struct device *dev, 1142 struct regmap *map, 1143 int irq, 1144 const char *name) 1145 { 1146 struct iio_dev *indio_dev; 1147 struct mpu3050 *mpu3050; 1148 unsigned int val; 1149 int ret; 1150 1151 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1152 if (!indio_dev) 1153 return -ENOMEM; 1154 mpu3050 = iio_priv(indio_dev); 1155 1156 mpu3050->dev = dev; 1157 mpu3050->map = map; 1158 mutex_init(&mpu3050->lock); 1159 /* Default fullscale: 2000 degrees per second */ 1160 mpu3050->fullscale = FS_2000_DPS; 1161 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1162 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1163 mpu3050->divisor = 99; 1164 1165 /* Read the mounting matrix, if present */ 1166 ret = iio_read_mount_matrix(dev, &mpu3050->orientation); 1167 if (ret) 1168 return ret; 1169 1170 /* Fetch and turn on regulators */ 1171 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1172 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1173 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1174 mpu3050->regs); 1175 if (ret) { 1176 dev_err(dev, "Cannot get regulators\n"); 1177 return ret; 1178 } 1179 1180 ret = mpu3050_power_up(mpu3050); 1181 if (ret) 1182 return ret; 1183 1184 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1185 if (ret) { 1186 dev_err(dev, "could not read device ID\n"); 1187 ret = -ENODEV; 1188 1189 goto err_power_down; 1190 } 1191 1192 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1193 dev_err(dev, "unsupported chip id %02x\n", 1194 (u8)(val & MPU3050_CHIP_ID_MASK)); 1195 ret = -ENODEV; 1196 goto err_power_down; 1197 } 1198 1199 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1200 if (ret) { 1201 dev_err(dev, "could not read device ID\n"); 1202 ret = -ENODEV; 1203 1204 goto err_power_down; 1205 } 1206 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1207 ((val >> 4) & 0xf), (val & 0xf)); 1208 1209 ret = mpu3050_hw_init(mpu3050); 1210 if (ret) 1211 goto err_power_down; 1212 1213 indio_dev->channels = mpu3050_channels; 1214 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1215 indio_dev->info = &mpu3050_info; 1216 indio_dev->available_scan_masks = mpu3050_scan_masks; 1217 indio_dev->modes = INDIO_DIRECT_MODE; 1218 indio_dev->name = name; 1219 1220 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1221 mpu3050_trigger_handler, 1222 &mpu3050_buffer_setup_ops); 1223 if (ret) { 1224 dev_err(dev, "triggered buffer setup failed\n"); 1225 goto err_power_down; 1226 } 1227 1228 ret = iio_device_register(indio_dev); 1229 if (ret) { 1230 dev_err(dev, "device register failed\n"); 1231 goto err_cleanup_buffer; 1232 } 1233 1234 dev_set_drvdata(dev, indio_dev); 1235 1236 /* Check if we have an assigned IRQ to use as trigger */ 1237 if (irq) { 1238 ret = mpu3050_trigger_probe(indio_dev, irq); 1239 if (ret) 1240 dev_err(dev, "failed to register trigger\n"); 1241 } 1242 1243 /* Enable runtime PM */ 1244 pm_runtime_get_noresume(dev); 1245 pm_runtime_set_active(dev); 1246 pm_runtime_enable(dev); 1247 /* 1248 * Set autosuspend to two orders of magnitude larger than the 1249 * start-up time. 100ms start-up time means 10000ms autosuspend, 1250 * i.e. 10 seconds. 1251 */ 1252 pm_runtime_set_autosuspend_delay(dev, 10000); 1253 pm_runtime_use_autosuspend(dev); 1254 pm_runtime_put(dev); 1255 1256 return 0; 1257 1258 err_cleanup_buffer: 1259 iio_triggered_buffer_cleanup(indio_dev); 1260 err_power_down: 1261 mpu3050_power_down(mpu3050); 1262 1263 return ret; 1264 } 1265 1266 void mpu3050_common_remove(struct device *dev) 1267 { 1268 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1269 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1270 1271 pm_runtime_get_sync(dev); 1272 pm_runtime_put_noidle(dev); 1273 pm_runtime_disable(dev); 1274 iio_triggered_buffer_cleanup(indio_dev); 1275 if (mpu3050->irq) 1276 free_irq(mpu3050->irq, mpu3050); 1277 iio_device_unregister(indio_dev); 1278 mpu3050_power_down(mpu3050); 1279 } 1280 1281 static int mpu3050_runtime_suspend(struct device *dev) 1282 { 1283 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1284 } 1285 1286 static int mpu3050_runtime_resume(struct device *dev) 1287 { 1288 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1289 } 1290 1291 DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend, 1292 mpu3050_runtime_resume, NULL); 1293 MODULE_AUTHOR("Linus Walleij"); 1294 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1295 MODULE_LICENSE("GPL"); 1296