1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/slab.h> 31 32 #include "mpu3050.h" 33 34 #define MPU3050_CHIP_ID 0x68 35 #define MPU3050_CHIP_ID_MASK 0x7E 36 37 /* 38 * Register map: anything suffixed *_H is a big-endian high byte and always 39 * followed by the corresponding low byte (*_L) even though these are not 40 * explicitly included in the register definitions. 41 */ 42 #define MPU3050_CHIP_ID_REG 0x00 43 #define MPU3050_PRODUCT_ID_REG 0x01 44 #define MPU3050_XG_OFFS_TC 0x05 45 #define MPU3050_YG_OFFS_TC 0x08 46 #define MPU3050_ZG_OFFS_TC 0x0B 47 #define MPU3050_X_OFFS_USR_H 0x0C 48 #define MPU3050_Y_OFFS_USR_H 0x0E 49 #define MPU3050_Z_OFFS_USR_H 0x10 50 #define MPU3050_FIFO_EN 0x12 51 #define MPU3050_AUX_VDDIO 0x13 52 #define MPU3050_SLV_ADDR 0x14 53 #define MPU3050_SMPLRT_DIV 0x15 54 #define MPU3050_DLPF_FS_SYNC 0x16 55 #define MPU3050_INT_CFG 0x17 56 #define MPU3050_AUX_ADDR 0x18 57 #define MPU3050_INT_STATUS 0x1A 58 #define MPU3050_TEMP_H 0x1B 59 #define MPU3050_XOUT_H 0x1D 60 #define MPU3050_YOUT_H 0x1F 61 #define MPU3050_ZOUT_H 0x21 62 #define MPU3050_DMP_CFG1 0x35 63 #define MPU3050_DMP_CFG2 0x36 64 #define MPU3050_BANK_SEL 0x37 65 #define MPU3050_MEM_START_ADDR 0x38 66 #define MPU3050_MEM_R_W 0x39 67 #define MPU3050_FIFO_COUNT_H 0x3A 68 #define MPU3050_FIFO_R 0x3C 69 #define MPU3050_USR_CTRL 0x3D 70 #define MPU3050_PWR_MGM 0x3E 71 72 /* MPU memory bank read options */ 73 #define MPU3050_MEM_PRFTCH BIT(5) 74 #define MPU3050_MEM_USER_BANK BIT(4) 75 /* Bits 8-11 select memory bank */ 76 #define MPU3050_MEM_RAM_BANK_0 0 77 #define MPU3050_MEM_RAM_BANK_1 1 78 #define MPU3050_MEM_RAM_BANK_2 2 79 #define MPU3050_MEM_RAM_BANK_3 3 80 #define MPU3050_MEM_OTP_BANK_0 4 81 82 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 83 84 /* Register bits */ 85 86 /* FIFO Enable */ 87 #define MPU3050_FIFO_EN_FOOTER BIT(0) 88 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 89 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 90 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 91 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 92 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 93 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 94 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 95 96 /* 97 * Digital Low Pass filter (DLPF) 98 * Full Scale (FS) 99 * and Synchronization 100 */ 101 #define MPU3050_EXT_SYNC_NONE 0x00 102 #define MPU3050_EXT_SYNC_TEMP 0x20 103 #define MPU3050_EXT_SYNC_GYROX 0x40 104 #define MPU3050_EXT_SYNC_GYROY 0x60 105 #define MPU3050_EXT_SYNC_GYROZ 0x80 106 #define MPU3050_EXT_SYNC_ACCELX 0xA0 107 #define MPU3050_EXT_SYNC_ACCELY 0xC0 108 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 109 #define MPU3050_EXT_SYNC_MASK 0xE0 110 #define MPU3050_EXT_SYNC_SHIFT 5 111 112 #define MPU3050_FS_250DPS 0x00 113 #define MPU3050_FS_500DPS 0x08 114 #define MPU3050_FS_1000DPS 0x10 115 #define MPU3050_FS_2000DPS 0x18 116 #define MPU3050_FS_MASK 0x18 117 #define MPU3050_FS_SHIFT 3 118 119 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 120 #define MPU3050_DLPF_CFG_188HZ 0x01 121 #define MPU3050_DLPF_CFG_98HZ 0x02 122 #define MPU3050_DLPF_CFG_42HZ 0x03 123 #define MPU3050_DLPF_CFG_20HZ 0x04 124 #define MPU3050_DLPF_CFG_10HZ 0x05 125 #define MPU3050_DLPF_CFG_5HZ 0x06 126 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 127 #define MPU3050_DLPF_CFG_MASK 0x07 128 #define MPU3050_DLPF_CFG_SHIFT 0 129 130 /* Interrupt config */ 131 #define MPU3050_INT_RAW_RDY_EN BIT(0) 132 #define MPU3050_INT_DMP_DONE_EN BIT(1) 133 #define MPU3050_INT_MPU_RDY_EN BIT(2) 134 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 135 #define MPU3050_INT_LATCH_EN BIT(5) 136 #define MPU3050_INT_OPEN BIT(6) 137 #define MPU3050_INT_ACTL BIT(7) 138 /* Interrupt status */ 139 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 140 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 141 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 142 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 143 /* USR_CTRL */ 144 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 145 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 146 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 147 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 148 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 149 /* PWR_MGM */ 150 #define MPU3050_PWR_MGM_PLL_X 0x01 151 #define MPU3050_PWR_MGM_PLL_Y 0x02 152 #define MPU3050_PWR_MGM_PLL_Z 0x03 153 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 154 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 155 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 156 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 157 #define MPU3050_PWR_MGM_SLEEP BIT(6) 158 #define MPU3050_PWR_MGM_RESET BIT(7) 159 #define MPU3050_PWR_MGM_MASK 0xff 160 161 /* 162 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 163 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 164 * in two's complement. 165 */ 166 static unsigned int mpu3050_fs_precision[] = { 167 IIO_DEGREE_TO_RAD(250), 168 IIO_DEGREE_TO_RAD(500), 169 IIO_DEGREE_TO_RAD(1000), 170 IIO_DEGREE_TO_RAD(2000) 171 }; 172 173 /* 174 * Regulator names 175 */ 176 static const char mpu3050_reg_vdd[] = "vdd"; 177 static const char mpu3050_reg_vlogic[] = "vlogic"; 178 179 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 180 { 181 unsigned int freq; 182 183 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 184 freq = 8000; 185 else 186 freq = 1000; 187 freq /= (mpu3050->divisor + 1); 188 189 return freq; 190 } 191 192 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 193 { 194 __be16 raw_val[3]; 195 int ret; 196 int i; 197 198 /* Reset */ 199 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 200 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 201 if (ret) 202 return ret; 203 204 /* Turn on the Z-axis PLL */ 205 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 206 MPU3050_PWR_MGM_CLKSEL_MASK, 207 MPU3050_PWR_MGM_PLL_Z); 208 if (ret) 209 return ret; 210 211 /* Write calibration offset registers */ 212 for (i = 0; i < 3; i++) 213 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 214 215 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 216 sizeof(raw_val)); 217 if (ret) 218 return ret; 219 220 /* Set low pass filter (sample rate), sync and full scale */ 221 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 222 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 223 mpu3050->fullscale << MPU3050_FS_SHIFT | 224 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 225 if (ret) 226 return ret; 227 228 /* Set up sampling frequency */ 229 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 230 if (ret) 231 return ret; 232 233 /* 234 * Max 50 ms start-up time after setting DLPF_FS_SYNC 235 * according to the data sheet, then wait for the next sample 236 * at this frequency T = 1000/f ms. 237 */ 238 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 239 240 return 0; 241 } 242 243 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 244 { 245 int ret; 246 u8 divisor; 247 enum mpu3050_lpf lpf; 248 249 lpf = mpu3050->lpf; 250 divisor = mpu3050->divisor; 251 252 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 253 mpu3050->divisor = 0; /* Divide by 1 */ 254 ret = mpu3050_start_sampling(mpu3050); 255 256 mpu3050->lpf = lpf; 257 mpu3050->divisor = divisor; 258 259 return ret; 260 } 261 262 static int mpu3050_read_raw(struct iio_dev *indio_dev, 263 struct iio_chan_spec const *chan, 264 int *val, int *val2, 265 long mask) 266 { 267 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 268 int ret; 269 __be16 raw_val; 270 271 switch (mask) { 272 case IIO_CHAN_INFO_OFFSET: 273 switch (chan->type) { 274 case IIO_TEMP: 275 /* 276 * The temperature scaling is (x+23000)/280 Celsius 277 * for the "best fit straight line" temperature range 278 * of -30C..85C. The 23000 includes room temperature 279 * offset of +35C, 280 is the precision scale and x is 280 * the 16-bit signed integer reported by hardware. 281 * 282 * Temperature value itself represents temperature of 283 * the sensor die. 284 */ 285 *val = 23000; 286 return IIO_VAL_INT; 287 default: 288 return -EINVAL; 289 } 290 case IIO_CHAN_INFO_CALIBBIAS: 291 switch (chan->type) { 292 case IIO_ANGL_VEL: 293 *val = mpu3050->calibration[chan->scan_index-1]; 294 return IIO_VAL_INT; 295 default: 296 return -EINVAL; 297 } 298 case IIO_CHAN_INFO_SAMP_FREQ: 299 *val = mpu3050_get_freq(mpu3050); 300 return IIO_VAL_INT; 301 case IIO_CHAN_INFO_SCALE: 302 switch (chan->type) { 303 case IIO_TEMP: 304 /* Millidegrees, see about temperature scaling above */ 305 *val = 1000; 306 *val2 = 280; 307 return IIO_VAL_FRACTIONAL; 308 case IIO_ANGL_VEL: 309 /* 310 * Convert to the corresponding full scale in 311 * radians. All 16 bits are used with sign to 312 * span the available scale: to account for the one 313 * missing value if we multiply by 1/S16_MAX, instead 314 * multiply with 2/U16_MAX. 315 */ 316 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 317 *val2 = U16_MAX; 318 return IIO_VAL_FRACTIONAL; 319 default: 320 return -EINVAL; 321 } 322 case IIO_CHAN_INFO_RAW: 323 /* Resume device */ 324 pm_runtime_get_sync(mpu3050->dev); 325 mutex_lock(&mpu3050->lock); 326 327 ret = mpu3050_set_8khz_samplerate(mpu3050); 328 if (ret) 329 goto out_read_raw_unlock; 330 331 switch (chan->type) { 332 case IIO_TEMP: 333 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 334 &raw_val, sizeof(raw_val)); 335 if (ret) { 336 dev_err(mpu3050->dev, 337 "error reading temperature\n"); 338 goto out_read_raw_unlock; 339 } 340 341 *val = (s16)be16_to_cpu(raw_val); 342 ret = IIO_VAL_INT; 343 344 goto out_read_raw_unlock; 345 case IIO_ANGL_VEL: 346 ret = regmap_bulk_read(mpu3050->map, 347 MPU3050_AXIS_REGS(chan->scan_index-1), 348 &raw_val, 349 sizeof(raw_val)); 350 if (ret) { 351 dev_err(mpu3050->dev, 352 "error reading axis data\n"); 353 goto out_read_raw_unlock; 354 } 355 356 *val = be16_to_cpu(raw_val); 357 ret = IIO_VAL_INT; 358 359 goto out_read_raw_unlock; 360 default: 361 ret = -EINVAL; 362 goto out_read_raw_unlock; 363 } 364 default: 365 break; 366 } 367 368 return -EINVAL; 369 370 out_read_raw_unlock: 371 mutex_unlock(&mpu3050->lock); 372 pm_runtime_mark_last_busy(mpu3050->dev); 373 pm_runtime_put_autosuspend(mpu3050->dev); 374 375 return ret; 376 } 377 378 static int mpu3050_write_raw(struct iio_dev *indio_dev, 379 const struct iio_chan_spec *chan, 380 int val, int val2, long mask) 381 { 382 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 383 /* 384 * Couldn't figure out a way to precalculate these at compile time. 385 */ 386 unsigned int fs250 = 387 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 388 U16_MAX); 389 unsigned int fs500 = 390 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 391 U16_MAX); 392 unsigned int fs1000 = 393 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 394 U16_MAX); 395 unsigned int fs2000 = 396 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 397 U16_MAX); 398 399 switch (mask) { 400 case IIO_CHAN_INFO_CALIBBIAS: 401 if (chan->type != IIO_ANGL_VEL) 402 return -EINVAL; 403 mpu3050->calibration[chan->scan_index-1] = val; 404 return 0; 405 case IIO_CHAN_INFO_SAMP_FREQ: 406 /* 407 * The max samplerate is 8000 Hz, the minimum 408 * 1000 / 256 ~= 4 Hz 409 */ 410 if (val < 4 || val > 8000) 411 return -EINVAL; 412 413 /* 414 * Above 1000 Hz we must turn off the digital low pass filter 415 * so we get a base frequency of 8kHz to the divider 416 */ 417 if (val > 1000) { 418 mpu3050->lpf = LPF_256_HZ_NOLPF; 419 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 420 return 0; 421 } 422 423 mpu3050->lpf = LPF_188_HZ; 424 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 425 return 0; 426 case IIO_CHAN_INFO_SCALE: 427 if (chan->type != IIO_ANGL_VEL) 428 return -EINVAL; 429 /* 430 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 431 * which means we need to round to the closest radians 432 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 433 * rad/s. The scale is then for the 16 bits used to cover 434 * it 2/(2^16) of that. 435 */ 436 437 /* Just too large, set the max range */ 438 if (val != 0) { 439 mpu3050->fullscale = FS_2000_DPS; 440 return 0; 441 } 442 443 /* 444 * Now we're dealing with fractions below zero in millirad/s 445 * do some integer interpolation and match with the closest 446 * fullscale in the table. 447 */ 448 if (val2 <= fs250 || 449 val2 < ((fs500 + fs250) / 2)) 450 mpu3050->fullscale = FS_250_DPS; 451 else if (val2 <= fs500 || 452 val2 < ((fs1000 + fs500) / 2)) 453 mpu3050->fullscale = FS_500_DPS; 454 else if (val2 <= fs1000 || 455 val2 < ((fs2000 + fs1000) / 2)) 456 mpu3050->fullscale = FS_1000_DPS; 457 else 458 /* Catch-all */ 459 mpu3050->fullscale = FS_2000_DPS; 460 return 0; 461 default: 462 break; 463 } 464 465 return -EINVAL; 466 } 467 468 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 469 { 470 const struct iio_poll_func *pf = p; 471 struct iio_dev *indio_dev = pf->indio_dev; 472 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 473 int ret; 474 /* 475 * Temperature 1*16 bits 476 * Three axes 3*16 bits 477 * Timestamp 64 bits (4*16 bits) 478 * Sum total 8*16 bits 479 */ 480 __be16 hw_values[8]; 481 s64 timestamp; 482 unsigned int datums_from_fifo = 0; 483 484 /* 485 * If we're using the hardware trigger, get the precise timestamp from 486 * the top half of the threaded IRQ handler. Otherwise get the 487 * timestamp here so it will be close in time to the actual values 488 * read from the registers. 489 */ 490 if (iio_trigger_using_own(indio_dev)) 491 timestamp = mpu3050->hw_timestamp; 492 else 493 timestamp = iio_get_time_ns(indio_dev); 494 495 mutex_lock(&mpu3050->lock); 496 497 /* Using the hardware IRQ trigger? Check the buffer then. */ 498 if (mpu3050->hw_irq_trigger) { 499 __be16 raw_fifocnt; 500 u16 fifocnt; 501 /* X, Y, Z + temperature */ 502 unsigned int bytes_per_datum = 8; 503 bool fifo_overflow = false; 504 505 ret = regmap_bulk_read(mpu3050->map, 506 MPU3050_FIFO_COUNT_H, 507 &raw_fifocnt, 508 sizeof(raw_fifocnt)); 509 if (ret) 510 goto out_trigger_unlock; 511 fifocnt = be16_to_cpu(raw_fifocnt); 512 513 if (fifocnt == 512) { 514 dev_info(mpu3050->dev, 515 "FIFO overflow! Emptying and resetting FIFO\n"); 516 fifo_overflow = true; 517 /* Reset and enable the FIFO */ 518 ret = regmap_update_bits(mpu3050->map, 519 MPU3050_USR_CTRL, 520 MPU3050_USR_CTRL_FIFO_EN | 521 MPU3050_USR_CTRL_FIFO_RST, 522 MPU3050_USR_CTRL_FIFO_EN | 523 MPU3050_USR_CTRL_FIFO_RST); 524 if (ret) { 525 dev_info(mpu3050->dev, "error resetting FIFO\n"); 526 goto out_trigger_unlock; 527 } 528 mpu3050->pending_fifo_footer = false; 529 } 530 531 if (fifocnt) 532 dev_dbg(mpu3050->dev, 533 "%d bytes in the FIFO\n", 534 fifocnt); 535 536 while (!fifo_overflow && fifocnt > bytes_per_datum) { 537 unsigned int toread; 538 unsigned int offset; 539 __be16 fifo_values[5]; 540 541 /* 542 * If there is a FIFO footer in the pipe, first clear 543 * that out. This follows the complex algorithm in the 544 * datasheet that states that you may never leave the 545 * FIFO empty after the first reading: you have to 546 * always leave two footer bytes in it. The footer is 547 * in practice just two zero bytes. 548 */ 549 if (mpu3050->pending_fifo_footer) { 550 toread = bytes_per_datum + 2; 551 offset = 0; 552 } else { 553 toread = bytes_per_datum; 554 offset = 1; 555 /* Put in some dummy value */ 556 fifo_values[0] = cpu_to_be16(0xAAAA); 557 } 558 559 ret = regmap_bulk_read(mpu3050->map, 560 MPU3050_FIFO_R, 561 &fifo_values[offset], 562 toread); 563 if (ret) 564 goto out_trigger_unlock; 565 566 dev_dbg(mpu3050->dev, 567 "%04x %04x %04x %04x %04x\n", 568 fifo_values[0], 569 fifo_values[1], 570 fifo_values[2], 571 fifo_values[3], 572 fifo_values[4]); 573 574 /* Index past the footer (fifo_values[0]) and push */ 575 iio_push_to_buffers_with_timestamp(indio_dev, 576 &fifo_values[1], 577 timestamp); 578 579 fifocnt -= toread; 580 datums_from_fifo++; 581 mpu3050->pending_fifo_footer = true; 582 583 /* 584 * If we're emptying the FIFO, just make sure to 585 * check if something new appeared. 586 */ 587 if (fifocnt < bytes_per_datum) { 588 ret = regmap_bulk_read(mpu3050->map, 589 MPU3050_FIFO_COUNT_H, 590 &raw_fifocnt, 591 sizeof(raw_fifocnt)); 592 if (ret) 593 goto out_trigger_unlock; 594 fifocnt = be16_to_cpu(raw_fifocnt); 595 } 596 597 if (fifocnt < bytes_per_datum) 598 dev_dbg(mpu3050->dev, 599 "%d bytes left in the FIFO\n", 600 fifocnt); 601 602 /* 603 * At this point, the timestamp that triggered the 604 * hardware interrupt is no longer valid for what 605 * we are reading (the interrupt likely fired for 606 * the value on the top of the FIFO), so set the 607 * timestamp to zero and let userspace deal with it. 608 */ 609 timestamp = 0; 610 } 611 } 612 613 /* 614 * If we picked some datums from the FIFO that's enough, else 615 * fall through and just read from the current value registers. 616 * This happens in two cases: 617 * 618 * - We are using some other trigger (external, like an HRTimer) 619 * than the sensor's own sample generator. In this case the 620 * sensor is just set to the max sampling frequency and we give 621 * the trigger a copy of the latest value every time we get here. 622 * 623 * - The hardware trigger is active but unused and we actually use 624 * another trigger which calls here with a frequency higher 625 * than what the device provides data. We will then just read 626 * duplicate values directly from the hardware registers. 627 */ 628 if (datums_from_fifo) { 629 dev_dbg(mpu3050->dev, 630 "read %d datums from the FIFO\n", 631 datums_from_fifo); 632 goto out_trigger_unlock; 633 } 634 635 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values, 636 sizeof(hw_values)); 637 if (ret) { 638 dev_err(mpu3050->dev, 639 "error reading axis data\n"); 640 goto out_trigger_unlock; 641 } 642 643 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp); 644 645 out_trigger_unlock: 646 mutex_unlock(&mpu3050->lock); 647 iio_trigger_notify_done(indio_dev->trig); 648 649 return IRQ_HANDLED; 650 } 651 652 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 653 { 654 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 655 656 pm_runtime_get_sync(mpu3050->dev); 657 658 /* Unless we have OUR trigger active, run at full speed */ 659 if (!mpu3050->hw_irq_trigger) 660 return mpu3050_set_8khz_samplerate(mpu3050); 661 662 return 0; 663 } 664 665 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 666 { 667 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 668 669 pm_runtime_mark_last_busy(mpu3050->dev); 670 pm_runtime_put_autosuspend(mpu3050->dev); 671 672 return 0; 673 } 674 675 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 676 .preenable = mpu3050_buffer_preenable, 677 .postdisable = mpu3050_buffer_postdisable, 678 }; 679 680 static const struct iio_mount_matrix * 681 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 682 const struct iio_chan_spec *chan) 683 { 684 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 685 686 return &mpu3050->orientation; 687 } 688 689 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 690 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 691 { }, 692 }; 693 694 #define MPU3050_AXIS_CHANNEL(axis, index) \ 695 { \ 696 .type = IIO_ANGL_VEL, \ 697 .modified = 1, \ 698 .channel2 = IIO_MOD_##axis, \ 699 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 700 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 701 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 702 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 703 .ext_info = mpu3050_ext_info, \ 704 .scan_index = index, \ 705 .scan_type = { \ 706 .sign = 's', \ 707 .realbits = 16, \ 708 .storagebits = 16, \ 709 .endianness = IIO_BE, \ 710 }, \ 711 } 712 713 static const struct iio_chan_spec mpu3050_channels[] = { 714 { 715 .type = IIO_TEMP, 716 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 717 BIT(IIO_CHAN_INFO_SCALE) | 718 BIT(IIO_CHAN_INFO_OFFSET), 719 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 720 .scan_index = 0, 721 .scan_type = { 722 .sign = 's', 723 .realbits = 16, 724 .storagebits = 16, 725 .endianness = IIO_BE, 726 }, 727 }, 728 MPU3050_AXIS_CHANNEL(X, 1), 729 MPU3050_AXIS_CHANNEL(Y, 2), 730 MPU3050_AXIS_CHANNEL(Z, 3), 731 IIO_CHAN_SOFT_TIMESTAMP(4), 732 }; 733 734 /* Four channels apart from timestamp, scan mask = 0x0f */ 735 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 736 737 /* 738 * These are just the hardcoded factors resulting from the more elaborate 739 * calculations done with fractions in the scale raw get/set functions. 740 */ 741 static IIO_CONST_ATTR(anglevel_scale_available, 742 "0.000122070 " 743 "0.000274658 " 744 "0.000518798 " 745 "0.001068115"); 746 747 static struct attribute *mpu3050_attributes[] = { 748 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 749 NULL, 750 }; 751 752 static const struct attribute_group mpu3050_attribute_group = { 753 .attrs = mpu3050_attributes, 754 }; 755 756 static const struct iio_info mpu3050_info = { 757 .read_raw = mpu3050_read_raw, 758 .write_raw = mpu3050_write_raw, 759 .attrs = &mpu3050_attribute_group, 760 }; 761 762 /** 763 * mpu3050_read_mem() - read MPU-3050 internal memory 764 * @mpu3050: device to read from 765 * @bank: target bank 766 * @addr: target address 767 * @len: number of bytes 768 * @buf: the buffer to store the read bytes in 769 */ 770 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 771 u8 bank, 772 u8 addr, 773 u8 len, 774 u8 *buf) 775 { 776 int ret; 777 778 ret = regmap_write(mpu3050->map, 779 MPU3050_BANK_SEL, 780 bank); 781 if (ret) 782 return ret; 783 784 ret = regmap_write(mpu3050->map, 785 MPU3050_MEM_START_ADDR, 786 addr); 787 if (ret) 788 return ret; 789 790 return regmap_bulk_read(mpu3050->map, 791 MPU3050_MEM_R_W, 792 buf, 793 len); 794 } 795 796 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 797 { 798 int ret; 799 __le64 otp_le; 800 u64 otp; 801 802 /* Reset */ 803 ret = regmap_update_bits(mpu3050->map, 804 MPU3050_PWR_MGM, 805 MPU3050_PWR_MGM_RESET, 806 MPU3050_PWR_MGM_RESET); 807 if (ret) 808 return ret; 809 810 /* Turn on the PLL */ 811 ret = regmap_update_bits(mpu3050->map, 812 MPU3050_PWR_MGM, 813 MPU3050_PWR_MGM_CLKSEL_MASK, 814 MPU3050_PWR_MGM_PLL_Z); 815 if (ret) 816 return ret; 817 818 /* Disable IRQs */ 819 ret = regmap_write(mpu3050->map, 820 MPU3050_INT_CFG, 821 0); 822 if (ret) 823 return ret; 824 825 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 826 ret = mpu3050_read_mem(mpu3050, 827 (MPU3050_MEM_PRFTCH | 828 MPU3050_MEM_USER_BANK | 829 MPU3050_MEM_OTP_BANK_0), 830 0, 831 sizeof(otp_le), 832 (u8 *)&otp_le); 833 if (ret) 834 return ret; 835 836 /* This is device-unique data so it goes into the entropy pool */ 837 add_device_randomness(&otp_le, sizeof(otp_le)); 838 839 otp = le64_to_cpu(otp_le); 840 841 dev_info(mpu3050->dev, 842 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 843 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 844 /* Die ID, bits 0-12 */ 845 FIELD_GET(GENMASK_ULL(12, 0), otp), 846 /* Wafer ID, bits 13-17 */ 847 FIELD_GET(GENMASK_ULL(17, 13), otp), 848 /* A lot ID, bits 18-33 */ 849 FIELD_GET(GENMASK_ULL(33, 18), otp), 850 /* W lot ID, bits 34-45 */ 851 FIELD_GET(GENMASK_ULL(45, 34), otp), 852 /* WP ID, bits 47-49 */ 853 FIELD_GET(GENMASK_ULL(49, 47), otp), 854 /* rev ID, bits 50-55 */ 855 FIELD_GET(GENMASK_ULL(55, 50), otp)); 856 857 return 0; 858 } 859 860 static int mpu3050_power_up(struct mpu3050 *mpu3050) 861 { 862 int ret; 863 864 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 865 if (ret) { 866 dev_err(mpu3050->dev, "cannot enable regulators\n"); 867 return ret; 868 } 869 /* 870 * 20-100 ms start-up time for register read/write according to 871 * the datasheet, be on the safe side and wait 200 ms. 872 */ 873 msleep(200); 874 875 /* Take device out of sleep mode */ 876 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 877 MPU3050_PWR_MGM_SLEEP, 0); 878 if (ret) { 879 dev_err(mpu3050->dev, "error setting power mode\n"); 880 return ret; 881 } 882 usleep_range(10000, 20000); 883 884 return 0; 885 } 886 887 static int mpu3050_power_down(struct mpu3050 *mpu3050) 888 { 889 int ret; 890 891 /* 892 * Put MPU-3050 into sleep mode before cutting regulators. 893 * This is important, because we may not be the sole user 894 * of the regulator so the power may stay on after this, and 895 * then we would be wasting power unless we go to sleep mode 896 * first. 897 */ 898 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 899 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 900 if (ret) 901 dev_err(mpu3050->dev, "error putting to sleep\n"); 902 903 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 904 if (ret) 905 dev_err(mpu3050->dev, "error disabling regulators\n"); 906 907 return 0; 908 } 909 910 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 911 { 912 struct iio_trigger *trig = p; 913 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 914 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 915 916 if (!mpu3050->hw_irq_trigger) 917 return IRQ_NONE; 918 919 /* Get the time stamp as close in time as possible */ 920 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 921 922 return IRQ_WAKE_THREAD; 923 } 924 925 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 926 { 927 struct iio_trigger *trig = p; 928 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 929 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 930 unsigned int val; 931 int ret; 932 933 /* ACK IRQ and check if it was from us */ 934 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 935 if (ret) { 936 dev_err(mpu3050->dev, "error reading IRQ status\n"); 937 return IRQ_HANDLED; 938 } 939 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 940 return IRQ_NONE; 941 942 iio_trigger_poll_chained(p); 943 944 return IRQ_HANDLED; 945 } 946 947 /** 948 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 949 * @trig: trigger instance 950 * @enable: true if trigger should be enabled, false to disable 951 */ 952 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 953 bool enable) 954 { 955 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 956 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 957 unsigned int val; 958 int ret; 959 960 /* Disabling trigger: disable interrupt and return */ 961 if (!enable) { 962 /* Disable all interrupts */ 963 ret = regmap_write(mpu3050->map, 964 MPU3050_INT_CFG, 965 0); 966 if (ret) 967 dev_err(mpu3050->dev, "error disabling IRQ\n"); 968 969 /* Clear IRQ flag */ 970 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 971 if (ret) 972 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 973 974 /* Disable all things in the FIFO and reset it */ 975 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 976 if (ret) 977 dev_err(mpu3050->dev, "error disabling FIFO\n"); 978 979 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 980 MPU3050_USR_CTRL_FIFO_RST); 981 if (ret) 982 dev_err(mpu3050->dev, "error resetting FIFO\n"); 983 984 pm_runtime_mark_last_busy(mpu3050->dev); 985 pm_runtime_put_autosuspend(mpu3050->dev); 986 mpu3050->hw_irq_trigger = false; 987 988 return 0; 989 } else { 990 /* Else we're enabling the trigger from this point */ 991 pm_runtime_get_sync(mpu3050->dev); 992 mpu3050->hw_irq_trigger = true; 993 994 /* Disable all things in the FIFO */ 995 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 996 if (ret) 997 return ret; 998 999 /* Reset and enable the FIFO */ 1000 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 1001 MPU3050_USR_CTRL_FIFO_EN | 1002 MPU3050_USR_CTRL_FIFO_RST, 1003 MPU3050_USR_CTRL_FIFO_EN | 1004 MPU3050_USR_CTRL_FIFO_RST); 1005 if (ret) 1006 return ret; 1007 1008 mpu3050->pending_fifo_footer = false; 1009 1010 /* Turn on the FIFO for temp+X+Y+Z */ 1011 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1012 MPU3050_FIFO_EN_TEMP_OUT | 1013 MPU3050_FIFO_EN_GYRO_XOUT | 1014 MPU3050_FIFO_EN_GYRO_YOUT | 1015 MPU3050_FIFO_EN_GYRO_ZOUT | 1016 MPU3050_FIFO_EN_FOOTER); 1017 if (ret) 1018 return ret; 1019 1020 /* Configure the sample engine */ 1021 ret = mpu3050_start_sampling(mpu3050); 1022 if (ret) 1023 return ret; 1024 1025 /* Clear IRQ flag */ 1026 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1027 if (ret) 1028 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1029 1030 /* Give us interrupts whenever there is new data ready */ 1031 val = MPU3050_INT_RAW_RDY_EN; 1032 1033 if (mpu3050->irq_actl) 1034 val |= MPU3050_INT_ACTL; 1035 if (mpu3050->irq_latch) 1036 val |= MPU3050_INT_LATCH_EN; 1037 if (mpu3050->irq_opendrain) 1038 val |= MPU3050_INT_OPEN; 1039 1040 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1049 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1050 }; 1051 1052 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1053 { 1054 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1055 unsigned long irq_trig; 1056 int ret; 1057 1058 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1059 "%s-dev%d", 1060 indio_dev->name, 1061 iio_device_id(indio_dev)); 1062 if (!mpu3050->trig) 1063 return -ENOMEM; 1064 1065 /* Check if IRQ is open drain */ 1066 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain")) 1067 mpu3050->irq_opendrain = true; 1068 1069 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1070 /* 1071 * Configure the interrupt generator hardware to supply whatever 1072 * the interrupt is configured for, edges low/high level low/high, 1073 * we can provide it all. 1074 */ 1075 switch (irq_trig) { 1076 case IRQF_TRIGGER_RISING: 1077 dev_info(&indio_dev->dev, 1078 "pulse interrupts on the rising edge\n"); 1079 break; 1080 case IRQF_TRIGGER_FALLING: 1081 mpu3050->irq_actl = true; 1082 dev_info(&indio_dev->dev, 1083 "pulse interrupts on the falling edge\n"); 1084 break; 1085 case IRQF_TRIGGER_HIGH: 1086 mpu3050->irq_latch = true; 1087 dev_info(&indio_dev->dev, 1088 "interrupts active high level\n"); 1089 /* 1090 * With level IRQs, we mask the IRQ until it is processed, 1091 * but with edge IRQs (pulses) we can queue several interrupts 1092 * in the top half. 1093 */ 1094 irq_trig |= IRQF_ONESHOT; 1095 break; 1096 case IRQF_TRIGGER_LOW: 1097 mpu3050->irq_latch = true; 1098 mpu3050->irq_actl = true; 1099 irq_trig |= IRQF_ONESHOT; 1100 dev_info(&indio_dev->dev, 1101 "interrupts active low level\n"); 1102 break; 1103 default: 1104 /* This is the most preferred mode, if possible */ 1105 dev_err(&indio_dev->dev, 1106 "unsupported IRQ trigger specified (%lx), enforce " 1107 "rising edge\n", irq_trig); 1108 irq_trig = IRQF_TRIGGER_RISING; 1109 break; 1110 } 1111 1112 /* An open drain line can be shared with several devices */ 1113 if (mpu3050->irq_opendrain) 1114 irq_trig |= IRQF_SHARED; 1115 1116 ret = request_threaded_irq(irq, 1117 mpu3050_irq_handler, 1118 mpu3050_irq_thread, 1119 irq_trig, 1120 mpu3050->trig->name, 1121 mpu3050->trig); 1122 if (ret) { 1123 dev_err(mpu3050->dev, 1124 "can't get IRQ %d, error %d\n", irq, ret); 1125 return ret; 1126 } 1127 1128 mpu3050->irq = irq; 1129 mpu3050->trig->dev.parent = mpu3050->dev; 1130 mpu3050->trig->ops = &mpu3050_trigger_ops; 1131 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1132 1133 ret = iio_trigger_register(mpu3050->trig); 1134 if (ret) 1135 return ret; 1136 1137 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1138 1139 return 0; 1140 } 1141 1142 int mpu3050_common_probe(struct device *dev, 1143 struct regmap *map, 1144 int irq, 1145 const char *name) 1146 { 1147 struct iio_dev *indio_dev; 1148 struct mpu3050 *mpu3050; 1149 unsigned int val; 1150 int ret; 1151 1152 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1153 if (!indio_dev) 1154 return -ENOMEM; 1155 mpu3050 = iio_priv(indio_dev); 1156 1157 mpu3050->dev = dev; 1158 mpu3050->map = map; 1159 mutex_init(&mpu3050->lock); 1160 /* Default fullscale: 2000 degrees per second */ 1161 mpu3050->fullscale = FS_2000_DPS; 1162 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1163 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1164 mpu3050->divisor = 99; 1165 1166 /* Read the mounting matrix, if present */ 1167 ret = iio_read_mount_matrix(dev, &mpu3050->orientation); 1168 if (ret) 1169 return ret; 1170 1171 /* Fetch and turn on regulators */ 1172 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1173 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1174 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1175 mpu3050->regs); 1176 if (ret) { 1177 dev_err(dev, "Cannot get regulators\n"); 1178 return ret; 1179 } 1180 1181 ret = mpu3050_power_up(mpu3050); 1182 if (ret) 1183 return ret; 1184 1185 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1186 if (ret) { 1187 dev_err(dev, "could not read device ID\n"); 1188 ret = -ENODEV; 1189 1190 goto err_power_down; 1191 } 1192 1193 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1194 dev_err(dev, "unsupported chip id %02x\n", 1195 (u8)(val & MPU3050_CHIP_ID_MASK)); 1196 ret = -ENODEV; 1197 goto err_power_down; 1198 } 1199 1200 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1201 if (ret) { 1202 dev_err(dev, "could not read device ID\n"); 1203 ret = -ENODEV; 1204 1205 goto err_power_down; 1206 } 1207 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1208 ((val >> 4) & 0xf), (val & 0xf)); 1209 1210 ret = mpu3050_hw_init(mpu3050); 1211 if (ret) 1212 goto err_power_down; 1213 1214 indio_dev->channels = mpu3050_channels; 1215 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1216 indio_dev->info = &mpu3050_info; 1217 indio_dev->available_scan_masks = mpu3050_scan_masks; 1218 indio_dev->modes = INDIO_DIRECT_MODE; 1219 indio_dev->name = name; 1220 1221 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1222 mpu3050_trigger_handler, 1223 &mpu3050_buffer_setup_ops); 1224 if (ret) { 1225 dev_err(dev, "triggered buffer setup failed\n"); 1226 goto err_power_down; 1227 } 1228 1229 ret = iio_device_register(indio_dev); 1230 if (ret) { 1231 dev_err(dev, "device register failed\n"); 1232 goto err_cleanup_buffer; 1233 } 1234 1235 dev_set_drvdata(dev, indio_dev); 1236 1237 /* Check if we have an assigned IRQ to use as trigger */ 1238 if (irq) { 1239 ret = mpu3050_trigger_probe(indio_dev, irq); 1240 if (ret) 1241 dev_err(dev, "failed to register trigger\n"); 1242 } 1243 1244 /* Enable runtime PM */ 1245 pm_runtime_get_noresume(dev); 1246 pm_runtime_set_active(dev); 1247 pm_runtime_enable(dev); 1248 /* 1249 * Set autosuspend to two orders of magnitude larger than the 1250 * start-up time. 100ms start-up time means 10000ms autosuspend, 1251 * i.e. 10 seconds. 1252 */ 1253 pm_runtime_set_autosuspend_delay(dev, 10000); 1254 pm_runtime_use_autosuspend(dev); 1255 pm_runtime_put(dev); 1256 1257 return 0; 1258 1259 err_cleanup_buffer: 1260 iio_triggered_buffer_cleanup(indio_dev); 1261 err_power_down: 1262 mpu3050_power_down(mpu3050); 1263 1264 return ret; 1265 } 1266 EXPORT_SYMBOL(mpu3050_common_probe); 1267 1268 int mpu3050_common_remove(struct device *dev) 1269 { 1270 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1271 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1272 1273 pm_runtime_get_sync(dev); 1274 pm_runtime_put_noidle(dev); 1275 pm_runtime_disable(dev); 1276 iio_triggered_buffer_cleanup(indio_dev); 1277 if (mpu3050->irq) 1278 free_irq(mpu3050->irq, mpu3050); 1279 iio_device_unregister(indio_dev); 1280 mpu3050_power_down(mpu3050); 1281 1282 return 0; 1283 } 1284 EXPORT_SYMBOL(mpu3050_common_remove); 1285 1286 #ifdef CONFIG_PM 1287 static int mpu3050_runtime_suspend(struct device *dev) 1288 { 1289 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1290 } 1291 1292 static int mpu3050_runtime_resume(struct device *dev) 1293 { 1294 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1295 } 1296 #endif /* CONFIG_PM */ 1297 1298 const struct dev_pm_ops mpu3050_dev_pm_ops = { 1299 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1300 pm_runtime_force_resume) 1301 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, 1302 mpu3050_runtime_resume, NULL) 1303 }; 1304 EXPORT_SYMBOL(mpu3050_dev_pm_ops); 1305 1306 MODULE_AUTHOR("Linus Walleij"); 1307 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1308 MODULE_LICENSE("GPL"); 1309