1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/slab.h> 31 32 #include "mpu3050.h" 33 34 #define MPU3050_CHIP_ID 0x68 35 #define MPU3050_CHIP_ID_MASK 0x7E 36 37 /* 38 * Register map: anything suffixed *_H is a big-endian high byte and always 39 * followed by the corresponding low byte (*_L) even though these are not 40 * explicitly included in the register definitions. 41 */ 42 #define MPU3050_CHIP_ID_REG 0x00 43 #define MPU3050_PRODUCT_ID_REG 0x01 44 #define MPU3050_XG_OFFS_TC 0x05 45 #define MPU3050_YG_OFFS_TC 0x08 46 #define MPU3050_ZG_OFFS_TC 0x0B 47 #define MPU3050_X_OFFS_USR_H 0x0C 48 #define MPU3050_Y_OFFS_USR_H 0x0E 49 #define MPU3050_Z_OFFS_USR_H 0x10 50 #define MPU3050_FIFO_EN 0x12 51 #define MPU3050_AUX_VDDIO 0x13 52 #define MPU3050_SLV_ADDR 0x14 53 #define MPU3050_SMPLRT_DIV 0x15 54 #define MPU3050_DLPF_FS_SYNC 0x16 55 #define MPU3050_INT_CFG 0x17 56 #define MPU3050_AUX_ADDR 0x18 57 #define MPU3050_INT_STATUS 0x1A 58 #define MPU3050_TEMP_H 0x1B 59 #define MPU3050_XOUT_H 0x1D 60 #define MPU3050_YOUT_H 0x1F 61 #define MPU3050_ZOUT_H 0x21 62 #define MPU3050_DMP_CFG1 0x35 63 #define MPU3050_DMP_CFG2 0x36 64 #define MPU3050_BANK_SEL 0x37 65 #define MPU3050_MEM_START_ADDR 0x38 66 #define MPU3050_MEM_R_W 0x39 67 #define MPU3050_FIFO_COUNT_H 0x3A 68 #define MPU3050_FIFO_R 0x3C 69 #define MPU3050_USR_CTRL 0x3D 70 #define MPU3050_PWR_MGM 0x3E 71 72 /* MPU memory bank read options */ 73 #define MPU3050_MEM_PRFTCH BIT(5) 74 #define MPU3050_MEM_USER_BANK BIT(4) 75 /* Bits 8-11 select memory bank */ 76 #define MPU3050_MEM_RAM_BANK_0 0 77 #define MPU3050_MEM_RAM_BANK_1 1 78 #define MPU3050_MEM_RAM_BANK_2 2 79 #define MPU3050_MEM_RAM_BANK_3 3 80 #define MPU3050_MEM_OTP_BANK_0 4 81 82 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 83 84 /* Register bits */ 85 86 /* FIFO Enable */ 87 #define MPU3050_FIFO_EN_FOOTER BIT(0) 88 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 89 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 90 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 91 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 92 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 93 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 94 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 95 96 /* 97 * Digital Low Pass filter (DLPF) 98 * Full Scale (FS) 99 * and Synchronization 100 */ 101 #define MPU3050_EXT_SYNC_NONE 0x00 102 #define MPU3050_EXT_SYNC_TEMP 0x20 103 #define MPU3050_EXT_SYNC_GYROX 0x40 104 #define MPU3050_EXT_SYNC_GYROY 0x60 105 #define MPU3050_EXT_SYNC_GYROZ 0x80 106 #define MPU3050_EXT_SYNC_ACCELX 0xA0 107 #define MPU3050_EXT_SYNC_ACCELY 0xC0 108 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 109 #define MPU3050_EXT_SYNC_MASK 0xE0 110 #define MPU3050_EXT_SYNC_SHIFT 5 111 112 #define MPU3050_FS_250DPS 0x00 113 #define MPU3050_FS_500DPS 0x08 114 #define MPU3050_FS_1000DPS 0x10 115 #define MPU3050_FS_2000DPS 0x18 116 #define MPU3050_FS_MASK 0x18 117 #define MPU3050_FS_SHIFT 3 118 119 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 120 #define MPU3050_DLPF_CFG_188HZ 0x01 121 #define MPU3050_DLPF_CFG_98HZ 0x02 122 #define MPU3050_DLPF_CFG_42HZ 0x03 123 #define MPU3050_DLPF_CFG_20HZ 0x04 124 #define MPU3050_DLPF_CFG_10HZ 0x05 125 #define MPU3050_DLPF_CFG_5HZ 0x06 126 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 127 #define MPU3050_DLPF_CFG_MASK 0x07 128 #define MPU3050_DLPF_CFG_SHIFT 0 129 130 /* Interrupt config */ 131 #define MPU3050_INT_RAW_RDY_EN BIT(0) 132 #define MPU3050_INT_DMP_DONE_EN BIT(1) 133 #define MPU3050_INT_MPU_RDY_EN BIT(2) 134 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 135 #define MPU3050_INT_LATCH_EN BIT(5) 136 #define MPU3050_INT_OPEN BIT(6) 137 #define MPU3050_INT_ACTL BIT(7) 138 /* Interrupt status */ 139 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 140 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 141 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 142 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 143 /* USR_CTRL */ 144 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 145 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 146 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 147 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 148 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 149 /* PWR_MGM */ 150 #define MPU3050_PWR_MGM_PLL_X 0x01 151 #define MPU3050_PWR_MGM_PLL_Y 0x02 152 #define MPU3050_PWR_MGM_PLL_Z 0x03 153 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 154 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 155 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 156 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 157 #define MPU3050_PWR_MGM_SLEEP BIT(6) 158 #define MPU3050_PWR_MGM_RESET BIT(7) 159 #define MPU3050_PWR_MGM_MASK 0xff 160 161 /* 162 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 163 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 164 * in two's complement. 165 */ 166 static unsigned int mpu3050_fs_precision[] = { 167 IIO_DEGREE_TO_RAD(250), 168 IIO_DEGREE_TO_RAD(500), 169 IIO_DEGREE_TO_RAD(1000), 170 IIO_DEGREE_TO_RAD(2000) 171 }; 172 173 /* 174 * Regulator names 175 */ 176 static const char mpu3050_reg_vdd[] = "vdd"; 177 static const char mpu3050_reg_vlogic[] = "vlogic"; 178 179 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 180 { 181 unsigned int freq; 182 183 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 184 freq = 8000; 185 else 186 freq = 1000; 187 freq /= (mpu3050->divisor + 1); 188 189 return freq; 190 } 191 192 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 193 { 194 __be16 raw_val[3]; 195 int ret; 196 int i; 197 198 /* Reset */ 199 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 200 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 201 if (ret) 202 return ret; 203 204 /* Turn on the Z-axis PLL */ 205 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 206 MPU3050_PWR_MGM_CLKSEL_MASK, 207 MPU3050_PWR_MGM_PLL_Z); 208 if (ret) 209 return ret; 210 211 /* Write calibration offset registers */ 212 for (i = 0; i < 3; i++) 213 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 214 215 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 216 sizeof(raw_val)); 217 if (ret) 218 return ret; 219 220 /* Set low pass filter (sample rate), sync and full scale */ 221 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 222 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 223 mpu3050->fullscale << MPU3050_FS_SHIFT | 224 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 225 if (ret) 226 return ret; 227 228 /* Set up sampling frequency */ 229 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 230 if (ret) 231 return ret; 232 233 /* 234 * Max 50 ms start-up time after setting DLPF_FS_SYNC 235 * according to the data sheet, then wait for the next sample 236 * at this frequency T = 1000/f ms. 237 */ 238 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 239 240 return 0; 241 } 242 243 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 244 { 245 int ret; 246 u8 divisor; 247 enum mpu3050_lpf lpf; 248 249 lpf = mpu3050->lpf; 250 divisor = mpu3050->divisor; 251 252 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 253 mpu3050->divisor = 0; /* Divide by 1 */ 254 ret = mpu3050_start_sampling(mpu3050); 255 256 mpu3050->lpf = lpf; 257 mpu3050->divisor = divisor; 258 259 return ret; 260 } 261 262 static int mpu3050_read_raw(struct iio_dev *indio_dev, 263 struct iio_chan_spec const *chan, 264 int *val, int *val2, 265 long mask) 266 { 267 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 268 int ret; 269 __be16 raw_val; 270 271 switch (mask) { 272 case IIO_CHAN_INFO_OFFSET: 273 switch (chan->type) { 274 case IIO_TEMP: 275 /* The temperature scaling is (x+23000)/280 Celsius */ 276 *val = 23000; 277 return IIO_VAL_INT; 278 default: 279 return -EINVAL; 280 } 281 case IIO_CHAN_INFO_CALIBBIAS: 282 switch (chan->type) { 283 case IIO_ANGL_VEL: 284 *val = mpu3050->calibration[chan->scan_index-1]; 285 return IIO_VAL_INT; 286 default: 287 return -EINVAL; 288 } 289 case IIO_CHAN_INFO_SAMP_FREQ: 290 *val = mpu3050_get_freq(mpu3050); 291 return IIO_VAL_INT; 292 case IIO_CHAN_INFO_SCALE: 293 switch (chan->type) { 294 case IIO_TEMP: 295 /* Millidegrees, see about temperature scaling above */ 296 *val = 1000; 297 *val2 = 280; 298 return IIO_VAL_FRACTIONAL; 299 case IIO_ANGL_VEL: 300 /* 301 * Convert to the corresponding full scale in 302 * radians. All 16 bits are used with sign to 303 * span the available scale: to account for the one 304 * missing value if we multiply by 1/S16_MAX, instead 305 * multiply with 2/U16_MAX. 306 */ 307 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 308 *val2 = U16_MAX; 309 return IIO_VAL_FRACTIONAL; 310 default: 311 return -EINVAL; 312 } 313 case IIO_CHAN_INFO_RAW: 314 /* Resume device */ 315 pm_runtime_get_sync(mpu3050->dev); 316 mutex_lock(&mpu3050->lock); 317 318 ret = mpu3050_set_8khz_samplerate(mpu3050); 319 if (ret) 320 goto out_read_raw_unlock; 321 322 switch (chan->type) { 323 case IIO_TEMP: 324 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 325 &raw_val, sizeof(raw_val)); 326 if (ret) { 327 dev_err(mpu3050->dev, 328 "error reading temperature\n"); 329 goto out_read_raw_unlock; 330 } 331 332 *val = be16_to_cpu(raw_val); 333 ret = IIO_VAL_INT; 334 335 goto out_read_raw_unlock; 336 case IIO_ANGL_VEL: 337 ret = regmap_bulk_read(mpu3050->map, 338 MPU3050_AXIS_REGS(chan->scan_index-1), 339 &raw_val, 340 sizeof(raw_val)); 341 if (ret) { 342 dev_err(mpu3050->dev, 343 "error reading axis data\n"); 344 goto out_read_raw_unlock; 345 } 346 347 *val = be16_to_cpu(raw_val); 348 ret = IIO_VAL_INT; 349 350 goto out_read_raw_unlock; 351 default: 352 ret = -EINVAL; 353 goto out_read_raw_unlock; 354 } 355 default: 356 break; 357 } 358 359 return -EINVAL; 360 361 out_read_raw_unlock: 362 mutex_unlock(&mpu3050->lock); 363 pm_runtime_mark_last_busy(mpu3050->dev); 364 pm_runtime_put_autosuspend(mpu3050->dev); 365 366 return ret; 367 } 368 369 static int mpu3050_write_raw(struct iio_dev *indio_dev, 370 const struct iio_chan_spec *chan, 371 int val, int val2, long mask) 372 { 373 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 374 /* 375 * Couldn't figure out a way to precalculate these at compile time. 376 */ 377 unsigned int fs250 = 378 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 379 U16_MAX); 380 unsigned int fs500 = 381 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 382 U16_MAX); 383 unsigned int fs1000 = 384 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 385 U16_MAX); 386 unsigned int fs2000 = 387 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 388 U16_MAX); 389 390 switch (mask) { 391 case IIO_CHAN_INFO_CALIBBIAS: 392 if (chan->type != IIO_ANGL_VEL) 393 return -EINVAL; 394 mpu3050->calibration[chan->scan_index-1] = val; 395 return 0; 396 case IIO_CHAN_INFO_SAMP_FREQ: 397 /* 398 * The max samplerate is 8000 Hz, the minimum 399 * 1000 / 256 ~= 4 Hz 400 */ 401 if (val < 4 || val > 8000) 402 return -EINVAL; 403 404 /* 405 * Above 1000 Hz we must turn off the digital low pass filter 406 * so we get a base frequency of 8kHz to the divider 407 */ 408 if (val > 1000) { 409 mpu3050->lpf = LPF_256_HZ_NOLPF; 410 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 411 return 0; 412 } 413 414 mpu3050->lpf = LPF_188_HZ; 415 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 416 return 0; 417 case IIO_CHAN_INFO_SCALE: 418 if (chan->type != IIO_ANGL_VEL) 419 return -EINVAL; 420 /* 421 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 422 * which means we need to round to the closest radians 423 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 424 * rad/s. The scale is then for the 16 bits used to cover 425 * it 2/(2^16) of that. 426 */ 427 428 /* Just too large, set the max range */ 429 if (val != 0) { 430 mpu3050->fullscale = FS_2000_DPS; 431 return 0; 432 } 433 434 /* 435 * Now we're dealing with fractions below zero in millirad/s 436 * do some integer interpolation and match with the closest 437 * fullscale in the table. 438 */ 439 if (val2 <= fs250 || 440 val2 < ((fs500 + fs250) / 2)) 441 mpu3050->fullscale = FS_250_DPS; 442 else if (val2 <= fs500 || 443 val2 < ((fs1000 + fs500) / 2)) 444 mpu3050->fullscale = FS_500_DPS; 445 else if (val2 <= fs1000 || 446 val2 < ((fs2000 + fs1000) / 2)) 447 mpu3050->fullscale = FS_1000_DPS; 448 else 449 /* Catch-all */ 450 mpu3050->fullscale = FS_2000_DPS; 451 return 0; 452 default: 453 break; 454 } 455 456 return -EINVAL; 457 } 458 459 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 460 { 461 const struct iio_poll_func *pf = p; 462 struct iio_dev *indio_dev = pf->indio_dev; 463 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 464 int ret; 465 /* 466 * Temperature 1*16 bits 467 * Three axes 3*16 bits 468 * Timestamp 64 bits (4*16 bits) 469 * Sum total 8*16 bits 470 */ 471 __be16 hw_values[8]; 472 s64 timestamp; 473 unsigned int datums_from_fifo = 0; 474 475 /* 476 * If we're using the hardware trigger, get the precise timestamp from 477 * the top half of the threaded IRQ handler. Otherwise get the 478 * timestamp here so it will be close in time to the actual values 479 * read from the registers. 480 */ 481 if (iio_trigger_using_own(indio_dev)) 482 timestamp = mpu3050->hw_timestamp; 483 else 484 timestamp = iio_get_time_ns(indio_dev); 485 486 mutex_lock(&mpu3050->lock); 487 488 /* Using the hardware IRQ trigger? Check the buffer then. */ 489 if (mpu3050->hw_irq_trigger) { 490 __be16 raw_fifocnt; 491 u16 fifocnt; 492 /* X, Y, Z + temperature */ 493 unsigned int bytes_per_datum = 8; 494 bool fifo_overflow = false; 495 496 ret = regmap_bulk_read(mpu3050->map, 497 MPU3050_FIFO_COUNT_H, 498 &raw_fifocnt, 499 sizeof(raw_fifocnt)); 500 if (ret) 501 goto out_trigger_unlock; 502 fifocnt = be16_to_cpu(raw_fifocnt); 503 504 if (fifocnt == 512) { 505 dev_info(mpu3050->dev, 506 "FIFO overflow! Emptying and resetting FIFO\n"); 507 fifo_overflow = true; 508 /* Reset and enable the FIFO */ 509 ret = regmap_update_bits(mpu3050->map, 510 MPU3050_USR_CTRL, 511 MPU3050_USR_CTRL_FIFO_EN | 512 MPU3050_USR_CTRL_FIFO_RST, 513 MPU3050_USR_CTRL_FIFO_EN | 514 MPU3050_USR_CTRL_FIFO_RST); 515 if (ret) { 516 dev_info(mpu3050->dev, "error resetting FIFO\n"); 517 goto out_trigger_unlock; 518 } 519 mpu3050->pending_fifo_footer = false; 520 } 521 522 if (fifocnt) 523 dev_dbg(mpu3050->dev, 524 "%d bytes in the FIFO\n", 525 fifocnt); 526 527 while (!fifo_overflow && fifocnt > bytes_per_datum) { 528 unsigned int toread; 529 unsigned int offset; 530 __be16 fifo_values[5]; 531 532 /* 533 * If there is a FIFO footer in the pipe, first clear 534 * that out. This follows the complex algorithm in the 535 * datasheet that states that you may never leave the 536 * FIFO empty after the first reading: you have to 537 * always leave two footer bytes in it. The footer is 538 * in practice just two zero bytes. 539 */ 540 if (mpu3050->pending_fifo_footer) { 541 toread = bytes_per_datum + 2; 542 offset = 0; 543 } else { 544 toread = bytes_per_datum; 545 offset = 1; 546 /* Put in some dummy value */ 547 fifo_values[0] = cpu_to_be16(0xAAAA); 548 } 549 550 ret = regmap_bulk_read(mpu3050->map, 551 MPU3050_FIFO_R, 552 &fifo_values[offset], 553 toread); 554 if (ret) 555 goto out_trigger_unlock; 556 557 dev_dbg(mpu3050->dev, 558 "%04x %04x %04x %04x %04x\n", 559 fifo_values[0], 560 fifo_values[1], 561 fifo_values[2], 562 fifo_values[3], 563 fifo_values[4]); 564 565 /* Index past the footer (fifo_values[0]) and push */ 566 iio_push_to_buffers_with_timestamp(indio_dev, 567 &fifo_values[1], 568 timestamp); 569 570 fifocnt -= toread; 571 datums_from_fifo++; 572 mpu3050->pending_fifo_footer = true; 573 574 /* 575 * If we're emptying the FIFO, just make sure to 576 * check if something new appeared. 577 */ 578 if (fifocnt < bytes_per_datum) { 579 ret = regmap_bulk_read(mpu3050->map, 580 MPU3050_FIFO_COUNT_H, 581 &raw_fifocnt, 582 sizeof(raw_fifocnt)); 583 if (ret) 584 goto out_trigger_unlock; 585 fifocnt = be16_to_cpu(raw_fifocnt); 586 } 587 588 if (fifocnt < bytes_per_datum) 589 dev_dbg(mpu3050->dev, 590 "%d bytes left in the FIFO\n", 591 fifocnt); 592 593 /* 594 * At this point, the timestamp that triggered the 595 * hardware interrupt is no longer valid for what 596 * we are reading (the interrupt likely fired for 597 * the value on the top of the FIFO), so set the 598 * timestamp to zero and let userspace deal with it. 599 */ 600 timestamp = 0; 601 } 602 } 603 604 /* 605 * If we picked some datums from the FIFO that's enough, else 606 * fall through and just read from the current value registers. 607 * This happens in two cases: 608 * 609 * - We are using some other trigger (external, like an HRTimer) 610 * than the sensor's own sample generator. In this case the 611 * sensor is just set to the max sampling frequency and we give 612 * the trigger a copy of the latest value every time we get here. 613 * 614 * - The hardware trigger is active but unused and we actually use 615 * another trigger which calls here with a frequency higher 616 * than what the device provides data. We will then just read 617 * duplicate values directly from the hardware registers. 618 */ 619 if (datums_from_fifo) { 620 dev_dbg(mpu3050->dev, 621 "read %d datums from the FIFO\n", 622 datums_from_fifo); 623 goto out_trigger_unlock; 624 } 625 626 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values, 627 sizeof(hw_values)); 628 if (ret) { 629 dev_err(mpu3050->dev, 630 "error reading axis data\n"); 631 goto out_trigger_unlock; 632 } 633 634 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp); 635 636 out_trigger_unlock: 637 mutex_unlock(&mpu3050->lock); 638 iio_trigger_notify_done(indio_dev->trig); 639 640 return IRQ_HANDLED; 641 } 642 643 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 644 { 645 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 646 647 pm_runtime_get_sync(mpu3050->dev); 648 649 /* Unless we have OUR trigger active, run at full speed */ 650 if (!mpu3050->hw_irq_trigger) 651 return mpu3050_set_8khz_samplerate(mpu3050); 652 653 return 0; 654 } 655 656 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 657 { 658 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 659 660 pm_runtime_mark_last_busy(mpu3050->dev); 661 pm_runtime_put_autosuspend(mpu3050->dev); 662 663 return 0; 664 } 665 666 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 667 .preenable = mpu3050_buffer_preenable, 668 .postdisable = mpu3050_buffer_postdisable, 669 }; 670 671 static const struct iio_mount_matrix * 672 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 673 const struct iio_chan_spec *chan) 674 { 675 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 676 677 return &mpu3050->orientation; 678 } 679 680 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 681 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 682 { }, 683 }; 684 685 #define MPU3050_AXIS_CHANNEL(axis, index) \ 686 { \ 687 .type = IIO_ANGL_VEL, \ 688 .modified = 1, \ 689 .channel2 = IIO_MOD_##axis, \ 690 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 691 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 692 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 693 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 694 .ext_info = mpu3050_ext_info, \ 695 .scan_index = index, \ 696 .scan_type = { \ 697 .sign = 's', \ 698 .realbits = 16, \ 699 .storagebits = 16, \ 700 .endianness = IIO_BE, \ 701 }, \ 702 } 703 704 static const struct iio_chan_spec mpu3050_channels[] = { 705 { 706 .type = IIO_TEMP, 707 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 708 BIT(IIO_CHAN_INFO_SCALE) | 709 BIT(IIO_CHAN_INFO_OFFSET), 710 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 711 .scan_index = 0, 712 .scan_type = { 713 .sign = 's', 714 .realbits = 16, 715 .storagebits = 16, 716 .endianness = IIO_BE, 717 }, 718 }, 719 MPU3050_AXIS_CHANNEL(X, 1), 720 MPU3050_AXIS_CHANNEL(Y, 2), 721 MPU3050_AXIS_CHANNEL(Z, 3), 722 IIO_CHAN_SOFT_TIMESTAMP(4), 723 }; 724 725 /* Four channels apart from timestamp, scan mask = 0x0f */ 726 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 727 728 /* 729 * These are just the hardcoded factors resulting from the more elaborate 730 * calculations done with fractions in the scale raw get/set functions. 731 */ 732 static IIO_CONST_ATTR(anglevel_scale_available, 733 "0.000122070 " 734 "0.000274658 " 735 "0.000518798 " 736 "0.001068115"); 737 738 static struct attribute *mpu3050_attributes[] = { 739 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 740 NULL, 741 }; 742 743 static const struct attribute_group mpu3050_attribute_group = { 744 .attrs = mpu3050_attributes, 745 }; 746 747 static const struct iio_info mpu3050_info = { 748 .read_raw = mpu3050_read_raw, 749 .write_raw = mpu3050_write_raw, 750 .attrs = &mpu3050_attribute_group, 751 }; 752 753 /** 754 * mpu3050_read_mem() - read MPU-3050 internal memory 755 * @mpu3050: device to read from 756 * @bank: target bank 757 * @addr: target address 758 * @len: number of bytes 759 * @buf: the buffer to store the read bytes in 760 */ 761 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 762 u8 bank, 763 u8 addr, 764 u8 len, 765 u8 *buf) 766 { 767 int ret; 768 769 ret = regmap_write(mpu3050->map, 770 MPU3050_BANK_SEL, 771 bank); 772 if (ret) 773 return ret; 774 775 ret = regmap_write(mpu3050->map, 776 MPU3050_MEM_START_ADDR, 777 addr); 778 if (ret) 779 return ret; 780 781 return regmap_bulk_read(mpu3050->map, 782 MPU3050_MEM_R_W, 783 buf, 784 len); 785 } 786 787 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 788 { 789 int ret; 790 __le64 otp_le; 791 u64 otp; 792 793 /* Reset */ 794 ret = regmap_update_bits(mpu3050->map, 795 MPU3050_PWR_MGM, 796 MPU3050_PWR_MGM_RESET, 797 MPU3050_PWR_MGM_RESET); 798 if (ret) 799 return ret; 800 801 /* Turn on the PLL */ 802 ret = regmap_update_bits(mpu3050->map, 803 MPU3050_PWR_MGM, 804 MPU3050_PWR_MGM_CLKSEL_MASK, 805 MPU3050_PWR_MGM_PLL_Z); 806 if (ret) 807 return ret; 808 809 /* Disable IRQs */ 810 ret = regmap_write(mpu3050->map, 811 MPU3050_INT_CFG, 812 0); 813 if (ret) 814 return ret; 815 816 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 817 ret = mpu3050_read_mem(mpu3050, 818 (MPU3050_MEM_PRFTCH | 819 MPU3050_MEM_USER_BANK | 820 MPU3050_MEM_OTP_BANK_0), 821 0, 822 sizeof(otp_le), 823 (u8 *)&otp_le); 824 if (ret) 825 return ret; 826 827 /* This is device-unique data so it goes into the entropy pool */ 828 add_device_randomness(&otp_le, sizeof(otp_le)); 829 830 otp = le64_to_cpu(otp_le); 831 832 dev_info(mpu3050->dev, 833 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 834 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 835 /* Die ID, bits 0-12 */ 836 FIELD_GET(GENMASK_ULL(12, 0), otp), 837 /* Wafer ID, bits 13-17 */ 838 FIELD_GET(GENMASK_ULL(17, 13), otp), 839 /* A lot ID, bits 18-33 */ 840 FIELD_GET(GENMASK_ULL(33, 18), otp), 841 /* W lot ID, bits 34-45 */ 842 FIELD_GET(GENMASK_ULL(45, 34), otp), 843 /* WP ID, bits 47-49 */ 844 FIELD_GET(GENMASK_ULL(49, 47), otp), 845 /* rev ID, bits 50-55 */ 846 FIELD_GET(GENMASK_ULL(55, 50), otp)); 847 848 return 0; 849 } 850 851 static int mpu3050_power_up(struct mpu3050 *mpu3050) 852 { 853 int ret; 854 855 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 856 if (ret) { 857 dev_err(mpu3050->dev, "cannot enable regulators\n"); 858 return ret; 859 } 860 /* 861 * 20-100 ms start-up time for register read/write according to 862 * the datasheet, be on the safe side and wait 200 ms. 863 */ 864 msleep(200); 865 866 /* Take device out of sleep mode */ 867 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 868 MPU3050_PWR_MGM_SLEEP, 0); 869 if (ret) { 870 dev_err(mpu3050->dev, "error setting power mode\n"); 871 return ret; 872 } 873 usleep_range(10000, 20000); 874 875 return 0; 876 } 877 878 static int mpu3050_power_down(struct mpu3050 *mpu3050) 879 { 880 int ret; 881 882 /* 883 * Put MPU-3050 into sleep mode before cutting regulators. 884 * This is important, because we may not be the sole user 885 * of the regulator so the power may stay on after this, and 886 * then we would be wasting power unless we go to sleep mode 887 * first. 888 */ 889 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 890 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 891 if (ret) 892 dev_err(mpu3050->dev, "error putting to sleep\n"); 893 894 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 895 if (ret) 896 dev_err(mpu3050->dev, "error disabling regulators\n"); 897 898 return 0; 899 } 900 901 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 902 { 903 struct iio_trigger *trig = p; 904 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 905 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 906 907 if (!mpu3050->hw_irq_trigger) 908 return IRQ_NONE; 909 910 /* Get the time stamp as close in time as possible */ 911 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 912 913 return IRQ_WAKE_THREAD; 914 } 915 916 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 917 { 918 struct iio_trigger *trig = p; 919 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 920 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 921 unsigned int val; 922 int ret; 923 924 /* ACK IRQ and check if it was from us */ 925 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 926 if (ret) { 927 dev_err(mpu3050->dev, "error reading IRQ status\n"); 928 return IRQ_HANDLED; 929 } 930 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 931 return IRQ_NONE; 932 933 iio_trigger_poll_chained(p); 934 935 return IRQ_HANDLED; 936 } 937 938 /** 939 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 940 * @trig: trigger instance 941 * @enable: true if trigger should be enabled, false to disable 942 */ 943 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 944 bool enable) 945 { 946 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 947 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 948 unsigned int val; 949 int ret; 950 951 /* Disabling trigger: disable interrupt and return */ 952 if (!enable) { 953 /* Disable all interrupts */ 954 ret = regmap_write(mpu3050->map, 955 MPU3050_INT_CFG, 956 0); 957 if (ret) 958 dev_err(mpu3050->dev, "error disabling IRQ\n"); 959 960 /* Clear IRQ flag */ 961 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 962 if (ret) 963 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 964 965 /* Disable all things in the FIFO and reset it */ 966 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 967 if (ret) 968 dev_err(mpu3050->dev, "error disabling FIFO\n"); 969 970 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 971 MPU3050_USR_CTRL_FIFO_RST); 972 if (ret) 973 dev_err(mpu3050->dev, "error resetting FIFO\n"); 974 975 pm_runtime_mark_last_busy(mpu3050->dev); 976 pm_runtime_put_autosuspend(mpu3050->dev); 977 mpu3050->hw_irq_trigger = false; 978 979 return 0; 980 } else { 981 /* Else we're enabling the trigger from this point */ 982 pm_runtime_get_sync(mpu3050->dev); 983 mpu3050->hw_irq_trigger = true; 984 985 /* Disable all things in the FIFO */ 986 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 987 if (ret) 988 return ret; 989 990 /* Reset and enable the FIFO */ 991 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 992 MPU3050_USR_CTRL_FIFO_EN | 993 MPU3050_USR_CTRL_FIFO_RST, 994 MPU3050_USR_CTRL_FIFO_EN | 995 MPU3050_USR_CTRL_FIFO_RST); 996 if (ret) 997 return ret; 998 999 mpu3050->pending_fifo_footer = false; 1000 1001 /* Turn on the FIFO for temp+X+Y+Z */ 1002 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1003 MPU3050_FIFO_EN_TEMP_OUT | 1004 MPU3050_FIFO_EN_GYRO_XOUT | 1005 MPU3050_FIFO_EN_GYRO_YOUT | 1006 MPU3050_FIFO_EN_GYRO_ZOUT | 1007 MPU3050_FIFO_EN_FOOTER); 1008 if (ret) 1009 return ret; 1010 1011 /* Configure the sample engine */ 1012 ret = mpu3050_start_sampling(mpu3050); 1013 if (ret) 1014 return ret; 1015 1016 /* Clear IRQ flag */ 1017 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1018 if (ret) 1019 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1020 1021 /* Give us interrupts whenever there is new data ready */ 1022 val = MPU3050_INT_RAW_RDY_EN; 1023 1024 if (mpu3050->irq_actl) 1025 val |= MPU3050_INT_ACTL; 1026 if (mpu3050->irq_latch) 1027 val |= MPU3050_INT_LATCH_EN; 1028 if (mpu3050->irq_opendrain) 1029 val |= MPU3050_INT_OPEN; 1030 1031 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1032 if (ret) 1033 return ret; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1040 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1041 }; 1042 1043 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1044 { 1045 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1046 unsigned long irq_trig; 1047 int ret; 1048 1049 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1050 "%s-dev%d", 1051 indio_dev->name, 1052 indio_dev->id); 1053 if (!mpu3050->trig) 1054 return -ENOMEM; 1055 1056 /* Check if IRQ is open drain */ 1057 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain")) 1058 mpu3050->irq_opendrain = true; 1059 1060 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1061 /* 1062 * Configure the interrupt generator hardware to supply whatever 1063 * the interrupt is configured for, edges low/high level low/high, 1064 * we can provide it all. 1065 */ 1066 switch (irq_trig) { 1067 case IRQF_TRIGGER_RISING: 1068 dev_info(&indio_dev->dev, 1069 "pulse interrupts on the rising edge\n"); 1070 break; 1071 case IRQF_TRIGGER_FALLING: 1072 mpu3050->irq_actl = true; 1073 dev_info(&indio_dev->dev, 1074 "pulse interrupts on the falling edge\n"); 1075 break; 1076 case IRQF_TRIGGER_HIGH: 1077 mpu3050->irq_latch = true; 1078 dev_info(&indio_dev->dev, 1079 "interrupts active high level\n"); 1080 /* 1081 * With level IRQs, we mask the IRQ until it is processed, 1082 * but with edge IRQs (pulses) we can queue several interrupts 1083 * in the top half. 1084 */ 1085 irq_trig |= IRQF_ONESHOT; 1086 break; 1087 case IRQF_TRIGGER_LOW: 1088 mpu3050->irq_latch = true; 1089 mpu3050->irq_actl = true; 1090 irq_trig |= IRQF_ONESHOT; 1091 dev_info(&indio_dev->dev, 1092 "interrupts active low level\n"); 1093 break; 1094 default: 1095 /* This is the most preferred mode, if possible */ 1096 dev_err(&indio_dev->dev, 1097 "unsupported IRQ trigger specified (%lx), enforce " 1098 "rising edge\n", irq_trig); 1099 irq_trig = IRQF_TRIGGER_RISING; 1100 break; 1101 } 1102 1103 /* An open drain line can be shared with several devices */ 1104 if (mpu3050->irq_opendrain) 1105 irq_trig |= IRQF_SHARED; 1106 1107 ret = request_threaded_irq(irq, 1108 mpu3050_irq_handler, 1109 mpu3050_irq_thread, 1110 irq_trig, 1111 mpu3050->trig->name, 1112 mpu3050->trig); 1113 if (ret) { 1114 dev_err(mpu3050->dev, 1115 "can't get IRQ %d, error %d\n", irq, ret); 1116 return ret; 1117 } 1118 1119 mpu3050->irq = irq; 1120 mpu3050->trig->dev.parent = mpu3050->dev; 1121 mpu3050->trig->ops = &mpu3050_trigger_ops; 1122 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1123 1124 ret = iio_trigger_register(mpu3050->trig); 1125 if (ret) 1126 return ret; 1127 1128 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1129 1130 return 0; 1131 } 1132 1133 int mpu3050_common_probe(struct device *dev, 1134 struct regmap *map, 1135 int irq, 1136 const char *name) 1137 { 1138 struct iio_dev *indio_dev; 1139 struct mpu3050 *mpu3050; 1140 unsigned int val; 1141 int ret; 1142 1143 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1144 if (!indio_dev) 1145 return -ENOMEM; 1146 mpu3050 = iio_priv(indio_dev); 1147 1148 mpu3050->dev = dev; 1149 mpu3050->map = map; 1150 mutex_init(&mpu3050->lock); 1151 /* Default fullscale: 2000 degrees per second */ 1152 mpu3050->fullscale = FS_2000_DPS; 1153 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1154 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1155 mpu3050->divisor = 99; 1156 1157 /* Read the mounting matrix, if present */ 1158 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation); 1159 if (ret) 1160 return ret; 1161 1162 /* Fetch and turn on regulators */ 1163 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1164 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1165 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1166 mpu3050->regs); 1167 if (ret) { 1168 dev_err(dev, "Cannot get regulators\n"); 1169 return ret; 1170 } 1171 1172 ret = mpu3050_power_up(mpu3050); 1173 if (ret) 1174 return ret; 1175 1176 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1177 if (ret) { 1178 dev_err(dev, "could not read device ID\n"); 1179 ret = -ENODEV; 1180 1181 goto err_power_down; 1182 } 1183 1184 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1185 dev_err(dev, "unsupported chip id %02x\n", 1186 (u8)(val & MPU3050_CHIP_ID_MASK)); 1187 ret = -ENODEV; 1188 goto err_power_down; 1189 } 1190 1191 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1192 if (ret) { 1193 dev_err(dev, "could not read device ID\n"); 1194 ret = -ENODEV; 1195 1196 goto err_power_down; 1197 } 1198 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1199 ((val >> 4) & 0xf), (val & 0xf)); 1200 1201 ret = mpu3050_hw_init(mpu3050); 1202 if (ret) 1203 goto err_power_down; 1204 1205 indio_dev->channels = mpu3050_channels; 1206 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1207 indio_dev->info = &mpu3050_info; 1208 indio_dev->available_scan_masks = mpu3050_scan_masks; 1209 indio_dev->modes = INDIO_DIRECT_MODE; 1210 indio_dev->name = name; 1211 1212 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1213 mpu3050_trigger_handler, 1214 &mpu3050_buffer_setup_ops); 1215 if (ret) { 1216 dev_err(dev, "triggered buffer setup failed\n"); 1217 goto err_power_down; 1218 } 1219 1220 ret = iio_device_register(indio_dev); 1221 if (ret) { 1222 dev_err(dev, "device register failed\n"); 1223 goto err_cleanup_buffer; 1224 } 1225 1226 dev_set_drvdata(dev, indio_dev); 1227 1228 /* Check if we have an assigned IRQ to use as trigger */ 1229 if (irq) { 1230 ret = mpu3050_trigger_probe(indio_dev, irq); 1231 if (ret) 1232 dev_err(dev, "failed to register trigger\n"); 1233 } 1234 1235 /* Enable runtime PM */ 1236 pm_runtime_get_noresume(dev); 1237 pm_runtime_set_active(dev); 1238 pm_runtime_enable(dev); 1239 /* 1240 * Set autosuspend to two orders of magnitude larger than the 1241 * start-up time. 100ms start-up time means 10000ms autosuspend, 1242 * i.e. 10 seconds. 1243 */ 1244 pm_runtime_set_autosuspend_delay(dev, 10000); 1245 pm_runtime_use_autosuspend(dev); 1246 pm_runtime_put(dev); 1247 1248 return 0; 1249 1250 err_cleanup_buffer: 1251 iio_triggered_buffer_cleanup(indio_dev); 1252 err_power_down: 1253 mpu3050_power_down(mpu3050); 1254 1255 return ret; 1256 } 1257 EXPORT_SYMBOL(mpu3050_common_probe); 1258 1259 int mpu3050_common_remove(struct device *dev) 1260 { 1261 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1262 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1263 1264 pm_runtime_get_sync(dev); 1265 pm_runtime_put_noidle(dev); 1266 pm_runtime_disable(dev); 1267 iio_triggered_buffer_cleanup(indio_dev); 1268 if (mpu3050->irq) 1269 free_irq(mpu3050->irq, mpu3050); 1270 iio_device_unregister(indio_dev); 1271 mpu3050_power_down(mpu3050); 1272 1273 return 0; 1274 } 1275 EXPORT_SYMBOL(mpu3050_common_remove); 1276 1277 #ifdef CONFIG_PM 1278 static int mpu3050_runtime_suspend(struct device *dev) 1279 { 1280 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1281 } 1282 1283 static int mpu3050_runtime_resume(struct device *dev) 1284 { 1285 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1286 } 1287 #endif /* CONFIG_PM */ 1288 1289 const struct dev_pm_ops mpu3050_dev_pm_ops = { 1290 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1291 pm_runtime_force_resume) 1292 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, 1293 mpu3050_runtime_resume, NULL) 1294 }; 1295 EXPORT_SYMBOL(mpu3050_dev_pm_ops); 1296 1297 MODULE_AUTHOR("Linus Walleij"); 1298 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1299 MODULE_LICENSE("GPL"); 1300