1 /* 2 * MPU3050 gyroscope driver 3 * 4 * Copyright (C) 2016 Linaro Ltd. 5 * Author: Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 8 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 9 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 10 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 11 * 12 * TODO: add support for setting up the low pass 3dB frequency. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/interrupt.h> 25 #include <linux/module.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/random.h> 28 #include <linux/slab.h> 29 30 #include "mpu3050.h" 31 32 #define MPU3050_CHIP_ID 0x68 33 #define MPU3050_CHIP_ID_MASK 0x7E 34 35 /* 36 * Register map: anything suffixed *_H is a big-endian high byte and always 37 * followed by the corresponding low byte (*_L) even though these are not 38 * explicitly included in the register definitions. 39 */ 40 #define MPU3050_CHIP_ID_REG 0x00 41 #define MPU3050_PRODUCT_ID_REG 0x01 42 #define MPU3050_XG_OFFS_TC 0x05 43 #define MPU3050_YG_OFFS_TC 0x08 44 #define MPU3050_ZG_OFFS_TC 0x0B 45 #define MPU3050_X_OFFS_USR_H 0x0C 46 #define MPU3050_Y_OFFS_USR_H 0x0E 47 #define MPU3050_Z_OFFS_USR_H 0x10 48 #define MPU3050_FIFO_EN 0x12 49 #define MPU3050_AUX_VDDIO 0x13 50 #define MPU3050_SLV_ADDR 0x14 51 #define MPU3050_SMPLRT_DIV 0x15 52 #define MPU3050_DLPF_FS_SYNC 0x16 53 #define MPU3050_INT_CFG 0x17 54 #define MPU3050_AUX_ADDR 0x18 55 #define MPU3050_INT_STATUS 0x1A 56 #define MPU3050_TEMP_H 0x1B 57 #define MPU3050_XOUT_H 0x1D 58 #define MPU3050_YOUT_H 0x1F 59 #define MPU3050_ZOUT_H 0x21 60 #define MPU3050_DMP_CFG1 0x35 61 #define MPU3050_DMP_CFG2 0x36 62 #define MPU3050_BANK_SEL 0x37 63 #define MPU3050_MEM_START_ADDR 0x38 64 #define MPU3050_MEM_R_W 0x39 65 #define MPU3050_FIFO_COUNT_H 0x3A 66 #define MPU3050_FIFO_R 0x3C 67 #define MPU3050_USR_CTRL 0x3D 68 #define MPU3050_PWR_MGM 0x3E 69 70 /* MPU memory bank read options */ 71 #define MPU3050_MEM_PRFTCH BIT(5) 72 #define MPU3050_MEM_USER_BANK BIT(4) 73 /* Bits 8-11 select memory bank */ 74 #define MPU3050_MEM_RAM_BANK_0 0 75 #define MPU3050_MEM_RAM_BANK_1 1 76 #define MPU3050_MEM_RAM_BANK_2 2 77 #define MPU3050_MEM_RAM_BANK_3 3 78 #define MPU3050_MEM_OTP_BANK_0 4 79 80 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 81 82 /* Register bits */ 83 84 /* FIFO Enable */ 85 #define MPU3050_FIFO_EN_FOOTER BIT(0) 86 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 87 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 88 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 89 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 90 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 91 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 92 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 93 94 /* 95 * Digital Low Pass filter (DLPF) 96 * Full Scale (FS) 97 * and Synchronization 98 */ 99 #define MPU3050_EXT_SYNC_NONE 0x00 100 #define MPU3050_EXT_SYNC_TEMP 0x20 101 #define MPU3050_EXT_SYNC_GYROX 0x40 102 #define MPU3050_EXT_SYNC_GYROY 0x60 103 #define MPU3050_EXT_SYNC_GYROZ 0x80 104 #define MPU3050_EXT_SYNC_ACCELX 0xA0 105 #define MPU3050_EXT_SYNC_ACCELY 0xC0 106 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 107 #define MPU3050_EXT_SYNC_MASK 0xE0 108 #define MPU3050_EXT_SYNC_SHIFT 5 109 110 #define MPU3050_FS_250DPS 0x00 111 #define MPU3050_FS_500DPS 0x08 112 #define MPU3050_FS_1000DPS 0x10 113 #define MPU3050_FS_2000DPS 0x18 114 #define MPU3050_FS_MASK 0x18 115 #define MPU3050_FS_SHIFT 3 116 117 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 118 #define MPU3050_DLPF_CFG_188HZ 0x01 119 #define MPU3050_DLPF_CFG_98HZ 0x02 120 #define MPU3050_DLPF_CFG_42HZ 0x03 121 #define MPU3050_DLPF_CFG_20HZ 0x04 122 #define MPU3050_DLPF_CFG_10HZ 0x05 123 #define MPU3050_DLPF_CFG_5HZ 0x06 124 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 125 #define MPU3050_DLPF_CFG_MASK 0x07 126 #define MPU3050_DLPF_CFG_SHIFT 0 127 128 /* Interrupt config */ 129 #define MPU3050_INT_RAW_RDY_EN BIT(0) 130 #define MPU3050_INT_DMP_DONE_EN BIT(1) 131 #define MPU3050_INT_MPU_RDY_EN BIT(2) 132 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 133 #define MPU3050_INT_LATCH_EN BIT(5) 134 #define MPU3050_INT_OPEN BIT(6) 135 #define MPU3050_INT_ACTL BIT(7) 136 /* Interrupt status */ 137 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 138 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 139 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 140 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 141 /* USR_CTRL */ 142 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 143 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 144 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 145 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 146 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 147 /* PWR_MGM */ 148 #define MPU3050_PWR_MGM_PLL_X 0x01 149 #define MPU3050_PWR_MGM_PLL_Y 0x02 150 #define MPU3050_PWR_MGM_PLL_Z 0x03 151 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 152 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 153 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 154 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 155 #define MPU3050_PWR_MGM_SLEEP BIT(6) 156 #define MPU3050_PWR_MGM_RESET BIT(7) 157 #define MPU3050_PWR_MGM_MASK 0xff 158 159 /* 160 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 161 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 162 * in two's complement. 163 */ 164 static unsigned int mpu3050_fs_precision[] = { 165 IIO_DEGREE_TO_RAD(250), 166 IIO_DEGREE_TO_RAD(500), 167 IIO_DEGREE_TO_RAD(1000), 168 IIO_DEGREE_TO_RAD(2000) 169 }; 170 171 /* 172 * Regulator names 173 */ 174 static const char mpu3050_reg_vdd[] = "vdd"; 175 static const char mpu3050_reg_vlogic[] = "vlogic"; 176 177 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 178 { 179 unsigned int freq; 180 181 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 182 freq = 8000; 183 else 184 freq = 1000; 185 freq /= (mpu3050->divisor + 1); 186 187 return freq; 188 } 189 190 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 191 { 192 __be16 raw_val[3]; 193 int ret; 194 int i; 195 196 /* Reset */ 197 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 198 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 199 if (ret) 200 return ret; 201 202 /* Turn on the Z-axis PLL */ 203 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 204 MPU3050_PWR_MGM_CLKSEL_MASK, 205 MPU3050_PWR_MGM_PLL_Z); 206 if (ret) 207 return ret; 208 209 /* Write calibration offset registers */ 210 for (i = 0; i < 3; i++) 211 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 212 213 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 214 sizeof(raw_val)); 215 if (ret) 216 return ret; 217 218 /* Set low pass filter (sample rate), sync and full scale */ 219 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 220 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 221 mpu3050->fullscale << MPU3050_FS_SHIFT | 222 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 223 if (ret) 224 return ret; 225 226 /* Set up sampling frequency */ 227 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 228 if (ret) 229 return ret; 230 231 /* 232 * Max 50 ms start-up time after setting DLPF_FS_SYNC 233 * according to the data sheet, then wait for the next sample 234 * at this frequency T = 1000/f ms. 235 */ 236 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 237 238 return 0; 239 } 240 241 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 242 { 243 int ret; 244 u8 divisor; 245 enum mpu3050_lpf lpf; 246 247 lpf = mpu3050->lpf; 248 divisor = mpu3050->divisor; 249 250 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 251 mpu3050->divisor = 0; /* Divide by 1 */ 252 ret = mpu3050_start_sampling(mpu3050); 253 254 mpu3050->lpf = lpf; 255 mpu3050->divisor = divisor; 256 257 return ret; 258 } 259 260 static int mpu3050_read_raw(struct iio_dev *indio_dev, 261 struct iio_chan_spec const *chan, 262 int *val, int *val2, 263 long mask) 264 { 265 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 266 int ret; 267 __be16 raw_val; 268 269 switch (mask) { 270 case IIO_CHAN_INFO_OFFSET: 271 switch (chan->type) { 272 case IIO_TEMP: 273 /* The temperature scaling is (x+23000)/280 Celsius */ 274 *val = 23000; 275 return IIO_VAL_INT; 276 default: 277 return -EINVAL; 278 } 279 case IIO_CHAN_INFO_CALIBBIAS: 280 switch (chan->type) { 281 case IIO_ANGL_VEL: 282 *val = mpu3050->calibration[chan->scan_index-1]; 283 return IIO_VAL_INT; 284 default: 285 return -EINVAL; 286 } 287 case IIO_CHAN_INFO_SAMP_FREQ: 288 *val = mpu3050_get_freq(mpu3050); 289 return IIO_VAL_INT; 290 case IIO_CHAN_INFO_SCALE: 291 switch (chan->type) { 292 case IIO_TEMP: 293 /* Millidegrees, see about temperature scaling above */ 294 *val = 1000; 295 *val2 = 280; 296 return IIO_VAL_FRACTIONAL; 297 case IIO_ANGL_VEL: 298 /* 299 * Convert to the corresponding full scale in 300 * radians. All 16 bits are used with sign to 301 * span the available scale: to account for the one 302 * missing value if we multiply by 1/S16_MAX, instead 303 * multiply with 2/U16_MAX. 304 */ 305 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 306 *val2 = U16_MAX; 307 return IIO_VAL_FRACTIONAL; 308 default: 309 return -EINVAL; 310 } 311 case IIO_CHAN_INFO_RAW: 312 /* Resume device */ 313 pm_runtime_get_sync(mpu3050->dev); 314 mutex_lock(&mpu3050->lock); 315 316 ret = mpu3050_set_8khz_samplerate(mpu3050); 317 if (ret) 318 goto out_read_raw_unlock; 319 320 switch (chan->type) { 321 case IIO_TEMP: 322 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 323 &raw_val, sizeof(raw_val)); 324 if (ret) { 325 dev_err(mpu3050->dev, 326 "error reading temperature\n"); 327 goto out_read_raw_unlock; 328 } 329 330 *val = be16_to_cpu(raw_val); 331 ret = IIO_VAL_INT; 332 333 goto out_read_raw_unlock; 334 case IIO_ANGL_VEL: 335 ret = regmap_bulk_read(mpu3050->map, 336 MPU3050_AXIS_REGS(chan->scan_index-1), 337 &raw_val, 338 sizeof(raw_val)); 339 if (ret) { 340 dev_err(mpu3050->dev, 341 "error reading axis data\n"); 342 goto out_read_raw_unlock; 343 } 344 345 *val = be16_to_cpu(raw_val); 346 ret = IIO_VAL_INT; 347 348 goto out_read_raw_unlock; 349 default: 350 ret = -EINVAL; 351 goto out_read_raw_unlock; 352 } 353 default: 354 break; 355 } 356 357 return -EINVAL; 358 359 out_read_raw_unlock: 360 mutex_unlock(&mpu3050->lock); 361 pm_runtime_mark_last_busy(mpu3050->dev); 362 pm_runtime_put_autosuspend(mpu3050->dev); 363 364 return ret; 365 } 366 367 static int mpu3050_write_raw(struct iio_dev *indio_dev, 368 const struct iio_chan_spec *chan, 369 int val, int val2, long mask) 370 { 371 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 372 /* 373 * Couldn't figure out a way to precalculate these at compile time. 374 */ 375 unsigned int fs250 = 376 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 377 U16_MAX); 378 unsigned int fs500 = 379 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 380 U16_MAX); 381 unsigned int fs1000 = 382 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 383 U16_MAX); 384 unsigned int fs2000 = 385 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 386 U16_MAX); 387 388 switch (mask) { 389 case IIO_CHAN_INFO_CALIBBIAS: 390 if (chan->type != IIO_ANGL_VEL) 391 return -EINVAL; 392 mpu3050->calibration[chan->scan_index-1] = val; 393 return 0; 394 case IIO_CHAN_INFO_SAMP_FREQ: 395 /* 396 * The max samplerate is 8000 Hz, the minimum 397 * 1000 / 256 ~= 4 Hz 398 */ 399 if (val < 4 || val > 8000) 400 return -EINVAL; 401 402 /* 403 * Above 1000 Hz we must turn off the digital low pass filter 404 * so we get a base frequency of 8kHz to the divider 405 */ 406 if (val > 1000) { 407 mpu3050->lpf = LPF_256_HZ_NOLPF; 408 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 409 return 0; 410 } 411 412 mpu3050->lpf = LPF_188_HZ; 413 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 414 return 0; 415 case IIO_CHAN_INFO_SCALE: 416 if (chan->type != IIO_ANGL_VEL) 417 return -EINVAL; 418 /* 419 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 420 * which means we need to round to the closest radians 421 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 422 * rad/s. The scale is then for the 16 bits used to cover 423 * it 2/(2^16) of that. 424 */ 425 426 /* Just too large, set the max range */ 427 if (val != 0) { 428 mpu3050->fullscale = FS_2000_DPS; 429 return 0; 430 } 431 432 /* 433 * Now we're dealing with fractions below zero in millirad/s 434 * do some integer interpolation and match with the closest 435 * fullscale in the table. 436 */ 437 if (val2 <= fs250 || 438 val2 < ((fs500 + fs250) / 2)) 439 mpu3050->fullscale = FS_250_DPS; 440 else if (val2 <= fs500 || 441 val2 < ((fs1000 + fs500) / 2)) 442 mpu3050->fullscale = FS_500_DPS; 443 else if (val2 <= fs1000 || 444 val2 < ((fs2000 + fs1000) / 2)) 445 mpu3050->fullscale = FS_1000_DPS; 446 else 447 /* Catch-all */ 448 mpu3050->fullscale = FS_2000_DPS; 449 return 0; 450 default: 451 break; 452 } 453 454 return -EINVAL; 455 } 456 457 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 458 { 459 const struct iio_poll_func *pf = p; 460 struct iio_dev *indio_dev = pf->indio_dev; 461 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 462 int ret; 463 /* 464 * Temperature 1*16 bits 465 * Three axes 3*16 bits 466 * Timestamp 64 bits (4*16 bits) 467 * Sum total 8*16 bits 468 */ 469 __be16 hw_values[8]; 470 s64 timestamp; 471 unsigned int datums_from_fifo = 0; 472 473 /* 474 * If we're using the hardware trigger, get the precise timestamp from 475 * the top half of the threaded IRQ handler. Otherwise get the 476 * timestamp here so it will be close in time to the actual values 477 * read from the registers. 478 */ 479 if (iio_trigger_using_own(indio_dev)) 480 timestamp = mpu3050->hw_timestamp; 481 else 482 timestamp = iio_get_time_ns(indio_dev); 483 484 mutex_lock(&mpu3050->lock); 485 486 /* Using the hardware IRQ trigger? Check the buffer then. */ 487 if (mpu3050->hw_irq_trigger) { 488 __be16 raw_fifocnt; 489 u16 fifocnt; 490 /* X, Y, Z + temperature */ 491 unsigned int bytes_per_datum = 8; 492 bool fifo_overflow = false; 493 494 ret = regmap_bulk_read(mpu3050->map, 495 MPU3050_FIFO_COUNT_H, 496 &raw_fifocnt, 497 sizeof(raw_fifocnt)); 498 if (ret) 499 goto out_trigger_unlock; 500 fifocnt = be16_to_cpu(raw_fifocnt); 501 502 if (fifocnt == 512) { 503 dev_info(mpu3050->dev, 504 "FIFO overflow! Emptying and resetting FIFO\n"); 505 fifo_overflow = true; 506 /* Reset and enable the FIFO */ 507 ret = regmap_update_bits(mpu3050->map, 508 MPU3050_USR_CTRL, 509 MPU3050_USR_CTRL_FIFO_EN | 510 MPU3050_USR_CTRL_FIFO_RST, 511 MPU3050_USR_CTRL_FIFO_EN | 512 MPU3050_USR_CTRL_FIFO_RST); 513 if (ret) { 514 dev_info(mpu3050->dev, "error resetting FIFO\n"); 515 goto out_trigger_unlock; 516 } 517 mpu3050->pending_fifo_footer = false; 518 } 519 520 if (fifocnt) 521 dev_dbg(mpu3050->dev, 522 "%d bytes in the FIFO\n", 523 fifocnt); 524 525 while (!fifo_overflow && fifocnt > bytes_per_datum) { 526 unsigned int toread; 527 unsigned int offset; 528 __be16 fifo_values[5]; 529 530 /* 531 * If there is a FIFO footer in the pipe, first clear 532 * that out. This follows the complex algorithm in the 533 * datasheet that states that you may never leave the 534 * FIFO empty after the first reading: you have to 535 * always leave two footer bytes in it. The footer is 536 * in practice just two zero bytes. 537 */ 538 if (mpu3050->pending_fifo_footer) { 539 toread = bytes_per_datum + 2; 540 offset = 0; 541 } else { 542 toread = bytes_per_datum; 543 offset = 1; 544 /* Put in some dummy value */ 545 fifo_values[0] = 0xAAAA; 546 } 547 548 ret = regmap_bulk_read(mpu3050->map, 549 MPU3050_FIFO_R, 550 &fifo_values[offset], 551 toread); 552 553 dev_dbg(mpu3050->dev, 554 "%04x %04x %04x %04x %04x\n", 555 fifo_values[0], 556 fifo_values[1], 557 fifo_values[2], 558 fifo_values[3], 559 fifo_values[4]); 560 561 /* Index past the footer (fifo_values[0]) and push */ 562 iio_push_to_buffers_with_timestamp(indio_dev, 563 &fifo_values[1], 564 timestamp); 565 566 fifocnt -= toread; 567 datums_from_fifo++; 568 mpu3050->pending_fifo_footer = true; 569 570 /* 571 * If we're emptying the FIFO, just make sure to 572 * check if something new appeared. 573 */ 574 if (fifocnt < bytes_per_datum) { 575 ret = regmap_bulk_read(mpu3050->map, 576 MPU3050_FIFO_COUNT_H, 577 &raw_fifocnt, 578 sizeof(raw_fifocnt)); 579 if (ret) 580 goto out_trigger_unlock; 581 fifocnt = be16_to_cpu(raw_fifocnt); 582 } 583 584 if (fifocnt < bytes_per_datum) 585 dev_dbg(mpu3050->dev, 586 "%d bytes left in the FIFO\n", 587 fifocnt); 588 589 /* 590 * At this point, the timestamp that triggered the 591 * hardware interrupt is no longer valid for what 592 * we are reading (the interrupt likely fired for 593 * the value on the top of the FIFO), so set the 594 * timestamp to zero and let userspace deal with it. 595 */ 596 timestamp = 0; 597 } 598 } 599 600 /* 601 * If we picked some datums from the FIFO that's enough, else 602 * fall through and just read from the current value registers. 603 * This happens in two cases: 604 * 605 * - We are using some other trigger (external, like an HRTimer) 606 * than the sensor's own sample generator. In this case the 607 * sensor is just set to the max sampling frequency and we give 608 * the trigger a copy of the latest value every time we get here. 609 * 610 * - The hardware trigger is active but unused and we actually use 611 * another trigger which calls here with a frequency higher 612 * than what the device provides data. We will then just read 613 * duplicate values directly from the hardware registers. 614 */ 615 if (datums_from_fifo) { 616 dev_dbg(mpu3050->dev, 617 "read %d datums from the FIFO\n", 618 datums_from_fifo); 619 goto out_trigger_unlock; 620 } 621 622 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values, 623 sizeof(hw_values)); 624 if (ret) { 625 dev_err(mpu3050->dev, 626 "error reading axis data\n"); 627 goto out_trigger_unlock; 628 } 629 630 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp); 631 632 out_trigger_unlock: 633 mutex_unlock(&mpu3050->lock); 634 iio_trigger_notify_done(indio_dev->trig); 635 636 return IRQ_HANDLED; 637 } 638 639 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 640 { 641 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 642 643 pm_runtime_get_sync(mpu3050->dev); 644 645 /* Unless we have OUR trigger active, run at full speed */ 646 if (!mpu3050->hw_irq_trigger) 647 return mpu3050_set_8khz_samplerate(mpu3050); 648 649 return 0; 650 } 651 652 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 653 { 654 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 655 656 pm_runtime_mark_last_busy(mpu3050->dev); 657 pm_runtime_put_autosuspend(mpu3050->dev); 658 659 return 0; 660 } 661 662 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 663 .preenable = mpu3050_buffer_preenable, 664 .postenable = iio_triggered_buffer_postenable, 665 .predisable = iio_triggered_buffer_predisable, 666 .postdisable = mpu3050_buffer_postdisable, 667 }; 668 669 static const struct iio_mount_matrix * 670 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 671 const struct iio_chan_spec *chan) 672 { 673 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 674 675 return &mpu3050->orientation; 676 } 677 678 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 679 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 680 { }, 681 }; 682 683 #define MPU3050_AXIS_CHANNEL(axis, index) \ 684 { \ 685 .type = IIO_ANGL_VEL, \ 686 .modified = 1, \ 687 .channel2 = IIO_MOD_##axis, \ 688 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 689 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 690 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 691 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 692 .ext_info = mpu3050_ext_info, \ 693 .scan_index = index, \ 694 .scan_type = { \ 695 .sign = 's', \ 696 .realbits = 16, \ 697 .storagebits = 16, \ 698 .endianness = IIO_BE, \ 699 }, \ 700 } 701 702 static const struct iio_chan_spec mpu3050_channels[] = { 703 { 704 .type = IIO_TEMP, 705 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 706 BIT(IIO_CHAN_INFO_SCALE) | 707 BIT(IIO_CHAN_INFO_OFFSET), 708 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 709 .scan_index = 0, 710 .scan_type = { 711 .sign = 's', 712 .realbits = 16, 713 .storagebits = 16, 714 .endianness = IIO_BE, 715 }, 716 }, 717 MPU3050_AXIS_CHANNEL(X, 1), 718 MPU3050_AXIS_CHANNEL(Y, 2), 719 MPU3050_AXIS_CHANNEL(Z, 3), 720 IIO_CHAN_SOFT_TIMESTAMP(4), 721 }; 722 723 /* Four channels apart from timestamp, scan mask = 0x0f */ 724 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 725 726 /* 727 * These are just the hardcoded factors resulting from the more elaborate 728 * calculations done with fractions in the scale raw get/set functions. 729 */ 730 static IIO_CONST_ATTR(anglevel_scale_available, 731 "0.000122070 " 732 "0.000274658 " 733 "0.000518798 " 734 "0.001068115"); 735 736 static struct attribute *mpu3050_attributes[] = { 737 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 738 NULL, 739 }; 740 741 static const struct attribute_group mpu3050_attribute_group = { 742 .attrs = mpu3050_attributes, 743 }; 744 745 static const struct iio_info mpu3050_info = { 746 .read_raw = mpu3050_read_raw, 747 .write_raw = mpu3050_write_raw, 748 .attrs = &mpu3050_attribute_group, 749 }; 750 751 /** 752 * mpu3050_read_mem() - read MPU-3050 internal memory 753 * @mpu3050: device to read from 754 * @bank: target bank 755 * @addr: target address 756 * @len: number of bytes 757 * @buf: the buffer to store the read bytes in 758 */ 759 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 760 u8 bank, 761 u8 addr, 762 u8 len, 763 u8 *buf) 764 { 765 int ret; 766 767 ret = regmap_write(mpu3050->map, 768 MPU3050_BANK_SEL, 769 bank); 770 if (ret) 771 return ret; 772 773 ret = regmap_write(mpu3050->map, 774 MPU3050_MEM_START_ADDR, 775 addr); 776 if (ret) 777 return ret; 778 779 return regmap_bulk_read(mpu3050->map, 780 MPU3050_MEM_R_W, 781 buf, 782 len); 783 } 784 785 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 786 { 787 int ret; 788 u8 otp[8]; 789 790 /* Reset */ 791 ret = regmap_update_bits(mpu3050->map, 792 MPU3050_PWR_MGM, 793 MPU3050_PWR_MGM_RESET, 794 MPU3050_PWR_MGM_RESET); 795 if (ret) 796 return ret; 797 798 /* Turn on the PLL */ 799 ret = regmap_update_bits(mpu3050->map, 800 MPU3050_PWR_MGM, 801 MPU3050_PWR_MGM_CLKSEL_MASK, 802 MPU3050_PWR_MGM_PLL_Z); 803 if (ret) 804 return ret; 805 806 /* Disable IRQs */ 807 ret = regmap_write(mpu3050->map, 808 MPU3050_INT_CFG, 809 0); 810 if (ret) 811 return ret; 812 813 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 814 ret = mpu3050_read_mem(mpu3050, 815 (MPU3050_MEM_PRFTCH | 816 MPU3050_MEM_USER_BANK | 817 MPU3050_MEM_OTP_BANK_0), 818 0, 819 sizeof(otp), 820 otp); 821 if (ret) 822 return ret; 823 824 /* This is device-unique data so it goes into the entropy pool */ 825 add_device_randomness(otp, sizeof(otp)); 826 827 dev_info(mpu3050->dev, 828 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, " 829 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n", 830 /* Die ID, bits 0-12 */ 831 (otp[1] << 8 | otp[0]) & 0x1fff, 832 /* Wafer ID, bits 13-17 */ 833 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5, 834 /* A lot ID, bits 18-33 */ 835 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2, 836 /* W lot ID, bits 34-45 */ 837 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2, 838 /* WP ID, bits 47-49 */ 839 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7, 840 /* rev ID, bits 50-55 */ 841 otp[6] >> 2); 842 843 return 0; 844 } 845 846 static int mpu3050_power_up(struct mpu3050 *mpu3050) 847 { 848 int ret; 849 850 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 851 if (ret) { 852 dev_err(mpu3050->dev, "cannot enable regulators\n"); 853 return ret; 854 } 855 /* 856 * 20-100 ms start-up time for register read/write according to 857 * the datasheet, be on the safe side and wait 200 ms. 858 */ 859 msleep(200); 860 861 /* Take device out of sleep mode */ 862 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 863 MPU3050_PWR_MGM_SLEEP, 0); 864 if (ret) { 865 dev_err(mpu3050->dev, "error setting power mode\n"); 866 return ret; 867 } 868 usleep_range(10000, 20000); 869 870 return 0; 871 } 872 873 static int mpu3050_power_down(struct mpu3050 *mpu3050) 874 { 875 int ret; 876 877 /* 878 * Put MPU-3050 into sleep mode before cutting regulators. 879 * This is important, because we may not be the sole user 880 * of the regulator so the power may stay on after this, and 881 * then we would be wasting power unless we go to sleep mode 882 * first. 883 */ 884 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 885 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 886 if (ret) 887 dev_err(mpu3050->dev, "error putting to sleep\n"); 888 889 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 890 if (ret) 891 dev_err(mpu3050->dev, "error disabling regulators\n"); 892 893 return 0; 894 } 895 896 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 897 { 898 struct iio_trigger *trig = p; 899 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 900 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 901 902 if (!mpu3050->hw_irq_trigger) 903 return IRQ_NONE; 904 905 /* Get the time stamp as close in time as possible */ 906 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 907 908 return IRQ_WAKE_THREAD; 909 } 910 911 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 912 { 913 struct iio_trigger *trig = p; 914 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 915 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 916 unsigned int val; 917 int ret; 918 919 /* ACK IRQ and check if it was from us */ 920 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 921 if (ret) { 922 dev_err(mpu3050->dev, "error reading IRQ status\n"); 923 return IRQ_HANDLED; 924 } 925 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 926 return IRQ_NONE; 927 928 iio_trigger_poll_chained(p); 929 930 return IRQ_HANDLED; 931 } 932 933 /** 934 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 935 * @trig: trigger instance 936 * @enable: true if trigger should be enabled, false to disable 937 */ 938 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 939 bool enable) 940 { 941 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 942 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 943 unsigned int val; 944 int ret; 945 946 /* Disabling trigger: disable interrupt and return */ 947 if (!enable) { 948 /* Disable all interrupts */ 949 ret = regmap_write(mpu3050->map, 950 MPU3050_INT_CFG, 951 0); 952 if (ret) 953 dev_err(mpu3050->dev, "error disabling IRQ\n"); 954 955 /* Clear IRQ flag */ 956 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 957 if (ret) 958 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 959 960 /* Disable all things in the FIFO and reset it */ 961 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 962 if (ret) 963 dev_err(mpu3050->dev, "error disabling FIFO\n"); 964 965 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 966 MPU3050_USR_CTRL_FIFO_RST); 967 if (ret) 968 dev_err(mpu3050->dev, "error resetting FIFO\n"); 969 970 pm_runtime_mark_last_busy(mpu3050->dev); 971 pm_runtime_put_autosuspend(mpu3050->dev); 972 mpu3050->hw_irq_trigger = false; 973 974 return 0; 975 } else { 976 /* Else we're enabling the trigger from this point */ 977 pm_runtime_get_sync(mpu3050->dev); 978 mpu3050->hw_irq_trigger = true; 979 980 /* Disable all things in the FIFO */ 981 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 982 if (ret) 983 return ret; 984 985 /* Reset and enable the FIFO */ 986 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 987 MPU3050_USR_CTRL_FIFO_EN | 988 MPU3050_USR_CTRL_FIFO_RST, 989 MPU3050_USR_CTRL_FIFO_EN | 990 MPU3050_USR_CTRL_FIFO_RST); 991 if (ret) 992 return ret; 993 994 mpu3050->pending_fifo_footer = false; 995 996 /* Turn on the FIFO for temp+X+Y+Z */ 997 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 998 MPU3050_FIFO_EN_TEMP_OUT | 999 MPU3050_FIFO_EN_GYRO_XOUT | 1000 MPU3050_FIFO_EN_GYRO_YOUT | 1001 MPU3050_FIFO_EN_GYRO_ZOUT | 1002 MPU3050_FIFO_EN_FOOTER); 1003 if (ret) 1004 return ret; 1005 1006 /* Configure the sample engine */ 1007 ret = mpu3050_start_sampling(mpu3050); 1008 if (ret) 1009 return ret; 1010 1011 /* Clear IRQ flag */ 1012 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1013 if (ret) 1014 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1015 1016 /* Give us interrupts whenever there is new data ready */ 1017 val = MPU3050_INT_RAW_RDY_EN; 1018 1019 if (mpu3050->irq_actl) 1020 val |= MPU3050_INT_ACTL; 1021 if (mpu3050->irq_latch) 1022 val |= MPU3050_INT_LATCH_EN; 1023 if (mpu3050->irq_opendrain) 1024 val |= MPU3050_INT_OPEN; 1025 1026 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1027 if (ret) 1028 return ret; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1035 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1036 }; 1037 1038 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1039 { 1040 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1041 unsigned long irq_trig; 1042 int ret; 1043 1044 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1045 "%s-dev%d", 1046 indio_dev->name, 1047 indio_dev->id); 1048 if (!mpu3050->trig) 1049 return -ENOMEM; 1050 1051 /* Check if IRQ is open drain */ 1052 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain")) 1053 mpu3050->irq_opendrain = true; 1054 1055 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1056 /* 1057 * Configure the interrupt generator hardware to supply whatever 1058 * the interrupt is configured for, edges low/high level low/high, 1059 * we can provide it all. 1060 */ 1061 switch (irq_trig) { 1062 case IRQF_TRIGGER_RISING: 1063 dev_info(&indio_dev->dev, 1064 "pulse interrupts on the rising edge\n"); 1065 break; 1066 case IRQF_TRIGGER_FALLING: 1067 mpu3050->irq_actl = true; 1068 dev_info(&indio_dev->dev, 1069 "pulse interrupts on the falling edge\n"); 1070 break; 1071 case IRQF_TRIGGER_HIGH: 1072 mpu3050->irq_latch = true; 1073 dev_info(&indio_dev->dev, 1074 "interrupts active high level\n"); 1075 /* 1076 * With level IRQs, we mask the IRQ until it is processed, 1077 * but with edge IRQs (pulses) we can queue several interrupts 1078 * in the top half. 1079 */ 1080 irq_trig |= IRQF_ONESHOT; 1081 break; 1082 case IRQF_TRIGGER_LOW: 1083 mpu3050->irq_latch = true; 1084 mpu3050->irq_actl = true; 1085 irq_trig |= IRQF_ONESHOT; 1086 dev_info(&indio_dev->dev, 1087 "interrupts active low level\n"); 1088 break; 1089 default: 1090 /* This is the most preferred mode, if possible */ 1091 dev_err(&indio_dev->dev, 1092 "unsupported IRQ trigger specified (%lx), enforce " 1093 "rising edge\n", irq_trig); 1094 irq_trig = IRQF_TRIGGER_RISING; 1095 break; 1096 } 1097 1098 /* An open drain line can be shared with several devices */ 1099 if (mpu3050->irq_opendrain) 1100 irq_trig |= IRQF_SHARED; 1101 1102 ret = request_threaded_irq(irq, 1103 mpu3050_irq_handler, 1104 mpu3050_irq_thread, 1105 irq_trig, 1106 mpu3050->trig->name, 1107 mpu3050->trig); 1108 if (ret) { 1109 dev_err(mpu3050->dev, 1110 "can't get IRQ %d, error %d\n", irq, ret); 1111 return ret; 1112 } 1113 1114 mpu3050->irq = irq; 1115 mpu3050->trig->dev.parent = mpu3050->dev; 1116 mpu3050->trig->ops = &mpu3050_trigger_ops; 1117 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1118 1119 ret = iio_trigger_register(mpu3050->trig); 1120 if (ret) 1121 return ret; 1122 1123 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1124 1125 return 0; 1126 } 1127 1128 int mpu3050_common_probe(struct device *dev, 1129 struct regmap *map, 1130 int irq, 1131 const char *name) 1132 { 1133 struct iio_dev *indio_dev; 1134 struct mpu3050 *mpu3050; 1135 unsigned int val; 1136 int ret; 1137 1138 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1139 if (!indio_dev) 1140 return -ENOMEM; 1141 mpu3050 = iio_priv(indio_dev); 1142 1143 mpu3050->dev = dev; 1144 mpu3050->map = map; 1145 mutex_init(&mpu3050->lock); 1146 /* Default fullscale: 2000 degrees per second */ 1147 mpu3050->fullscale = FS_2000_DPS; 1148 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1149 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1150 mpu3050->divisor = 99; 1151 1152 /* Read the mounting matrix, if present */ 1153 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation); 1154 if (ret) 1155 return ret; 1156 1157 /* Fetch and turn on regulators */ 1158 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1159 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1160 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1161 mpu3050->regs); 1162 if (ret) { 1163 dev_err(dev, "Cannot get regulators\n"); 1164 return ret; 1165 } 1166 1167 ret = mpu3050_power_up(mpu3050); 1168 if (ret) 1169 return ret; 1170 1171 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1172 if (ret) { 1173 dev_err(dev, "could not read device ID\n"); 1174 ret = -ENODEV; 1175 1176 goto err_power_down; 1177 } 1178 1179 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1180 dev_err(dev, "unsupported chip id %02x\n", 1181 (u8)(val & MPU3050_CHIP_ID_MASK)); 1182 ret = -ENODEV; 1183 goto err_power_down; 1184 } 1185 1186 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1187 if (ret) { 1188 dev_err(dev, "could not read device ID\n"); 1189 ret = -ENODEV; 1190 1191 goto err_power_down; 1192 } 1193 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1194 ((val >> 4) & 0xf), (val & 0xf)); 1195 1196 ret = mpu3050_hw_init(mpu3050); 1197 if (ret) 1198 goto err_power_down; 1199 1200 indio_dev->dev.parent = dev; 1201 indio_dev->channels = mpu3050_channels; 1202 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1203 indio_dev->info = &mpu3050_info; 1204 indio_dev->available_scan_masks = mpu3050_scan_masks; 1205 indio_dev->modes = INDIO_DIRECT_MODE; 1206 indio_dev->name = name; 1207 1208 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1209 mpu3050_trigger_handler, 1210 &mpu3050_buffer_setup_ops); 1211 if (ret) { 1212 dev_err(dev, "triggered buffer setup failed\n"); 1213 goto err_power_down; 1214 } 1215 1216 ret = iio_device_register(indio_dev); 1217 if (ret) { 1218 dev_err(dev, "device register failed\n"); 1219 goto err_cleanup_buffer; 1220 } 1221 1222 dev_set_drvdata(dev, indio_dev); 1223 1224 /* Check if we have an assigned IRQ to use as trigger */ 1225 if (irq) { 1226 ret = mpu3050_trigger_probe(indio_dev, irq); 1227 if (ret) 1228 dev_err(dev, "failed to register trigger\n"); 1229 } 1230 1231 /* Enable runtime PM */ 1232 pm_runtime_get_noresume(dev); 1233 pm_runtime_set_active(dev); 1234 pm_runtime_enable(dev); 1235 /* 1236 * Set autosuspend to two orders of magnitude larger than the 1237 * start-up time. 100ms start-up time means 10000ms autosuspend, 1238 * i.e. 10 seconds. 1239 */ 1240 pm_runtime_set_autosuspend_delay(dev, 10000); 1241 pm_runtime_use_autosuspend(dev); 1242 pm_runtime_put(dev); 1243 1244 return 0; 1245 1246 err_cleanup_buffer: 1247 iio_triggered_buffer_cleanup(indio_dev); 1248 err_power_down: 1249 mpu3050_power_down(mpu3050); 1250 1251 return ret; 1252 } 1253 EXPORT_SYMBOL(mpu3050_common_probe); 1254 1255 int mpu3050_common_remove(struct device *dev) 1256 { 1257 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1258 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1259 1260 pm_runtime_get_sync(dev); 1261 pm_runtime_put_noidle(dev); 1262 pm_runtime_disable(dev); 1263 iio_triggered_buffer_cleanup(indio_dev); 1264 if (mpu3050->irq) 1265 free_irq(mpu3050->irq, mpu3050); 1266 iio_device_unregister(indio_dev); 1267 mpu3050_power_down(mpu3050); 1268 1269 return 0; 1270 } 1271 EXPORT_SYMBOL(mpu3050_common_remove); 1272 1273 #ifdef CONFIG_PM 1274 static int mpu3050_runtime_suspend(struct device *dev) 1275 { 1276 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1277 } 1278 1279 static int mpu3050_runtime_resume(struct device *dev) 1280 { 1281 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1282 } 1283 #endif /* CONFIG_PM */ 1284 1285 const struct dev_pm_ops mpu3050_dev_pm_ops = { 1286 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1287 pm_runtime_force_resume) 1288 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, 1289 mpu3050_runtime_resume, NULL) 1290 }; 1291 EXPORT_SYMBOL(mpu3050_dev_pm_ops); 1292 1293 MODULE_AUTHOR("Linus Walleij"); 1294 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1295 MODULE_LICENSE("GPL"); 1296