1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for NXP FXAS21002C Gyroscope - Core 4 * 5 * Copyright (C) 2019 Linaro Ltd. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of_irq.h> 11 #include <linux/pm.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <linux/iio/events.h> 17 #include <linux/iio/iio.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/trigger.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 24 #include "fxas21002c.h" 25 26 #define FXAS21002C_CHIP_ID_1 0xD6 27 #define FXAS21002C_CHIP_ID_2 0xD7 28 29 enum fxas21002c_mode_state { 30 FXAS21002C_MODE_STANDBY, 31 FXAS21002C_MODE_READY, 32 FXAS21002C_MODE_ACTIVE, 33 }; 34 35 #define FXAS21002C_STANDBY_ACTIVE_TIME_MS 62 36 #define FXAS21002C_READY_ACTIVE_TIME_MS 7 37 38 #define FXAS21002C_ODR_LIST_MAX 10 39 40 #define FXAS21002C_SCALE_FRACTIONAL 32 41 #define FXAS21002C_RANGE_LIMIT_DOUBLE 2000 42 43 #define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2)) 44 45 static const struct reg_field fxas21002c_reg_fields[] = { 46 [F_DR_STATUS] = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7), 47 [F_OUT_X_MSB] = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7), 48 [F_OUT_X_LSB] = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7), 49 [F_OUT_Y_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7), 50 [F_OUT_Y_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7), 51 [F_OUT_Z_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7), 52 [F_OUT_Z_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7), 53 [F_ZYX_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7), 54 [F_Z_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6), 55 [F_Y_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5), 56 [F_X_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4), 57 [F_ZYX_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3), 58 [F_Z_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2), 59 [F_Y_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1), 60 [F_X_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0), 61 [F_OVF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7), 62 [F_WMKF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6), 63 [F_CNT] = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5), 64 [F_MODE] = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7), 65 [F_WMRK] = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5), 66 [F_EVENT] = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5), 67 [FE_TIME] = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4), 68 [F_BOOTEND] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3), 69 [F_SRC_FIFO] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2), 70 [F_SRC_RT] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1), 71 [F_SRC_DRDY] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0), 72 [F_WHO_AM_I] = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7), 73 [F_BW] = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7), 74 [F_SPIW] = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5), 75 [F_SEL] = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4), 76 [F_HPF_EN] = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2), 77 [F_FS] = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1), 78 [F_ELE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3), 79 [F_ZTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2), 80 [F_YTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1), 81 [F_XTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0), 82 [F_EA] = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6), 83 [F_ZRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5), 84 [F_ZRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4), 85 [F_YRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3), 86 [F_YRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2), 87 [F_XRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1), 88 [F_XRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0), 89 [F_DBCNTM] = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7), 90 [F_THS] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6), 91 [F_RT_COUNT] = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7), 92 [F_TEMP] = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7), 93 [F_RST] = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6), 94 [F_ST] = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5), 95 [F_DR] = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4), 96 [F_ACTIVE] = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1), 97 [F_READY] = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0), 98 [F_INT_CFG_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7), 99 [F_INT_EN_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6), 100 [F_INT_CFG_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5), 101 [F_INT_EN_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4), 102 [F_INT_CFG_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3), 103 [F_INT_EN_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2), 104 [F_IPOL] = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1), 105 [F_PP_OD] = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0), 106 [F_WRAPTOONE] = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3), 107 [F_EXTCTRLEN] = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2), 108 [F_FS_DOUBLE] = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0), 109 }; 110 111 static const int fxas21002c_odr_values[] = { 112 800, 400, 200, 100, 50, 25, 12, 12 113 }; 114 115 /* 116 * These values are taken from the low-pass filter cutoff frequency calculated 117 * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32 118 * => LPF cutoff frequency = 800 * 0.32 = 256 Hz 119 */ 120 static const int fxas21002c_lpf_values[] = { 121 32, 16, 8 122 }; 123 124 /* 125 * These values are taken from the high-pass filter cutoff frequency calculated 126 * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750 127 * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz 128 */ 129 static const int fxas21002c_hpf_values[] = { 130 18750, 9625, 4875, 2475 131 }; 132 133 static const int fxas21002c_range_values[] = { 134 4000, 2000, 1000, 500, 250 135 }; 136 137 struct fxas21002c_data { 138 u8 chip_id; 139 enum fxas21002c_mode_state mode; 140 enum fxas21002c_mode_state prev_mode; 141 142 struct mutex lock; /* serialize data access */ 143 struct regmap *regmap; 144 struct regmap_field *regmap_fields[F_MAX_FIELDS]; 145 struct iio_trigger *dready_trig; 146 s64 timestamp; 147 int irq; 148 149 struct regulator *vdd; 150 struct regulator *vddio; 151 152 /* 153 * DMA (thus cache coherency maintenance) requires the 154 * transfer buffers to live in their own cache lines. 155 */ 156 s16 buffer[8] ____cacheline_aligned; 157 }; 158 159 enum fxas21002c_channel_index { 160 CHANNEL_SCAN_INDEX_X, 161 CHANNEL_SCAN_INDEX_Y, 162 CHANNEL_SCAN_INDEX_Z, 163 CHANNEL_SCAN_MAX, 164 }; 165 166 static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value) 167 { 168 int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1; 169 170 value = min_t(u8, value, odr_value_max); 171 172 return fxas21002c_odr_values[value]; 173 } 174 175 static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data, 176 unsigned int hz) 177 { 178 int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values); 179 int i; 180 181 for (i = 0; i < odr_table_size; i++) 182 if (fxas21002c_odr_values[i] == hz) 183 return i; 184 185 return -EINVAL; 186 } 187 188 static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value) 189 { 190 int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1; 191 192 value = min_t(u8, value, lpf_value_max); 193 194 return fxas21002c_lpf_values[value]; 195 } 196 197 static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data, 198 unsigned int hz) 199 { 200 int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values); 201 int i; 202 203 for (i = 0; i < lpf_table_size; i++) 204 if (fxas21002c_lpf_values[i] == hz) 205 return i; 206 207 return -EINVAL; 208 } 209 210 static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value) 211 { 212 int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1; 213 214 value = min_t(u8, value, hpf_value_max); 215 216 return fxas21002c_hpf_values[value]; 217 } 218 219 static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data, 220 unsigned int hz) 221 { 222 int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values); 223 int i; 224 225 for (i = 0; i < hpf_table_size; i++) 226 if (fxas21002c_hpf_values[i] == hz) 227 return i; 228 229 return -EINVAL; 230 } 231 232 static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data, 233 u8 value) 234 { 235 int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1; 236 unsigned int fs_double; 237 int ret; 238 239 /* We need to check if FS_DOUBLE is enabled to offset the value */ 240 ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double); 241 if (ret < 0) 242 return ret; 243 244 if (!fs_double) 245 value += 1; 246 247 value = min_t(u8, value, range_value_max); 248 249 return fxas21002c_range_values[value]; 250 } 251 252 static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data, 253 unsigned int range) 254 { 255 int range_table_size = ARRAY_SIZE(fxas21002c_range_values); 256 bool found = false; 257 int fs_double = 0; 258 int ret; 259 int i; 260 261 for (i = 0; i < range_table_size; i++) 262 if (fxas21002c_range_values[i] == range) { 263 found = true; 264 break; 265 } 266 267 if (!found) 268 return -EINVAL; 269 270 if (range > FXAS21002C_RANGE_LIMIT_DOUBLE) 271 fs_double = 1; 272 273 ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double); 274 if (ret < 0) 275 return ret; 276 277 return i; 278 } 279 280 static int fxas21002c_mode_get(struct fxas21002c_data *data) 281 { 282 unsigned int active; 283 unsigned int ready; 284 int ret; 285 286 ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active); 287 if (ret < 0) 288 return ret; 289 if (active) 290 return FXAS21002C_MODE_ACTIVE; 291 292 ret = regmap_field_read(data->regmap_fields[F_READY], &ready); 293 if (ret < 0) 294 return ret; 295 if (ready) 296 return FXAS21002C_MODE_READY; 297 298 return FXAS21002C_MODE_STANDBY; 299 } 300 301 static int fxas21002c_mode_set(struct fxas21002c_data *data, 302 enum fxas21002c_mode_state mode) 303 { 304 int ret; 305 306 if (mode == data->mode) 307 return 0; 308 309 if (mode == FXAS21002C_MODE_READY) 310 ret = regmap_field_write(data->regmap_fields[F_READY], 1); 311 else 312 ret = regmap_field_write(data->regmap_fields[F_READY], 0); 313 if (ret < 0) 314 return ret; 315 316 if (mode == FXAS21002C_MODE_ACTIVE) 317 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1); 318 else 319 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0); 320 if (ret < 0) 321 return ret; 322 323 /* if going to active wait the setup times */ 324 if (mode == FXAS21002C_MODE_ACTIVE && 325 data->mode == FXAS21002C_MODE_STANDBY) 326 msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS); 327 328 if (data->mode == FXAS21002C_MODE_READY) 329 msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS); 330 331 data->prev_mode = data->mode; 332 data->mode = mode; 333 334 return ret; 335 } 336 337 static int fxas21002c_write(struct fxas21002c_data *data, 338 enum fxas21002c_fields field, int bits) 339 { 340 int actual_mode; 341 int ret; 342 343 mutex_lock(&data->lock); 344 345 actual_mode = fxas21002c_mode_get(data); 346 if (actual_mode < 0) { 347 ret = actual_mode; 348 goto out_unlock; 349 } 350 351 ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY); 352 if (ret < 0) 353 goto out_unlock; 354 355 ret = regmap_field_write(data->regmap_fields[field], bits); 356 if (ret < 0) 357 goto out_unlock; 358 359 ret = fxas21002c_mode_set(data, data->prev_mode); 360 361 out_unlock: 362 mutex_unlock(&data->lock); 363 364 return ret; 365 } 366 367 static int fxas21002c_pm_get(struct fxas21002c_data *data) 368 { 369 struct device *dev = regmap_get_device(data->regmap); 370 int ret; 371 372 ret = pm_runtime_get_sync(dev); 373 if (ret < 0) 374 pm_runtime_put_noidle(dev); 375 376 return ret; 377 } 378 379 static int fxas21002c_pm_put(struct fxas21002c_data *data) 380 { 381 struct device *dev = regmap_get_device(data->regmap); 382 383 pm_runtime_mark_last_busy(dev); 384 385 return pm_runtime_put_autosuspend(dev); 386 } 387 388 static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val) 389 { 390 struct device *dev = regmap_get_device(data->regmap); 391 unsigned int temp; 392 int ret; 393 394 mutex_lock(&data->lock); 395 ret = fxas21002c_pm_get(data); 396 if (ret < 0) 397 goto data_unlock; 398 399 ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp); 400 if (ret < 0) { 401 dev_err(dev, "failed to read temp: %d\n", ret); 402 fxas21002c_pm_put(data); 403 goto data_unlock; 404 } 405 406 *val = sign_extend32(temp, 7); 407 408 ret = fxas21002c_pm_put(data); 409 if (ret < 0) 410 goto data_unlock; 411 412 ret = IIO_VAL_INT; 413 414 data_unlock: 415 mutex_unlock(&data->lock); 416 417 return ret; 418 } 419 420 static int fxas21002c_axis_get(struct fxas21002c_data *data, 421 int index, int *val) 422 { 423 struct device *dev = regmap_get_device(data->regmap); 424 __be16 axis_be; 425 int ret; 426 427 mutex_lock(&data->lock); 428 ret = fxas21002c_pm_get(data); 429 if (ret < 0) 430 goto data_unlock; 431 432 ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index), 433 &axis_be, sizeof(axis_be)); 434 if (ret < 0) { 435 dev_err(dev, "failed to read axis: %d: %d\n", index, ret); 436 fxas21002c_pm_put(data); 437 goto data_unlock; 438 } 439 440 *val = sign_extend32(be16_to_cpu(axis_be), 15); 441 442 ret = fxas21002c_pm_put(data); 443 if (ret < 0) 444 goto data_unlock; 445 446 ret = IIO_VAL_INT; 447 448 data_unlock: 449 mutex_unlock(&data->lock); 450 451 return ret; 452 } 453 454 static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr) 455 { 456 unsigned int odr_bits; 457 int ret; 458 459 mutex_lock(&data->lock); 460 ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits); 461 if (ret < 0) 462 goto data_unlock; 463 464 *odr = fxas21002c_odr_hz_from_value(data, odr_bits); 465 466 ret = IIO_VAL_INT; 467 468 data_unlock: 469 mutex_unlock(&data->lock); 470 471 return ret; 472 } 473 474 static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr) 475 { 476 int odr_bits; 477 478 odr_bits = fxas21002c_odr_value_from_hz(data, odr); 479 if (odr_bits < 0) 480 return odr_bits; 481 482 return fxas21002c_write(data, F_DR, odr_bits); 483 } 484 485 static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2) 486 { 487 unsigned int bw_bits; 488 int ret; 489 490 mutex_lock(&data->lock); 491 ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits); 492 if (ret < 0) 493 goto data_unlock; 494 495 *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000; 496 497 ret = IIO_VAL_INT_PLUS_MICRO; 498 499 data_unlock: 500 mutex_unlock(&data->lock); 501 502 return ret; 503 } 504 505 static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw) 506 { 507 int bw_bits; 508 int odr; 509 int ret; 510 511 bw_bits = fxas21002c_lpf_value_from_bw(data, bw); 512 if (bw_bits < 0) 513 return bw_bits; 514 515 /* 516 * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08 517 * is not allowed and for ODR = 12.5 value 0.16 is also not allowed 518 */ 519 ret = fxas21002c_odr_get(data, &odr); 520 if (ret < 0) 521 return -EINVAL; 522 523 if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0)) 524 return -EINVAL; 525 526 return fxas21002c_write(data, F_BW, bw_bits); 527 } 528 529 static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2) 530 { 531 unsigned int sel_bits; 532 int ret; 533 534 mutex_lock(&data->lock); 535 ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits); 536 if (ret < 0) 537 goto data_unlock; 538 539 *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits); 540 541 ret = IIO_VAL_INT_PLUS_MICRO; 542 543 data_unlock: 544 mutex_unlock(&data->lock); 545 546 return ret; 547 } 548 549 static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel) 550 { 551 int sel_bits; 552 553 sel_bits = fxas21002c_hpf_value_from_sel(data, sel); 554 if (sel_bits < 0) 555 return sel_bits; 556 557 return fxas21002c_write(data, F_SEL, sel_bits); 558 } 559 560 static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val) 561 { 562 int fs_bits; 563 int scale; 564 int ret; 565 566 mutex_lock(&data->lock); 567 ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits); 568 if (ret < 0) 569 goto data_unlock; 570 571 scale = fxas21002c_range_fs_from_value(data, fs_bits); 572 if (scale < 0) { 573 ret = scale; 574 goto data_unlock; 575 } 576 577 *val = scale; 578 579 data_unlock: 580 mutex_unlock(&data->lock); 581 582 return ret; 583 } 584 585 static int fxas21002c_scale_set(struct fxas21002c_data *data, int range) 586 { 587 int fs_bits; 588 589 fs_bits = fxas21002c_range_value_from_fs(data, range); 590 if (fs_bits < 0) 591 return fs_bits; 592 593 return fxas21002c_write(data, F_FS, fs_bits); 594 } 595 596 static int fxas21002c_read_raw(struct iio_dev *indio_dev, 597 struct iio_chan_spec const *chan, int *val, 598 int *val2, long mask) 599 { 600 struct fxas21002c_data *data = iio_priv(indio_dev); 601 int ret; 602 603 switch (mask) { 604 case IIO_CHAN_INFO_RAW: 605 switch (chan->type) { 606 case IIO_TEMP: 607 return fxas21002c_temp_get(data, val); 608 case IIO_ANGL_VEL: 609 return fxas21002c_axis_get(data, chan->scan_index, val); 610 default: 611 return -EINVAL; 612 } 613 case IIO_CHAN_INFO_SCALE: 614 switch (chan->type) { 615 case IIO_ANGL_VEL: 616 *val2 = FXAS21002C_SCALE_FRACTIONAL; 617 ret = fxas21002c_scale_get(data, val); 618 if (ret < 0) 619 return ret; 620 621 return IIO_VAL_FRACTIONAL; 622 default: 623 return -EINVAL; 624 } 625 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 626 *val = 0; 627 return fxas21002c_lpf_get(data, val2); 628 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 629 *val = 0; 630 return fxas21002c_hpf_get(data, val2); 631 case IIO_CHAN_INFO_SAMP_FREQ: 632 *val2 = 0; 633 return fxas21002c_odr_get(data, val); 634 default: 635 return -EINVAL; 636 } 637 } 638 639 static int fxas21002c_write_raw(struct iio_dev *indio_dev, 640 struct iio_chan_spec const *chan, int val, 641 int val2, long mask) 642 { 643 struct fxas21002c_data *data = iio_priv(indio_dev); 644 int range; 645 646 switch (mask) { 647 case IIO_CHAN_INFO_SAMP_FREQ: 648 if (val2) 649 return -EINVAL; 650 651 return fxas21002c_odr_set(data, val); 652 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 653 if (val) 654 return -EINVAL; 655 656 val2 = val2 / 10000; 657 return fxas21002c_lpf_set(data, val2); 658 case IIO_CHAN_INFO_SCALE: 659 switch (chan->type) { 660 case IIO_ANGL_VEL: 661 range = (((val * 1000 + val2 / 1000) * 662 FXAS21002C_SCALE_FRACTIONAL) / 1000); 663 return fxas21002c_scale_set(data, range); 664 default: 665 return -EINVAL; 666 } 667 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 668 return fxas21002c_hpf_set(data, val2); 669 default: 670 return -EINVAL; 671 } 672 } 673 674 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800"); 675 676 static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available, 677 "0.32 0.16 0.08"); 678 679 static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available, 680 "0.018750 0.009625 0.004875 0.002475"); 681 682 static IIO_CONST_ATTR(in_anglvel_scale_available, 683 "125.0 62.5 31.25 15.625 7.8125"); 684 685 static struct attribute *fxas21002c_attributes[] = { 686 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 687 &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr, 688 &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr, 689 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 690 NULL, 691 }; 692 693 static const struct attribute_group fxas21002c_attrs_group = { 694 .attrs = fxas21002c_attributes, 695 }; 696 697 #define FXAS21002C_CHANNEL(_axis) { \ 698 .type = IIO_ANGL_VEL, \ 699 .modified = 1, \ 700 .channel2 = IIO_MOD_##_axis, \ 701 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 702 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 703 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 704 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 705 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 706 .scan_index = CHANNEL_SCAN_INDEX_##_axis, \ 707 .scan_type = { \ 708 .sign = 's', \ 709 .realbits = 16, \ 710 .storagebits = 16, \ 711 .endianness = IIO_BE, \ 712 }, \ 713 } 714 715 static const struct iio_chan_spec fxas21002c_channels[] = { 716 { 717 .type = IIO_TEMP, 718 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 719 .scan_index = -1, 720 }, 721 FXAS21002C_CHANNEL(X), 722 FXAS21002C_CHANNEL(Y), 723 FXAS21002C_CHANNEL(Z), 724 }; 725 726 static const struct iio_info fxas21002c_info = { 727 .attrs = &fxas21002c_attrs_group, 728 .read_raw = &fxas21002c_read_raw, 729 .write_raw = &fxas21002c_write_raw, 730 }; 731 732 static irqreturn_t fxas21002c_trigger_handler(int irq, void *p) 733 { 734 struct iio_poll_func *pf = p; 735 struct iio_dev *indio_dev = pf->indio_dev; 736 struct fxas21002c_data *data = iio_priv(indio_dev); 737 int ret; 738 739 mutex_lock(&data->lock); 740 ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB, 741 data->buffer, CHANNEL_SCAN_MAX * sizeof(s16)); 742 if (ret < 0) 743 goto out_unlock; 744 745 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 746 data->timestamp); 747 748 out_unlock: 749 mutex_unlock(&data->lock); 750 751 iio_trigger_notify_done(indio_dev->trig); 752 753 return IRQ_HANDLED; 754 } 755 756 static int fxas21002c_chip_init(struct fxas21002c_data *data) 757 { 758 struct device *dev = regmap_get_device(data->regmap); 759 unsigned int chip_id; 760 int ret; 761 762 ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id); 763 if (ret < 0) 764 return ret; 765 766 if (chip_id != FXAS21002C_CHIP_ID_1 && 767 chip_id != FXAS21002C_CHIP_ID_2) { 768 dev_err(dev, "chip id 0x%02x is not supported\n", chip_id); 769 return -EINVAL; 770 } 771 772 data->chip_id = chip_id; 773 774 ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY); 775 if (ret < 0) 776 return ret; 777 778 /* Set ODR to 200HZ as default */ 779 ret = fxas21002c_odr_set(data, 200); 780 if (ret < 0) 781 dev_err(dev, "failed to set ODR: %d\n", ret); 782 783 return ret; 784 } 785 786 static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig, 787 bool state) 788 { 789 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 790 struct fxas21002c_data *data = iio_priv(indio_dev); 791 792 return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state); 793 } 794 795 static const struct iio_trigger_ops fxas21002c_trigger_ops = { 796 .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state, 797 }; 798 799 static irqreturn_t fxas21002c_data_rdy_handler(int irq, void *private) 800 { 801 struct iio_dev *indio_dev = private; 802 struct fxas21002c_data *data = iio_priv(indio_dev); 803 804 data->timestamp = iio_get_time_ns(indio_dev); 805 806 return IRQ_WAKE_THREAD; 807 } 808 809 static irqreturn_t fxas21002c_data_rdy_thread(int irq, void *private) 810 { 811 struct iio_dev *indio_dev = private; 812 struct fxas21002c_data *data = iio_priv(indio_dev); 813 unsigned int data_ready; 814 int ret; 815 816 ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready); 817 if (ret < 0) 818 return IRQ_NONE; 819 820 if (!data_ready) 821 return IRQ_NONE; 822 823 iio_trigger_poll_chained(data->dready_trig); 824 825 return IRQ_HANDLED; 826 } 827 828 static int fxas21002c_trigger_probe(struct fxas21002c_data *data) 829 { 830 struct device *dev = regmap_get_device(data->regmap); 831 struct iio_dev *indio_dev = dev_get_drvdata(dev); 832 struct device_node *np = indio_dev->dev.of_node; 833 unsigned long irq_trig; 834 bool irq_open_drain; 835 int irq1; 836 int ret; 837 838 if (!data->irq) 839 return 0; 840 841 irq1 = of_irq_get_byname(np, "INT1"); 842 843 if (irq1 == data->irq) { 844 dev_info(dev, "using interrupt line INT1\n"); 845 ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY], 846 1); 847 if (ret < 0) 848 return ret; 849 } 850 851 dev_info(dev, "using interrupt line INT2\n"); 852 853 irq_open_drain = of_property_read_bool(np, "drive-open-drain"); 854 855 data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 856 indio_dev->name, 857 indio_dev->id); 858 if (!data->dready_trig) 859 return -ENOMEM; 860 861 irq_trig = irqd_get_trigger_type(irq_get_irq_data(data->irq)); 862 863 if (irq_trig == IRQF_TRIGGER_RISING) { 864 ret = regmap_field_write(data->regmap_fields[F_IPOL], 1); 865 if (ret < 0) 866 return ret; 867 } 868 869 if (irq_open_drain) 870 irq_trig |= IRQF_SHARED; 871 872 ret = devm_request_threaded_irq(dev, data->irq, 873 fxas21002c_data_rdy_handler, 874 fxas21002c_data_rdy_thread, 875 irq_trig, "fxas21002c_data_ready", 876 indio_dev); 877 if (ret < 0) 878 return ret; 879 880 data->dready_trig->ops = &fxas21002c_trigger_ops; 881 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 882 883 return devm_iio_trigger_register(dev, data->dready_trig); 884 } 885 886 static int fxas21002c_power_enable(struct fxas21002c_data *data) 887 { 888 int ret; 889 890 ret = regulator_enable(data->vdd); 891 if (ret < 0) 892 return ret; 893 894 ret = regulator_enable(data->vddio); 895 if (ret < 0) { 896 regulator_disable(data->vdd); 897 return ret; 898 } 899 900 return 0; 901 } 902 903 static void fxas21002c_power_disable(struct fxas21002c_data *data) 904 { 905 regulator_disable(data->vdd); 906 regulator_disable(data->vddio); 907 } 908 909 static void fxas21002c_power_disable_action(void *_data) 910 { 911 struct fxas21002c_data *data = _data; 912 913 fxas21002c_power_disable(data); 914 } 915 916 static int fxas21002c_regulators_get(struct fxas21002c_data *data) 917 { 918 struct device *dev = regmap_get_device(data->regmap); 919 920 data->vdd = devm_regulator_get(dev->parent, "vdd"); 921 if (IS_ERR(data->vdd)) 922 return PTR_ERR(data->vdd); 923 924 data->vddio = devm_regulator_get(dev->parent, "vddio"); 925 926 return PTR_ERR_OR_ZERO(data->vddio); 927 } 928 929 int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq, 930 const char *name) 931 { 932 struct fxas21002c_data *data; 933 struct iio_dev *indio_dev; 934 struct regmap_field *f; 935 int i; 936 int ret; 937 938 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 939 if (!indio_dev) 940 return -ENOMEM; 941 942 data = iio_priv(indio_dev); 943 dev_set_drvdata(dev, indio_dev); 944 data->irq = irq; 945 data->regmap = regmap; 946 947 for (i = 0; i < F_MAX_FIELDS; i++) { 948 f = devm_regmap_field_alloc(dev, data->regmap, 949 fxas21002c_reg_fields[i]); 950 if (IS_ERR(f)) 951 return PTR_ERR(f); 952 953 data->regmap_fields[i] = f; 954 } 955 956 mutex_init(&data->lock); 957 958 ret = fxas21002c_regulators_get(data); 959 if (ret < 0) 960 return ret; 961 962 ret = fxas21002c_power_enable(data); 963 if (ret < 0) 964 return ret; 965 966 ret = devm_add_action_or_reset(dev, fxas21002c_power_disable_action, 967 data); 968 if (ret < 0) 969 return ret; 970 971 ret = fxas21002c_chip_init(data); 972 if (ret < 0) 973 return ret; 974 975 indio_dev->channels = fxas21002c_channels; 976 indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels); 977 indio_dev->name = name; 978 indio_dev->modes = INDIO_DIRECT_MODE; 979 indio_dev->info = &fxas21002c_info; 980 981 ret = fxas21002c_trigger_probe(data); 982 if (ret < 0) 983 return ret; 984 985 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 986 fxas21002c_trigger_handler, NULL); 987 if (ret < 0) 988 return ret; 989 990 ret = pm_runtime_set_active(dev); 991 if (ret) 992 return ret; 993 994 pm_runtime_enable(dev); 995 pm_runtime_set_autosuspend_delay(dev, 2000); 996 pm_runtime_use_autosuspend(dev); 997 998 ret = iio_device_register(indio_dev); 999 if (ret < 0) 1000 goto pm_disable; 1001 1002 return 0; 1003 1004 pm_disable: 1005 pm_runtime_disable(dev); 1006 pm_runtime_set_suspended(dev); 1007 pm_runtime_put_noidle(dev); 1008 1009 return ret; 1010 } 1011 EXPORT_SYMBOL_GPL(fxas21002c_core_probe); 1012 1013 void fxas21002c_core_remove(struct device *dev) 1014 { 1015 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1016 1017 iio_device_unregister(indio_dev); 1018 1019 pm_runtime_disable(dev); 1020 pm_runtime_set_suspended(dev); 1021 pm_runtime_put_noidle(dev); 1022 } 1023 EXPORT_SYMBOL_GPL(fxas21002c_core_remove); 1024 1025 static int __maybe_unused fxas21002c_suspend(struct device *dev) 1026 { 1027 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); 1028 1029 fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY); 1030 fxas21002c_power_disable(data); 1031 1032 return 0; 1033 } 1034 1035 static int __maybe_unused fxas21002c_resume(struct device *dev) 1036 { 1037 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); 1038 int ret; 1039 1040 ret = fxas21002c_power_enable(data); 1041 if (ret < 0) 1042 return ret; 1043 1044 return fxas21002c_mode_set(data, data->prev_mode); 1045 } 1046 1047 static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev) 1048 { 1049 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); 1050 1051 return fxas21002c_mode_set(data, FXAS21002C_MODE_READY); 1052 } 1053 1054 static int __maybe_unused fxas21002c_runtime_resume(struct device *dev) 1055 { 1056 struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); 1057 1058 return fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE); 1059 } 1060 1061 const struct dev_pm_ops fxas21002c_pm_ops = { 1062 SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume) 1063 SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend, 1064 fxas21002c_runtime_resume, NULL) 1065 }; 1066 EXPORT_SYMBOL_GPL(fxas21002c_pm_ops); 1067 1068 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>"); 1069 MODULE_LICENSE("GPL v2"); 1070 MODULE_DESCRIPTION("FXAS21002C Gyro driver"); 1071