1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BMG160 Gyro Sensor driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/acpi.h> 12 #include <linux/pm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/iio/triggered_buffer.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include "bmg160.h" 24 25 #define BMG160_IRQ_NAME "bmg160_event" 26 27 #define BMG160_REG_CHIP_ID 0x00 28 #define BMG160_CHIP_ID_VAL 0x0F 29 30 #define BMG160_REG_PMU_LPW 0x11 31 #define BMG160_MODE_NORMAL 0x00 32 #define BMG160_MODE_DEEP_SUSPEND 0x20 33 #define BMG160_MODE_SUSPEND 0x80 34 35 #define BMG160_REG_RANGE 0x0F 36 37 #define BMG160_RANGE_2000DPS 0 38 #define BMG160_RANGE_1000DPS 1 39 #define BMG160_RANGE_500DPS 2 40 #define BMG160_RANGE_250DPS 3 41 #define BMG160_RANGE_125DPS 4 42 43 #define BMG160_REG_PMU_BW 0x10 44 #define BMG160_NO_FILTER 0 45 #define BMG160_DEF_BW 100 46 #define BMG160_REG_PMU_BW_RES BIT(7) 47 48 #define BMG160_GYRO_REG_RESET 0x14 49 #define BMG160_GYRO_RESET_VAL 0xb6 50 51 #define BMG160_REG_INT_MAP_0 0x17 52 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 53 54 #define BMG160_REG_INT_MAP_1 0x18 55 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 56 57 #define BMG160_REG_INT_RST_LATCH 0x21 58 #define BMG160_INT_MODE_LATCH_RESET 0x80 59 #define BMG160_INT_MODE_LATCH_INT 0x0F 60 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 61 62 #define BMG160_REG_INT_EN_0 0x15 63 #define BMG160_DATA_ENABLE_INT BIT(7) 64 65 #define BMG160_REG_INT_EN_1 0x16 66 #define BMG160_INT1_BIT_OD BIT(1) 67 68 #define BMG160_REG_XOUT_L 0x02 69 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 70 71 #define BMG160_REG_SLOPE_THRES 0x1B 72 #define BMG160_SLOPE_THRES_MASK 0x0F 73 74 #define BMG160_REG_MOTION_INTR 0x1C 75 #define BMG160_INT_MOTION_X BIT(0) 76 #define BMG160_INT_MOTION_Y BIT(1) 77 #define BMG160_INT_MOTION_Z BIT(2) 78 #define BMG160_ANY_DUR_MASK 0x30 79 #define BMG160_ANY_DUR_SHIFT 4 80 81 #define BMG160_REG_INT_STATUS_2 0x0B 82 #define BMG160_ANY_MOTION_MASK 0x07 83 #define BMG160_ANY_MOTION_BIT_X BIT(0) 84 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 85 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 86 87 #define BMG160_REG_TEMP 0x08 88 #define BMG160_TEMP_CENTER_VAL 23 89 90 #define BMG160_MAX_STARTUP_TIME_MS 80 91 92 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 93 94 struct bmg160_data { 95 struct regmap *regmap; 96 struct regulator_bulk_data regulators[2]; 97 struct iio_trigger *dready_trig; 98 struct iio_trigger *motion_trig; 99 struct iio_mount_matrix orientation; 100 struct mutex mutex; 101 /* Ensure naturally aligned timestamp */ 102 struct { 103 s16 chans[3]; 104 s64 timestamp __aligned(8); 105 } scan; 106 u32 dps_range; 107 int ev_enable_state; 108 int slope_thres; 109 bool dready_trigger_on; 110 bool motion_trigger_on; 111 int irq; 112 }; 113 114 enum bmg160_axis { 115 AXIS_X, 116 AXIS_Y, 117 AXIS_Z, 118 AXIS_MAX, 119 }; 120 121 static const struct { 122 int odr; 123 int filter; 124 int bw_bits; 125 } bmg160_samp_freq_table[] = { {100, 32, 0x07}, 126 {200, 64, 0x06}, 127 {100, 12, 0x05}, 128 {200, 23, 0x04}, 129 {400, 47, 0x03}, 130 {1000, 116, 0x02}, 131 {2000, 230, 0x01} }; 132 133 static const struct { 134 int scale; 135 int dps_range; 136 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 137 { 532, BMG160_RANGE_1000DPS}, 138 { 266, BMG160_RANGE_500DPS}, 139 { 133, BMG160_RANGE_250DPS}, 140 { 66, BMG160_RANGE_125DPS} }; 141 142 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 143 { 144 struct device *dev = regmap_get_device(data->regmap); 145 int ret; 146 147 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 148 if (ret < 0) { 149 dev_err(dev, "Error writing reg_pmu_lpw\n"); 150 return ret; 151 } 152 153 return 0; 154 } 155 156 static int bmg160_convert_freq_to_bit(int val) 157 { 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 161 if (bmg160_samp_freq_table[i].odr == val) 162 return bmg160_samp_freq_table[i].bw_bits; 163 } 164 165 return -EINVAL; 166 } 167 168 static int bmg160_set_bw(struct bmg160_data *data, int val) 169 { 170 struct device *dev = regmap_get_device(data->regmap); 171 int ret; 172 int bw_bits; 173 174 bw_bits = bmg160_convert_freq_to_bit(val); 175 if (bw_bits < 0) 176 return bw_bits; 177 178 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 179 if (ret < 0) { 180 dev_err(dev, "Error writing reg_pmu_bw\n"); 181 return ret; 182 } 183 184 return 0; 185 } 186 187 static int bmg160_get_filter(struct bmg160_data *data, int *val) 188 { 189 struct device *dev = regmap_get_device(data->regmap); 190 int ret; 191 int i; 192 unsigned int bw_bits; 193 194 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 195 if (ret < 0) { 196 dev_err(dev, "Error reading reg_pmu_bw\n"); 197 return ret; 198 } 199 200 /* Ignore the readonly reserved bit. */ 201 bw_bits &= ~BMG160_REG_PMU_BW_RES; 202 203 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 204 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) 205 break; 206 } 207 208 *val = bmg160_samp_freq_table[i].filter; 209 210 return ret ? ret : IIO_VAL_INT; 211 } 212 213 214 static int bmg160_set_filter(struct bmg160_data *data, int val) 215 { 216 struct device *dev = regmap_get_device(data->regmap); 217 int ret; 218 int i; 219 220 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 221 if (bmg160_samp_freq_table[i].filter == val) 222 break; 223 } 224 225 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, 226 bmg160_samp_freq_table[i].bw_bits); 227 if (ret < 0) { 228 dev_err(dev, "Error writing reg_pmu_bw\n"); 229 return ret; 230 } 231 232 return 0; 233 } 234 235 static int bmg160_chip_init(struct bmg160_data *data) 236 { 237 struct device *dev = regmap_get_device(data->regmap); 238 int ret; 239 unsigned int val; 240 241 /* 242 * Reset chip to get it in a known good state. A delay of 30ms after 243 * reset is required according to the datasheet. 244 */ 245 regmap_write(data->regmap, BMG160_GYRO_REG_RESET, 246 BMG160_GYRO_RESET_VAL); 247 usleep_range(30000, 30700); 248 249 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 250 if (ret < 0) { 251 dev_err(dev, "Error reading reg_chip_id\n"); 252 return ret; 253 } 254 255 dev_dbg(dev, "Chip Id %x\n", val); 256 if (val != BMG160_CHIP_ID_VAL) { 257 dev_err(dev, "invalid chip %x\n", val); 258 return -ENODEV; 259 } 260 261 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 262 if (ret < 0) 263 return ret; 264 265 /* Wait upto 500 ms to be ready after changing mode */ 266 usleep_range(500, 1000); 267 268 /* Set Bandwidth */ 269 ret = bmg160_set_bw(data, BMG160_DEF_BW); 270 if (ret < 0) 271 return ret; 272 273 /* Set Default Range */ 274 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 275 if (ret < 0) { 276 dev_err(dev, "Error writing reg_range\n"); 277 return ret; 278 } 279 data->dps_range = BMG160_RANGE_500DPS; 280 281 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 282 if (ret < 0) { 283 dev_err(dev, "Error reading reg_slope_thres\n"); 284 return ret; 285 } 286 data->slope_thres = val; 287 288 /* Set default interrupt mode */ 289 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 290 BMG160_INT1_BIT_OD, 0); 291 if (ret < 0) { 292 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 293 return ret; 294 } 295 296 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 297 BMG160_INT_MODE_LATCH_INT | 298 BMG160_INT_MODE_LATCH_RESET); 299 if (ret < 0) { 300 dev_err(dev, 301 "Error writing reg_motion_intr\n"); 302 return ret; 303 } 304 305 return 0; 306 } 307 308 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 309 { 310 #ifdef CONFIG_PM 311 struct device *dev = regmap_get_device(data->regmap); 312 int ret; 313 314 if (on) 315 ret = pm_runtime_get_sync(dev); 316 else { 317 pm_runtime_mark_last_busy(dev); 318 ret = pm_runtime_put_autosuspend(dev); 319 } 320 321 if (ret < 0) { 322 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 323 324 if (on) 325 pm_runtime_put_noidle(dev); 326 327 return ret; 328 } 329 #endif 330 331 return 0; 332 } 333 334 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 335 bool status) 336 { 337 struct device *dev = regmap_get_device(data->regmap); 338 int ret; 339 340 /* Enable/Disable INT_MAP0 mapping */ 341 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 342 BMG160_INT_MAP_0_BIT_ANY, 343 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 344 if (ret < 0) { 345 dev_err(dev, "Error updating bits reg_int_map0\n"); 346 return ret; 347 } 348 349 /* Enable/Disable slope interrupts */ 350 if (status) { 351 /* Update slope thres */ 352 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 353 data->slope_thres); 354 if (ret < 0) { 355 dev_err(dev, "Error writing reg_slope_thres\n"); 356 return ret; 357 } 358 359 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 360 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 361 BMG160_INT_MOTION_Z); 362 if (ret < 0) { 363 dev_err(dev, "Error writing reg_motion_intr\n"); 364 return ret; 365 } 366 367 /* 368 * New data interrupt is always non-latched, 369 * which will have higher priority, so no need 370 * to set latched mode, we will be flooded anyway with INTR 371 */ 372 if (!data->dready_trigger_on) { 373 ret = regmap_write(data->regmap, 374 BMG160_REG_INT_RST_LATCH, 375 BMG160_INT_MODE_LATCH_INT | 376 BMG160_INT_MODE_LATCH_RESET); 377 if (ret < 0) { 378 dev_err(dev, "Error writing reg_rst_latch\n"); 379 return ret; 380 } 381 } 382 383 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 384 BMG160_DATA_ENABLE_INT); 385 386 } else { 387 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 388 } 389 390 if (ret < 0) { 391 dev_err(dev, "Error writing reg_int_en0\n"); 392 return ret; 393 } 394 395 return 0; 396 } 397 398 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 399 bool status) 400 { 401 struct device *dev = regmap_get_device(data->regmap); 402 int ret; 403 404 /* Enable/Disable INT_MAP1 mapping */ 405 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 406 BMG160_INT_MAP_1_BIT_NEW_DATA, 407 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 408 if (ret < 0) { 409 dev_err(dev, "Error updating bits in reg_int_map1\n"); 410 return ret; 411 } 412 413 if (status) { 414 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 415 BMG160_INT_MODE_NON_LATCH_INT | 416 BMG160_INT_MODE_LATCH_RESET); 417 if (ret < 0) { 418 dev_err(dev, "Error writing reg_rst_latch\n"); 419 return ret; 420 } 421 422 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 423 BMG160_DATA_ENABLE_INT); 424 425 } else { 426 /* Restore interrupt mode */ 427 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 428 BMG160_INT_MODE_LATCH_INT | 429 BMG160_INT_MODE_LATCH_RESET); 430 if (ret < 0) { 431 dev_err(dev, "Error writing reg_rst_latch\n"); 432 return ret; 433 } 434 435 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 436 } 437 438 if (ret < 0) { 439 dev_err(dev, "Error writing reg_int_en0\n"); 440 return ret; 441 } 442 443 return 0; 444 } 445 446 static int bmg160_get_bw(struct bmg160_data *data, int *val) 447 { 448 struct device *dev = regmap_get_device(data->regmap); 449 int i; 450 unsigned int bw_bits; 451 int ret; 452 453 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 454 if (ret < 0) { 455 dev_err(dev, "Error reading reg_pmu_bw\n"); 456 return ret; 457 } 458 459 /* Ignore the readonly reserved bit. */ 460 bw_bits &= ~BMG160_REG_PMU_BW_RES; 461 462 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 463 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { 464 *val = bmg160_samp_freq_table[i].odr; 465 return IIO_VAL_INT; 466 } 467 } 468 469 return -EINVAL; 470 } 471 472 static int bmg160_set_scale(struct bmg160_data *data, int val) 473 { 474 struct device *dev = regmap_get_device(data->regmap); 475 int ret, i; 476 477 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 478 if (bmg160_scale_table[i].scale == val) { 479 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 480 bmg160_scale_table[i].dps_range); 481 if (ret < 0) { 482 dev_err(dev, "Error writing reg_range\n"); 483 return ret; 484 } 485 data->dps_range = bmg160_scale_table[i].dps_range; 486 return 0; 487 } 488 } 489 490 return -EINVAL; 491 } 492 493 static int bmg160_get_temp(struct bmg160_data *data, int *val) 494 { 495 struct device *dev = regmap_get_device(data->regmap); 496 int ret; 497 unsigned int raw_val; 498 499 mutex_lock(&data->mutex); 500 ret = bmg160_set_power_state(data, true); 501 if (ret < 0) { 502 mutex_unlock(&data->mutex); 503 return ret; 504 } 505 506 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 507 if (ret < 0) { 508 dev_err(dev, "Error reading reg_temp\n"); 509 bmg160_set_power_state(data, false); 510 mutex_unlock(&data->mutex); 511 return ret; 512 } 513 514 *val = sign_extend32(raw_val, 7); 515 ret = bmg160_set_power_state(data, false); 516 mutex_unlock(&data->mutex); 517 if (ret < 0) 518 return ret; 519 520 return IIO_VAL_INT; 521 } 522 523 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 524 { 525 struct device *dev = regmap_get_device(data->regmap); 526 int ret; 527 __le16 raw_val; 528 529 mutex_lock(&data->mutex); 530 ret = bmg160_set_power_state(data, true); 531 if (ret < 0) { 532 mutex_unlock(&data->mutex); 533 return ret; 534 } 535 536 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 537 sizeof(raw_val)); 538 if (ret < 0) { 539 dev_err(dev, "Error reading axis %d\n", axis); 540 bmg160_set_power_state(data, false); 541 mutex_unlock(&data->mutex); 542 return ret; 543 } 544 545 *val = sign_extend32(le16_to_cpu(raw_val), 15); 546 ret = bmg160_set_power_state(data, false); 547 mutex_unlock(&data->mutex); 548 if (ret < 0) 549 return ret; 550 551 return IIO_VAL_INT; 552 } 553 554 static int bmg160_read_raw(struct iio_dev *indio_dev, 555 struct iio_chan_spec const *chan, 556 int *val, int *val2, long mask) 557 { 558 struct bmg160_data *data = iio_priv(indio_dev); 559 int ret; 560 561 switch (mask) { 562 case IIO_CHAN_INFO_RAW: 563 switch (chan->type) { 564 case IIO_TEMP: 565 return bmg160_get_temp(data, val); 566 case IIO_ANGL_VEL: 567 if (iio_buffer_enabled(indio_dev)) 568 return -EBUSY; 569 else 570 return bmg160_get_axis(data, chan->scan_index, 571 val); 572 default: 573 return -EINVAL; 574 } 575 case IIO_CHAN_INFO_OFFSET: 576 if (chan->type == IIO_TEMP) { 577 *val = BMG160_TEMP_CENTER_VAL; 578 return IIO_VAL_INT; 579 } else 580 return -EINVAL; 581 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 582 return bmg160_get_filter(data, val); 583 case IIO_CHAN_INFO_SCALE: 584 switch (chan->type) { 585 case IIO_TEMP: 586 *val = 500; 587 return IIO_VAL_INT; 588 case IIO_ANGL_VEL: 589 { 590 int i; 591 592 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 593 if (bmg160_scale_table[i].dps_range == 594 data->dps_range) { 595 *val = 0; 596 *val2 = bmg160_scale_table[i].scale; 597 return IIO_VAL_INT_PLUS_MICRO; 598 } 599 } 600 return -EINVAL; 601 } 602 default: 603 return -EINVAL; 604 } 605 case IIO_CHAN_INFO_SAMP_FREQ: 606 *val2 = 0; 607 mutex_lock(&data->mutex); 608 ret = bmg160_get_bw(data, val); 609 mutex_unlock(&data->mutex); 610 return ret; 611 default: 612 return -EINVAL; 613 } 614 } 615 616 static int bmg160_write_raw(struct iio_dev *indio_dev, 617 struct iio_chan_spec const *chan, 618 int val, int val2, long mask) 619 { 620 struct bmg160_data *data = iio_priv(indio_dev); 621 int ret; 622 623 switch (mask) { 624 case IIO_CHAN_INFO_SAMP_FREQ: 625 mutex_lock(&data->mutex); 626 /* 627 * Section 4.2 of spec 628 * In suspend mode, the only supported operations are reading 629 * registers as well as writing to the (0x14) softreset 630 * register. Since we will be in suspend mode by default, change 631 * mode to power on for other writes. 632 */ 633 ret = bmg160_set_power_state(data, true); 634 if (ret < 0) { 635 mutex_unlock(&data->mutex); 636 return ret; 637 } 638 ret = bmg160_set_bw(data, val); 639 if (ret < 0) { 640 bmg160_set_power_state(data, false); 641 mutex_unlock(&data->mutex); 642 return ret; 643 } 644 ret = bmg160_set_power_state(data, false); 645 mutex_unlock(&data->mutex); 646 return ret; 647 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 648 if (val2) 649 return -EINVAL; 650 651 mutex_lock(&data->mutex); 652 ret = bmg160_set_power_state(data, true); 653 if (ret < 0) { 654 bmg160_set_power_state(data, false); 655 mutex_unlock(&data->mutex); 656 return ret; 657 } 658 ret = bmg160_set_filter(data, val); 659 if (ret < 0) { 660 bmg160_set_power_state(data, false); 661 mutex_unlock(&data->mutex); 662 return ret; 663 } 664 ret = bmg160_set_power_state(data, false); 665 mutex_unlock(&data->mutex); 666 return ret; 667 case IIO_CHAN_INFO_SCALE: 668 if (val) 669 return -EINVAL; 670 671 mutex_lock(&data->mutex); 672 /* Refer to comments above for the suspend mode ops */ 673 ret = bmg160_set_power_state(data, true); 674 if (ret < 0) { 675 mutex_unlock(&data->mutex); 676 return ret; 677 } 678 ret = bmg160_set_scale(data, val2); 679 if (ret < 0) { 680 bmg160_set_power_state(data, false); 681 mutex_unlock(&data->mutex); 682 return ret; 683 } 684 ret = bmg160_set_power_state(data, false); 685 mutex_unlock(&data->mutex); 686 return ret; 687 default: 688 return -EINVAL; 689 } 690 691 return -EINVAL; 692 } 693 694 static int bmg160_read_event(struct iio_dev *indio_dev, 695 const struct iio_chan_spec *chan, 696 enum iio_event_type type, 697 enum iio_event_direction dir, 698 enum iio_event_info info, 699 int *val, int *val2) 700 { 701 struct bmg160_data *data = iio_priv(indio_dev); 702 703 *val2 = 0; 704 switch (info) { 705 case IIO_EV_INFO_VALUE: 706 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 707 break; 708 default: 709 return -EINVAL; 710 } 711 712 return IIO_VAL_INT; 713 } 714 715 static int bmg160_write_event(struct iio_dev *indio_dev, 716 const struct iio_chan_spec *chan, 717 enum iio_event_type type, 718 enum iio_event_direction dir, 719 enum iio_event_info info, 720 int val, int val2) 721 { 722 struct bmg160_data *data = iio_priv(indio_dev); 723 724 switch (info) { 725 case IIO_EV_INFO_VALUE: 726 if (data->ev_enable_state) 727 return -EBUSY; 728 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 729 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 730 break; 731 default: 732 return -EINVAL; 733 } 734 735 return 0; 736 } 737 738 static int bmg160_read_event_config(struct iio_dev *indio_dev, 739 const struct iio_chan_spec *chan, 740 enum iio_event_type type, 741 enum iio_event_direction dir) 742 { 743 744 struct bmg160_data *data = iio_priv(indio_dev); 745 746 return data->ev_enable_state; 747 } 748 749 static int bmg160_write_event_config(struct iio_dev *indio_dev, 750 const struct iio_chan_spec *chan, 751 enum iio_event_type type, 752 enum iio_event_direction dir, 753 int state) 754 { 755 struct bmg160_data *data = iio_priv(indio_dev); 756 int ret; 757 758 if (state && data->ev_enable_state) 759 return 0; 760 761 mutex_lock(&data->mutex); 762 763 if (!state && data->motion_trigger_on) { 764 data->ev_enable_state = 0; 765 mutex_unlock(&data->mutex); 766 return 0; 767 } 768 /* 769 * We will expect the enable and disable to do operation 770 * in reverse order. This will happen here anyway as our 771 * resume operation uses sync mode runtime pm calls, the 772 * suspend operation will be delayed by autosuspend delay 773 * So the disable operation will still happen in reverse of 774 * enable operation. When runtime pm is disabled the mode 775 * is always on so sequence doesn't matter 776 */ 777 ret = bmg160_set_power_state(data, state); 778 if (ret < 0) { 779 mutex_unlock(&data->mutex); 780 return ret; 781 } 782 783 ret = bmg160_setup_any_motion_interrupt(data, state); 784 if (ret < 0) { 785 bmg160_set_power_state(data, false); 786 mutex_unlock(&data->mutex); 787 return ret; 788 } 789 790 data->ev_enable_state = state; 791 mutex_unlock(&data->mutex); 792 793 return 0; 794 } 795 796 static const struct iio_mount_matrix * 797 bmg160_get_mount_matrix(const struct iio_dev *indio_dev, 798 const struct iio_chan_spec *chan) 799 { 800 struct bmg160_data *data = iio_priv(indio_dev); 801 802 return &data->orientation; 803 } 804 805 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = { 806 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix), 807 { } 808 }; 809 810 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 811 812 static IIO_CONST_ATTR(in_anglvel_scale_available, 813 "0.001065 0.000532 0.000266 0.000133 0.000066"); 814 815 static struct attribute *bmg160_attributes[] = { 816 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 817 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 818 NULL, 819 }; 820 821 static const struct attribute_group bmg160_attrs_group = { 822 .attrs = bmg160_attributes, 823 }; 824 825 static const struct iio_event_spec bmg160_event = { 826 .type = IIO_EV_TYPE_ROC, 827 .dir = IIO_EV_DIR_EITHER, 828 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 829 BIT(IIO_EV_INFO_ENABLE) 830 }; 831 832 #define BMG160_CHANNEL(_axis) { \ 833 .type = IIO_ANGL_VEL, \ 834 .modified = 1, \ 835 .channel2 = IIO_MOD_##_axis, \ 836 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 837 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 838 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 839 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 840 .scan_index = AXIS_##_axis, \ 841 .scan_type = { \ 842 .sign = 's', \ 843 .realbits = 16, \ 844 .storagebits = 16, \ 845 .endianness = IIO_LE, \ 846 }, \ 847 .ext_info = bmg160_ext_info, \ 848 .event_spec = &bmg160_event, \ 849 .num_event_specs = 1 \ 850 } 851 852 static const struct iio_chan_spec bmg160_channels[] = { 853 { 854 .type = IIO_TEMP, 855 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 856 BIT(IIO_CHAN_INFO_SCALE) | 857 BIT(IIO_CHAN_INFO_OFFSET), 858 .scan_index = -1, 859 }, 860 BMG160_CHANNEL(X), 861 BMG160_CHANNEL(Y), 862 BMG160_CHANNEL(Z), 863 IIO_CHAN_SOFT_TIMESTAMP(3), 864 }; 865 866 static const struct iio_info bmg160_info = { 867 .attrs = &bmg160_attrs_group, 868 .read_raw = bmg160_read_raw, 869 .write_raw = bmg160_write_raw, 870 .read_event_value = bmg160_read_event, 871 .write_event_value = bmg160_write_event, 872 .write_event_config = bmg160_write_event_config, 873 .read_event_config = bmg160_read_event_config, 874 }; 875 876 static const unsigned long bmg160_accel_scan_masks[] = { 877 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 878 0}; 879 880 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 881 { 882 struct iio_poll_func *pf = p; 883 struct iio_dev *indio_dev = pf->indio_dev; 884 struct bmg160_data *data = iio_priv(indio_dev); 885 int ret; 886 887 mutex_lock(&data->mutex); 888 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 889 data->scan.chans, AXIS_MAX * 2); 890 mutex_unlock(&data->mutex); 891 if (ret < 0) 892 goto err; 893 894 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 895 pf->timestamp); 896 err: 897 iio_trigger_notify_done(indio_dev->trig); 898 899 return IRQ_HANDLED; 900 } 901 902 static void bmg160_trig_reen(struct iio_trigger *trig) 903 { 904 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 905 struct bmg160_data *data = iio_priv(indio_dev); 906 struct device *dev = regmap_get_device(data->regmap); 907 int ret; 908 909 /* new data interrupts don't need ack */ 910 if (data->dready_trigger_on) 911 return; 912 913 /* Set latched mode interrupt and clear any latched interrupt */ 914 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 915 BMG160_INT_MODE_LATCH_INT | 916 BMG160_INT_MODE_LATCH_RESET); 917 if (ret < 0) 918 dev_err(dev, "Error writing reg_rst_latch\n"); 919 } 920 921 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 922 bool state) 923 { 924 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 925 struct bmg160_data *data = iio_priv(indio_dev); 926 int ret; 927 928 mutex_lock(&data->mutex); 929 930 if (!state && data->ev_enable_state && data->motion_trigger_on) { 931 data->motion_trigger_on = false; 932 mutex_unlock(&data->mutex); 933 return 0; 934 } 935 936 /* 937 * Refer to comment in bmg160_write_event_config for 938 * enable/disable operation order 939 */ 940 ret = bmg160_set_power_state(data, state); 941 if (ret < 0) { 942 mutex_unlock(&data->mutex); 943 return ret; 944 } 945 if (data->motion_trig == trig) 946 ret = bmg160_setup_any_motion_interrupt(data, state); 947 else 948 ret = bmg160_setup_new_data_interrupt(data, state); 949 if (ret < 0) { 950 bmg160_set_power_state(data, false); 951 mutex_unlock(&data->mutex); 952 return ret; 953 } 954 if (data->motion_trig == trig) 955 data->motion_trigger_on = state; 956 else 957 data->dready_trigger_on = state; 958 959 mutex_unlock(&data->mutex); 960 961 return 0; 962 } 963 964 static const struct iio_trigger_ops bmg160_trigger_ops = { 965 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 966 .reenable = bmg160_trig_reen, 967 }; 968 969 static irqreturn_t bmg160_event_handler(int irq, void *private) 970 { 971 struct iio_dev *indio_dev = private; 972 struct bmg160_data *data = iio_priv(indio_dev); 973 struct device *dev = regmap_get_device(data->regmap); 974 int ret; 975 int dir; 976 unsigned int val; 977 978 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 979 if (ret < 0) { 980 dev_err(dev, "Error reading reg_int_status2\n"); 981 goto ack_intr_status; 982 } 983 984 if (val & 0x08) 985 dir = IIO_EV_DIR_RISING; 986 else 987 dir = IIO_EV_DIR_FALLING; 988 989 if (val & BMG160_ANY_MOTION_BIT_X) 990 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 991 0, 992 IIO_MOD_X, 993 IIO_EV_TYPE_ROC, 994 dir), 995 iio_get_time_ns(indio_dev)); 996 if (val & BMG160_ANY_MOTION_BIT_Y) 997 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 998 0, 999 IIO_MOD_Y, 1000 IIO_EV_TYPE_ROC, 1001 dir), 1002 iio_get_time_ns(indio_dev)); 1003 if (val & BMG160_ANY_MOTION_BIT_Z) 1004 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 1005 0, 1006 IIO_MOD_Z, 1007 IIO_EV_TYPE_ROC, 1008 dir), 1009 iio_get_time_ns(indio_dev)); 1010 1011 ack_intr_status: 1012 if (!data->dready_trigger_on) { 1013 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 1014 BMG160_INT_MODE_LATCH_INT | 1015 BMG160_INT_MODE_LATCH_RESET); 1016 if (ret < 0) 1017 dev_err(dev, "Error writing reg_rst_latch\n"); 1018 } 1019 1020 return IRQ_HANDLED; 1021 } 1022 1023 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 1024 { 1025 struct iio_dev *indio_dev = private; 1026 struct bmg160_data *data = iio_priv(indio_dev); 1027 1028 if (data->dready_trigger_on) 1029 iio_trigger_poll(data->dready_trig); 1030 else if (data->motion_trigger_on) 1031 iio_trigger_poll(data->motion_trig); 1032 1033 if (data->ev_enable_state) 1034 return IRQ_WAKE_THREAD; 1035 else 1036 return IRQ_HANDLED; 1037 1038 } 1039 1040 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 1041 { 1042 struct bmg160_data *data = iio_priv(indio_dev); 1043 1044 return bmg160_set_power_state(data, true); 1045 } 1046 1047 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 1048 { 1049 struct bmg160_data *data = iio_priv(indio_dev); 1050 1051 return bmg160_set_power_state(data, false); 1052 } 1053 1054 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 1055 .preenable = bmg160_buffer_preenable, 1056 .postdisable = bmg160_buffer_postdisable, 1057 }; 1058 1059 static const char *bmg160_match_acpi_device(struct device *dev) 1060 { 1061 const struct acpi_device_id *id; 1062 1063 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1064 if (!id) 1065 return NULL; 1066 1067 return dev_name(dev); 1068 } 1069 1070 static void bmg160_disable_regulators(void *d) 1071 { 1072 struct bmg160_data *data = d; 1073 1074 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); 1075 } 1076 1077 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 1078 const char *name) 1079 { 1080 struct bmg160_data *data; 1081 struct iio_dev *indio_dev; 1082 int ret; 1083 1084 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1085 if (!indio_dev) 1086 return -ENOMEM; 1087 1088 data = iio_priv(indio_dev); 1089 dev_set_drvdata(dev, indio_dev); 1090 data->irq = irq; 1091 data->regmap = regmap; 1092 1093 data->regulators[0].supply = "vdd"; 1094 data->regulators[1].supply = "vddio"; 1095 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->regulators), 1096 data->regulators); 1097 if (ret) 1098 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1099 1100 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), 1101 data->regulators); 1102 if (ret) 1103 return ret; 1104 1105 ret = devm_add_action_or_reset(dev, bmg160_disable_regulators, data); 1106 if (ret) 1107 return ret; 1108 1109 ret = iio_read_mount_matrix(dev, &data->orientation); 1110 if (ret) 1111 return ret; 1112 1113 ret = bmg160_chip_init(data); 1114 if (ret < 0) 1115 return ret; 1116 1117 mutex_init(&data->mutex); 1118 1119 if (ACPI_HANDLE(dev)) 1120 name = bmg160_match_acpi_device(dev); 1121 1122 indio_dev->channels = bmg160_channels; 1123 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1124 indio_dev->name = name; 1125 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 1126 indio_dev->modes = INDIO_DIRECT_MODE; 1127 indio_dev->info = &bmg160_info; 1128 1129 if (data->irq > 0) { 1130 ret = devm_request_threaded_irq(dev, 1131 data->irq, 1132 bmg160_data_rdy_trig_poll, 1133 bmg160_event_handler, 1134 IRQF_TRIGGER_RISING, 1135 BMG160_IRQ_NAME, 1136 indio_dev); 1137 if (ret) 1138 return ret; 1139 1140 data->dready_trig = devm_iio_trigger_alloc(dev, 1141 "%s-dev%d", 1142 indio_dev->name, 1143 iio_device_id(indio_dev)); 1144 if (!data->dready_trig) 1145 return -ENOMEM; 1146 1147 data->motion_trig = devm_iio_trigger_alloc(dev, 1148 "%s-any-motion-dev%d", 1149 indio_dev->name, 1150 iio_device_id(indio_dev)); 1151 if (!data->motion_trig) 1152 return -ENOMEM; 1153 1154 data->dready_trig->ops = &bmg160_trigger_ops; 1155 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1156 ret = iio_trigger_register(data->dready_trig); 1157 if (ret) 1158 return ret; 1159 1160 data->motion_trig->ops = &bmg160_trigger_ops; 1161 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1162 ret = iio_trigger_register(data->motion_trig); 1163 if (ret) { 1164 data->motion_trig = NULL; 1165 goto err_trigger_unregister; 1166 } 1167 } 1168 1169 ret = iio_triggered_buffer_setup(indio_dev, 1170 iio_pollfunc_store_time, 1171 bmg160_trigger_handler, 1172 &bmg160_buffer_setup_ops); 1173 if (ret < 0) { 1174 dev_err(dev, 1175 "iio triggered buffer setup failed\n"); 1176 goto err_trigger_unregister; 1177 } 1178 1179 ret = pm_runtime_set_active(dev); 1180 if (ret) 1181 goto err_buffer_cleanup; 1182 1183 pm_runtime_enable(dev); 1184 pm_runtime_set_autosuspend_delay(dev, 1185 BMG160_AUTO_SUSPEND_DELAY_MS); 1186 pm_runtime_use_autosuspend(dev); 1187 1188 ret = iio_device_register(indio_dev); 1189 if (ret < 0) { 1190 dev_err(dev, "unable to register iio device\n"); 1191 goto err_pm_cleanup; 1192 } 1193 1194 return 0; 1195 1196 err_pm_cleanup: 1197 pm_runtime_dont_use_autosuspend(dev); 1198 pm_runtime_disable(dev); 1199 err_buffer_cleanup: 1200 iio_triggered_buffer_cleanup(indio_dev); 1201 err_trigger_unregister: 1202 if (data->dready_trig) 1203 iio_trigger_unregister(data->dready_trig); 1204 if (data->motion_trig) 1205 iio_trigger_unregister(data->motion_trig); 1206 1207 return ret; 1208 } 1209 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1210 1211 void bmg160_core_remove(struct device *dev) 1212 { 1213 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1214 struct bmg160_data *data = iio_priv(indio_dev); 1215 1216 iio_device_unregister(indio_dev); 1217 1218 pm_runtime_disable(dev); 1219 pm_runtime_set_suspended(dev); 1220 pm_runtime_put_noidle(dev); 1221 1222 iio_triggered_buffer_cleanup(indio_dev); 1223 1224 if (data->dready_trig) { 1225 iio_trigger_unregister(data->dready_trig); 1226 iio_trigger_unregister(data->motion_trig); 1227 } 1228 1229 mutex_lock(&data->mutex); 1230 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1231 mutex_unlock(&data->mutex); 1232 } 1233 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1234 1235 #ifdef CONFIG_PM_SLEEP 1236 static int bmg160_suspend(struct device *dev) 1237 { 1238 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1239 struct bmg160_data *data = iio_priv(indio_dev); 1240 1241 mutex_lock(&data->mutex); 1242 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1243 mutex_unlock(&data->mutex); 1244 1245 return 0; 1246 } 1247 1248 static int bmg160_resume(struct device *dev) 1249 { 1250 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1251 struct bmg160_data *data = iio_priv(indio_dev); 1252 1253 mutex_lock(&data->mutex); 1254 if (data->dready_trigger_on || data->motion_trigger_on || 1255 data->ev_enable_state) 1256 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1257 mutex_unlock(&data->mutex); 1258 1259 return 0; 1260 } 1261 #endif 1262 1263 #ifdef CONFIG_PM 1264 static int bmg160_runtime_suspend(struct device *dev) 1265 { 1266 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1267 struct bmg160_data *data = iio_priv(indio_dev); 1268 int ret; 1269 1270 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1271 if (ret < 0) { 1272 dev_err(dev, "set mode failed\n"); 1273 return -EAGAIN; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int bmg160_runtime_resume(struct device *dev) 1280 { 1281 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1282 struct bmg160_data *data = iio_priv(indio_dev); 1283 int ret; 1284 1285 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1286 if (ret < 0) 1287 return ret; 1288 1289 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1290 1291 return 0; 1292 } 1293 #endif 1294 1295 const struct dev_pm_ops bmg160_pm_ops = { 1296 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1297 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1298 bmg160_runtime_resume, NULL) 1299 }; 1300 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1301 1302 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1303 MODULE_LICENSE("GPL v2"); 1304 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1305