1 /* 2 * BMG160 Gyro Sensor driver 3 * Copyright (c) 2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/trigger.h> 26 #include <linux/iio/events.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/regmap.h> 30 #include "bmg160.h" 31 32 #define BMG160_IRQ_NAME "bmg160_event" 33 34 #define BMG160_REG_CHIP_ID 0x00 35 #define BMG160_CHIP_ID_VAL 0x0F 36 37 #define BMG160_REG_PMU_LPW 0x11 38 #define BMG160_MODE_NORMAL 0x00 39 #define BMG160_MODE_DEEP_SUSPEND 0x20 40 #define BMG160_MODE_SUSPEND 0x80 41 42 #define BMG160_REG_RANGE 0x0F 43 44 #define BMG160_RANGE_2000DPS 0 45 #define BMG160_RANGE_1000DPS 1 46 #define BMG160_RANGE_500DPS 2 47 #define BMG160_RANGE_250DPS 3 48 #define BMG160_RANGE_125DPS 4 49 50 #define BMG160_REG_PMU_BW 0x10 51 #define BMG160_NO_FILTER 0 52 #define BMG160_DEF_BW 100 53 #define BMG160_REG_PMU_BW_RES BIT(7) 54 55 #define BMG160_GYRO_REG_RESET 0x14 56 #define BMG160_GYRO_RESET_VAL 0xb6 57 58 #define BMG160_REG_INT_MAP_0 0x17 59 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 60 61 #define BMG160_REG_INT_MAP_1 0x18 62 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 63 64 #define BMG160_REG_INT_RST_LATCH 0x21 65 #define BMG160_INT_MODE_LATCH_RESET 0x80 66 #define BMG160_INT_MODE_LATCH_INT 0x0F 67 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 68 69 #define BMG160_REG_INT_EN_0 0x15 70 #define BMG160_DATA_ENABLE_INT BIT(7) 71 72 #define BMG160_REG_INT_EN_1 0x16 73 #define BMG160_INT1_BIT_OD BIT(1) 74 75 #define BMG160_REG_XOUT_L 0x02 76 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 77 78 #define BMG160_REG_SLOPE_THRES 0x1B 79 #define BMG160_SLOPE_THRES_MASK 0x0F 80 81 #define BMG160_REG_MOTION_INTR 0x1C 82 #define BMG160_INT_MOTION_X BIT(0) 83 #define BMG160_INT_MOTION_Y BIT(1) 84 #define BMG160_INT_MOTION_Z BIT(2) 85 #define BMG160_ANY_DUR_MASK 0x30 86 #define BMG160_ANY_DUR_SHIFT 4 87 88 #define BMG160_REG_INT_STATUS_2 0x0B 89 #define BMG160_ANY_MOTION_MASK 0x07 90 #define BMG160_ANY_MOTION_BIT_X BIT(0) 91 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 92 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 93 94 #define BMG160_REG_TEMP 0x08 95 #define BMG160_TEMP_CENTER_VAL 23 96 97 #define BMG160_MAX_STARTUP_TIME_MS 80 98 99 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 100 101 struct bmg160_data { 102 struct regmap *regmap; 103 struct iio_trigger *dready_trig; 104 struct iio_trigger *motion_trig; 105 struct mutex mutex; 106 s16 buffer[8]; 107 u32 dps_range; 108 int ev_enable_state; 109 int slope_thres; 110 bool dready_trigger_on; 111 bool motion_trigger_on; 112 int irq; 113 }; 114 115 enum bmg160_axis { 116 AXIS_X, 117 AXIS_Y, 118 AXIS_Z, 119 AXIS_MAX, 120 }; 121 122 static const struct { 123 int odr; 124 int filter; 125 int bw_bits; 126 } bmg160_samp_freq_table[] = { {100, 32, 0x07}, 127 {200, 64, 0x06}, 128 {100, 12, 0x05}, 129 {200, 23, 0x04}, 130 {400, 47, 0x03}, 131 {1000, 116, 0x02}, 132 {2000, 230, 0x01} }; 133 134 static const struct { 135 int scale; 136 int dps_range; 137 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 138 { 532, BMG160_RANGE_1000DPS}, 139 { 266, BMG160_RANGE_500DPS}, 140 { 133, BMG160_RANGE_250DPS}, 141 { 66, BMG160_RANGE_125DPS} }; 142 143 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 144 { 145 struct device *dev = regmap_get_device(data->regmap); 146 int ret; 147 148 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 149 if (ret < 0) { 150 dev_err(dev, "Error writing reg_pmu_lpw\n"); 151 return ret; 152 } 153 154 return 0; 155 } 156 157 static int bmg160_convert_freq_to_bit(int val) 158 { 159 int i; 160 161 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 162 if (bmg160_samp_freq_table[i].odr == val) 163 return bmg160_samp_freq_table[i].bw_bits; 164 } 165 166 return -EINVAL; 167 } 168 169 static int bmg160_set_bw(struct bmg160_data *data, int val) 170 { 171 struct device *dev = regmap_get_device(data->regmap); 172 int ret; 173 int bw_bits; 174 175 bw_bits = bmg160_convert_freq_to_bit(val); 176 if (bw_bits < 0) 177 return bw_bits; 178 179 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 180 if (ret < 0) { 181 dev_err(dev, "Error writing reg_pmu_bw\n"); 182 return ret; 183 } 184 185 return 0; 186 } 187 188 static int bmg160_get_filter(struct bmg160_data *data, int *val) 189 { 190 struct device *dev = regmap_get_device(data->regmap); 191 int ret; 192 int i; 193 unsigned int bw_bits; 194 195 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 196 if (ret < 0) { 197 dev_err(dev, "Error reading reg_pmu_bw\n"); 198 return ret; 199 } 200 201 /* Ignore the readonly reserved bit. */ 202 bw_bits &= ~BMG160_REG_PMU_BW_RES; 203 204 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 205 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) 206 break; 207 } 208 209 *val = bmg160_samp_freq_table[i].filter; 210 211 return ret ? ret : IIO_VAL_INT; 212 } 213 214 215 static int bmg160_set_filter(struct bmg160_data *data, int val) 216 { 217 struct device *dev = regmap_get_device(data->regmap); 218 int ret; 219 int i; 220 221 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 222 if (bmg160_samp_freq_table[i].filter == val) 223 break; 224 } 225 226 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, 227 bmg160_samp_freq_table[i].bw_bits); 228 if (ret < 0) { 229 dev_err(dev, "Error writing reg_pmu_bw\n"); 230 return ret; 231 } 232 233 return 0; 234 } 235 236 static int bmg160_chip_init(struct bmg160_data *data) 237 { 238 struct device *dev = regmap_get_device(data->regmap); 239 int ret; 240 unsigned int val; 241 242 /* 243 * Reset chip to get it in a known good state. A delay of 30ms after 244 * reset is required according to the datasheet. 245 */ 246 regmap_write(data->regmap, BMG160_GYRO_REG_RESET, 247 BMG160_GYRO_RESET_VAL); 248 usleep_range(30000, 30700); 249 250 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 251 if (ret < 0) { 252 dev_err(dev, "Error reading reg_chip_id\n"); 253 return ret; 254 } 255 256 dev_dbg(dev, "Chip Id %x\n", val); 257 if (val != BMG160_CHIP_ID_VAL) { 258 dev_err(dev, "invalid chip %x\n", val); 259 return -ENODEV; 260 } 261 262 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 263 if (ret < 0) 264 return ret; 265 266 /* Wait upto 500 ms to be ready after changing mode */ 267 usleep_range(500, 1000); 268 269 /* Set Bandwidth */ 270 ret = bmg160_set_bw(data, BMG160_DEF_BW); 271 if (ret < 0) 272 return ret; 273 274 /* Set Default Range */ 275 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 276 if (ret < 0) { 277 dev_err(dev, "Error writing reg_range\n"); 278 return ret; 279 } 280 data->dps_range = BMG160_RANGE_500DPS; 281 282 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 283 if (ret < 0) { 284 dev_err(dev, "Error reading reg_slope_thres\n"); 285 return ret; 286 } 287 data->slope_thres = val; 288 289 /* Set default interrupt mode */ 290 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 291 BMG160_INT1_BIT_OD, 0); 292 if (ret < 0) { 293 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 294 return ret; 295 } 296 297 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 298 BMG160_INT_MODE_LATCH_INT | 299 BMG160_INT_MODE_LATCH_RESET); 300 if (ret < 0) { 301 dev_err(dev, 302 "Error writing reg_motion_intr\n"); 303 return ret; 304 } 305 306 return 0; 307 } 308 309 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 310 { 311 #ifdef CONFIG_PM 312 struct device *dev = regmap_get_device(data->regmap); 313 int ret; 314 315 if (on) 316 ret = pm_runtime_get_sync(dev); 317 else { 318 pm_runtime_mark_last_busy(dev); 319 ret = pm_runtime_put_autosuspend(dev); 320 } 321 322 if (ret < 0) { 323 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 324 325 if (on) 326 pm_runtime_put_noidle(dev); 327 328 return ret; 329 } 330 #endif 331 332 return 0; 333 } 334 335 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 336 bool status) 337 { 338 struct device *dev = regmap_get_device(data->regmap); 339 int ret; 340 341 /* Enable/Disable INT_MAP0 mapping */ 342 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 343 BMG160_INT_MAP_0_BIT_ANY, 344 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 345 if (ret < 0) { 346 dev_err(dev, "Error updating bits reg_int_map0\n"); 347 return ret; 348 } 349 350 /* Enable/Disable slope interrupts */ 351 if (status) { 352 /* Update slope thres */ 353 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 354 data->slope_thres); 355 if (ret < 0) { 356 dev_err(dev, "Error writing reg_slope_thres\n"); 357 return ret; 358 } 359 360 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 361 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 362 BMG160_INT_MOTION_Z); 363 if (ret < 0) { 364 dev_err(dev, "Error writing reg_motion_intr\n"); 365 return ret; 366 } 367 368 /* 369 * New data interrupt is always non-latched, 370 * which will have higher priority, so no need 371 * to set latched mode, we will be flooded anyway with INTR 372 */ 373 if (!data->dready_trigger_on) { 374 ret = regmap_write(data->regmap, 375 BMG160_REG_INT_RST_LATCH, 376 BMG160_INT_MODE_LATCH_INT | 377 BMG160_INT_MODE_LATCH_RESET); 378 if (ret < 0) { 379 dev_err(dev, "Error writing reg_rst_latch\n"); 380 return ret; 381 } 382 } 383 384 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 385 BMG160_DATA_ENABLE_INT); 386 387 } else { 388 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 389 } 390 391 if (ret < 0) { 392 dev_err(dev, "Error writing reg_int_en0\n"); 393 return ret; 394 } 395 396 return 0; 397 } 398 399 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 400 bool status) 401 { 402 struct device *dev = regmap_get_device(data->regmap); 403 int ret; 404 405 /* Enable/Disable INT_MAP1 mapping */ 406 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 407 BMG160_INT_MAP_1_BIT_NEW_DATA, 408 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 409 if (ret < 0) { 410 dev_err(dev, "Error updating bits in reg_int_map1\n"); 411 return ret; 412 } 413 414 if (status) { 415 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 416 BMG160_INT_MODE_NON_LATCH_INT | 417 BMG160_INT_MODE_LATCH_RESET); 418 if (ret < 0) { 419 dev_err(dev, "Error writing reg_rst_latch\n"); 420 return ret; 421 } 422 423 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 424 BMG160_DATA_ENABLE_INT); 425 426 } else { 427 /* Restore interrupt mode */ 428 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 429 BMG160_INT_MODE_LATCH_INT | 430 BMG160_INT_MODE_LATCH_RESET); 431 if (ret < 0) { 432 dev_err(dev, "Error writing reg_rst_latch\n"); 433 return ret; 434 } 435 436 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 437 } 438 439 if (ret < 0) { 440 dev_err(dev, "Error writing reg_int_en0\n"); 441 return ret; 442 } 443 444 return 0; 445 } 446 447 static int bmg160_get_bw(struct bmg160_data *data, int *val) 448 { 449 struct device *dev = regmap_get_device(data->regmap); 450 int i; 451 unsigned int bw_bits; 452 int ret; 453 454 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 455 if (ret < 0) { 456 dev_err(dev, "Error reading reg_pmu_bw\n"); 457 return ret; 458 } 459 460 /* Ignore the readonly reserved bit. */ 461 bw_bits &= ~BMG160_REG_PMU_BW_RES; 462 463 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 464 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { 465 *val = bmg160_samp_freq_table[i].odr; 466 return IIO_VAL_INT; 467 } 468 } 469 470 return -EINVAL; 471 } 472 473 static int bmg160_set_scale(struct bmg160_data *data, int val) 474 { 475 struct device *dev = regmap_get_device(data->regmap); 476 int ret, i; 477 478 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 479 if (bmg160_scale_table[i].scale == val) { 480 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 481 bmg160_scale_table[i].dps_range); 482 if (ret < 0) { 483 dev_err(dev, "Error writing reg_range\n"); 484 return ret; 485 } 486 data->dps_range = bmg160_scale_table[i].dps_range; 487 return 0; 488 } 489 } 490 491 return -EINVAL; 492 } 493 494 static int bmg160_get_temp(struct bmg160_data *data, int *val) 495 { 496 struct device *dev = regmap_get_device(data->regmap); 497 int ret; 498 unsigned int raw_val; 499 500 mutex_lock(&data->mutex); 501 ret = bmg160_set_power_state(data, true); 502 if (ret < 0) { 503 mutex_unlock(&data->mutex); 504 return ret; 505 } 506 507 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 508 if (ret < 0) { 509 dev_err(dev, "Error reading reg_temp\n"); 510 bmg160_set_power_state(data, false); 511 mutex_unlock(&data->mutex); 512 return ret; 513 } 514 515 *val = sign_extend32(raw_val, 7); 516 ret = bmg160_set_power_state(data, false); 517 mutex_unlock(&data->mutex); 518 if (ret < 0) 519 return ret; 520 521 return IIO_VAL_INT; 522 } 523 524 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 525 { 526 struct device *dev = regmap_get_device(data->regmap); 527 int ret; 528 __le16 raw_val; 529 530 mutex_lock(&data->mutex); 531 ret = bmg160_set_power_state(data, true); 532 if (ret < 0) { 533 mutex_unlock(&data->mutex); 534 return ret; 535 } 536 537 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 538 sizeof(raw_val)); 539 if (ret < 0) { 540 dev_err(dev, "Error reading axis %d\n", axis); 541 bmg160_set_power_state(data, false); 542 mutex_unlock(&data->mutex); 543 return ret; 544 } 545 546 *val = sign_extend32(le16_to_cpu(raw_val), 15); 547 ret = bmg160_set_power_state(data, false); 548 mutex_unlock(&data->mutex); 549 if (ret < 0) 550 return ret; 551 552 return IIO_VAL_INT; 553 } 554 555 static int bmg160_read_raw(struct iio_dev *indio_dev, 556 struct iio_chan_spec const *chan, 557 int *val, int *val2, long mask) 558 { 559 struct bmg160_data *data = iio_priv(indio_dev); 560 int ret; 561 562 switch (mask) { 563 case IIO_CHAN_INFO_RAW: 564 switch (chan->type) { 565 case IIO_TEMP: 566 return bmg160_get_temp(data, val); 567 case IIO_ANGL_VEL: 568 if (iio_buffer_enabled(indio_dev)) 569 return -EBUSY; 570 else 571 return bmg160_get_axis(data, chan->scan_index, 572 val); 573 default: 574 return -EINVAL; 575 } 576 case IIO_CHAN_INFO_OFFSET: 577 if (chan->type == IIO_TEMP) { 578 *val = BMG160_TEMP_CENTER_VAL; 579 return IIO_VAL_INT; 580 } else 581 return -EINVAL; 582 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 583 return bmg160_get_filter(data, val); 584 case IIO_CHAN_INFO_SCALE: 585 *val = 0; 586 switch (chan->type) { 587 case IIO_TEMP: 588 *val2 = 500000; 589 return IIO_VAL_INT_PLUS_MICRO; 590 case IIO_ANGL_VEL: 591 { 592 int i; 593 594 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 595 if (bmg160_scale_table[i].dps_range == 596 data->dps_range) { 597 *val2 = bmg160_scale_table[i].scale; 598 return IIO_VAL_INT_PLUS_MICRO; 599 } 600 } 601 return -EINVAL; 602 } 603 default: 604 return -EINVAL; 605 } 606 case IIO_CHAN_INFO_SAMP_FREQ: 607 *val2 = 0; 608 mutex_lock(&data->mutex); 609 ret = bmg160_get_bw(data, val); 610 mutex_unlock(&data->mutex); 611 return ret; 612 default: 613 return -EINVAL; 614 } 615 } 616 617 static int bmg160_write_raw(struct iio_dev *indio_dev, 618 struct iio_chan_spec const *chan, 619 int val, int val2, long mask) 620 { 621 struct bmg160_data *data = iio_priv(indio_dev); 622 int ret; 623 624 switch (mask) { 625 case IIO_CHAN_INFO_SAMP_FREQ: 626 mutex_lock(&data->mutex); 627 /* 628 * Section 4.2 of spec 629 * In suspend mode, the only supported operations are reading 630 * registers as well as writing to the (0x14) softreset 631 * register. Since we will be in suspend mode by default, change 632 * mode to power on for other writes. 633 */ 634 ret = bmg160_set_power_state(data, true); 635 if (ret < 0) { 636 mutex_unlock(&data->mutex); 637 return ret; 638 } 639 ret = bmg160_set_bw(data, val); 640 if (ret < 0) { 641 bmg160_set_power_state(data, false); 642 mutex_unlock(&data->mutex); 643 return ret; 644 } 645 ret = bmg160_set_power_state(data, false); 646 mutex_unlock(&data->mutex); 647 return ret; 648 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 649 if (val2) 650 return -EINVAL; 651 652 mutex_lock(&data->mutex); 653 ret = bmg160_set_power_state(data, true); 654 if (ret < 0) { 655 bmg160_set_power_state(data, false); 656 mutex_unlock(&data->mutex); 657 return ret; 658 } 659 ret = bmg160_set_filter(data, val); 660 if (ret < 0) { 661 bmg160_set_power_state(data, false); 662 mutex_unlock(&data->mutex); 663 return ret; 664 } 665 ret = bmg160_set_power_state(data, false); 666 mutex_unlock(&data->mutex); 667 return ret; 668 case IIO_CHAN_INFO_SCALE: 669 if (val) 670 return -EINVAL; 671 672 mutex_lock(&data->mutex); 673 /* Refer to comments above for the suspend mode ops */ 674 ret = bmg160_set_power_state(data, true); 675 if (ret < 0) { 676 mutex_unlock(&data->mutex); 677 return ret; 678 } 679 ret = bmg160_set_scale(data, val2); 680 if (ret < 0) { 681 bmg160_set_power_state(data, false); 682 mutex_unlock(&data->mutex); 683 return ret; 684 } 685 ret = bmg160_set_power_state(data, false); 686 mutex_unlock(&data->mutex); 687 return ret; 688 default: 689 return -EINVAL; 690 } 691 692 return -EINVAL; 693 } 694 695 static int bmg160_read_event(struct iio_dev *indio_dev, 696 const struct iio_chan_spec *chan, 697 enum iio_event_type type, 698 enum iio_event_direction dir, 699 enum iio_event_info info, 700 int *val, int *val2) 701 { 702 struct bmg160_data *data = iio_priv(indio_dev); 703 704 *val2 = 0; 705 switch (info) { 706 case IIO_EV_INFO_VALUE: 707 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 708 break; 709 default: 710 return -EINVAL; 711 } 712 713 return IIO_VAL_INT; 714 } 715 716 static int bmg160_write_event(struct iio_dev *indio_dev, 717 const struct iio_chan_spec *chan, 718 enum iio_event_type type, 719 enum iio_event_direction dir, 720 enum iio_event_info info, 721 int val, int val2) 722 { 723 struct bmg160_data *data = iio_priv(indio_dev); 724 725 switch (info) { 726 case IIO_EV_INFO_VALUE: 727 if (data->ev_enable_state) 728 return -EBUSY; 729 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 730 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 731 break; 732 default: 733 return -EINVAL; 734 } 735 736 return 0; 737 } 738 739 static int bmg160_read_event_config(struct iio_dev *indio_dev, 740 const struct iio_chan_spec *chan, 741 enum iio_event_type type, 742 enum iio_event_direction dir) 743 { 744 745 struct bmg160_data *data = iio_priv(indio_dev); 746 747 return data->ev_enable_state; 748 } 749 750 static int bmg160_write_event_config(struct iio_dev *indio_dev, 751 const struct iio_chan_spec *chan, 752 enum iio_event_type type, 753 enum iio_event_direction dir, 754 int state) 755 { 756 struct bmg160_data *data = iio_priv(indio_dev); 757 int ret; 758 759 if (state && data->ev_enable_state) 760 return 0; 761 762 mutex_lock(&data->mutex); 763 764 if (!state && data->motion_trigger_on) { 765 data->ev_enable_state = 0; 766 mutex_unlock(&data->mutex); 767 return 0; 768 } 769 /* 770 * We will expect the enable and disable to do operation in 771 * in reverse order. This will happen here anyway as our 772 * resume operation uses sync mode runtime pm calls, the 773 * suspend operation will be delayed by autosuspend delay 774 * So the disable operation will still happen in reverse of 775 * enable operation. When runtime pm is disabled the mode 776 * is always on so sequence doesn't matter 777 */ 778 ret = bmg160_set_power_state(data, state); 779 if (ret < 0) { 780 mutex_unlock(&data->mutex); 781 return ret; 782 } 783 784 ret = bmg160_setup_any_motion_interrupt(data, state); 785 if (ret < 0) { 786 bmg160_set_power_state(data, false); 787 mutex_unlock(&data->mutex); 788 return ret; 789 } 790 791 data->ev_enable_state = state; 792 mutex_unlock(&data->mutex); 793 794 return 0; 795 } 796 797 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 798 799 static IIO_CONST_ATTR(in_anglvel_scale_available, 800 "0.001065 0.000532 0.000266 0.000133 0.000066"); 801 802 static struct attribute *bmg160_attributes[] = { 803 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 804 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 805 NULL, 806 }; 807 808 static const struct attribute_group bmg160_attrs_group = { 809 .attrs = bmg160_attributes, 810 }; 811 812 static const struct iio_event_spec bmg160_event = { 813 .type = IIO_EV_TYPE_ROC, 814 .dir = IIO_EV_DIR_EITHER, 815 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 816 BIT(IIO_EV_INFO_ENABLE) 817 }; 818 819 #define BMG160_CHANNEL(_axis) { \ 820 .type = IIO_ANGL_VEL, \ 821 .modified = 1, \ 822 .channel2 = IIO_MOD_##_axis, \ 823 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 824 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 825 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 826 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 827 .scan_index = AXIS_##_axis, \ 828 .scan_type = { \ 829 .sign = 's', \ 830 .realbits = 16, \ 831 .storagebits = 16, \ 832 .endianness = IIO_LE, \ 833 }, \ 834 .event_spec = &bmg160_event, \ 835 .num_event_specs = 1 \ 836 } 837 838 static const struct iio_chan_spec bmg160_channels[] = { 839 { 840 .type = IIO_TEMP, 841 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 842 BIT(IIO_CHAN_INFO_SCALE) | 843 BIT(IIO_CHAN_INFO_OFFSET), 844 .scan_index = -1, 845 }, 846 BMG160_CHANNEL(X), 847 BMG160_CHANNEL(Y), 848 BMG160_CHANNEL(Z), 849 IIO_CHAN_SOFT_TIMESTAMP(3), 850 }; 851 852 static const struct iio_info bmg160_info = { 853 .attrs = &bmg160_attrs_group, 854 .read_raw = bmg160_read_raw, 855 .write_raw = bmg160_write_raw, 856 .read_event_value = bmg160_read_event, 857 .write_event_value = bmg160_write_event, 858 .write_event_config = bmg160_write_event_config, 859 .read_event_config = bmg160_read_event_config, 860 }; 861 862 static const unsigned long bmg160_accel_scan_masks[] = { 863 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 864 0}; 865 866 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 867 { 868 struct iio_poll_func *pf = p; 869 struct iio_dev *indio_dev = pf->indio_dev; 870 struct bmg160_data *data = iio_priv(indio_dev); 871 int ret; 872 873 mutex_lock(&data->mutex); 874 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 875 data->buffer, AXIS_MAX * 2); 876 mutex_unlock(&data->mutex); 877 if (ret < 0) 878 goto err; 879 880 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 881 pf->timestamp); 882 err: 883 iio_trigger_notify_done(indio_dev->trig); 884 885 return IRQ_HANDLED; 886 } 887 888 static int bmg160_trig_try_reen(struct iio_trigger *trig) 889 { 890 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 891 struct bmg160_data *data = iio_priv(indio_dev); 892 struct device *dev = regmap_get_device(data->regmap); 893 int ret; 894 895 /* new data interrupts don't need ack */ 896 if (data->dready_trigger_on) 897 return 0; 898 899 /* Set latched mode interrupt and clear any latched interrupt */ 900 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 901 BMG160_INT_MODE_LATCH_INT | 902 BMG160_INT_MODE_LATCH_RESET); 903 if (ret < 0) { 904 dev_err(dev, "Error writing reg_rst_latch\n"); 905 return ret; 906 } 907 908 return 0; 909 } 910 911 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 912 bool state) 913 { 914 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 915 struct bmg160_data *data = iio_priv(indio_dev); 916 int ret; 917 918 mutex_lock(&data->mutex); 919 920 if (!state && data->ev_enable_state && data->motion_trigger_on) { 921 data->motion_trigger_on = false; 922 mutex_unlock(&data->mutex); 923 return 0; 924 } 925 926 /* 927 * Refer to comment in bmg160_write_event_config for 928 * enable/disable operation order 929 */ 930 ret = bmg160_set_power_state(data, state); 931 if (ret < 0) { 932 mutex_unlock(&data->mutex); 933 return ret; 934 } 935 if (data->motion_trig == trig) 936 ret = bmg160_setup_any_motion_interrupt(data, state); 937 else 938 ret = bmg160_setup_new_data_interrupt(data, state); 939 if (ret < 0) { 940 bmg160_set_power_state(data, false); 941 mutex_unlock(&data->mutex); 942 return ret; 943 } 944 if (data->motion_trig == trig) 945 data->motion_trigger_on = state; 946 else 947 data->dready_trigger_on = state; 948 949 mutex_unlock(&data->mutex); 950 951 return 0; 952 } 953 954 static const struct iio_trigger_ops bmg160_trigger_ops = { 955 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 956 .try_reenable = bmg160_trig_try_reen, 957 }; 958 959 static irqreturn_t bmg160_event_handler(int irq, void *private) 960 { 961 struct iio_dev *indio_dev = private; 962 struct bmg160_data *data = iio_priv(indio_dev); 963 struct device *dev = regmap_get_device(data->regmap); 964 int ret; 965 int dir; 966 unsigned int val; 967 968 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 969 if (ret < 0) { 970 dev_err(dev, "Error reading reg_int_status2\n"); 971 goto ack_intr_status; 972 } 973 974 if (val & 0x08) 975 dir = IIO_EV_DIR_RISING; 976 else 977 dir = IIO_EV_DIR_FALLING; 978 979 if (val & BMG160_ANY_MOTION_BIT_X) 980 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 981 0, 982 IIO_MOD_X, 983 IIO_EV_TYPE_ROC, 984 dir), 985 iio_get_time_ns(indio_dev)); 986 if (val & BMG160_ANY_MOTION_BIT_Y) 987 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 988 0, 989 IIO_MOD_Y, 990 IIO_EV_TYPE_ROC, 991 dir), 992 iio_get_time_ns(indio_dev)); 993 if (val & BMG160_ANY_MOTION_BIT_Z) 994 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 995 0, 996 IIO_MOD_Z, 997 IIO_EV_TYPE_ROC, 998 dir), 999 iio_get_time_ns(indio_dev)); 1000 1001 ack_intr_status: 1002 if (!data->dready_trigger_on) { 1003 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 1004 BMG160_INT_MODE_LATCH_INT | 1005 BMG160_INT_MODE_LATCH_RESET); 1006 if (ret < 0) 1007 dev_err(dev, "Error writing reg_rst_latch\n"); 1008 } 1009 1010 return IRQ_HANDLED; 1011 } 1012 1013 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 1014 { 1015 struct iio_dev *indio_dev = private; 1016 struct bmg160_data *data = iio_priv(indio_dev); 1017 1018 if (data->dready_trigger_on) 1019 iio_trigger_poll(data->dready_trig); 1020 else if (data->motion_trigger_on) 1021 iio_trigger_poll(data->motion_trig); 1022 1023 if (data->ev_enable_state) 1024 return IRQ_WAKE_THREAD; 1025 else 1026 return IRQ_HANDLED; 1027 1028 } 1029 1030 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 1031 { 1032 struct bmg160_data *data = iio_priv(indio_dev); 1033 1034 return bmg160_set_power_state(data, true); 1035 } 1036 1037 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 1038 { 1039 struct bmg160_data *data = iio_priv(indio_dev); 1040 1041 return bmg160_set_power_state(data, false); 1042 } 1043 1044 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 1045 .preenable = bmg160_buffer_preenable, 1046 .postenable = iio_triggered_buffer_postenable, 1047 .predisable = iio_triggered_buffer_predisable, 1048 .postdisable = bmg160_buffer_postdisable, 1049 }; 1050 1051 static const char *bmg160_match_acpi_device(struct device *dev) 1052 { 1053 const struct acpi_device_id *id; 1054 1055 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1056 if (!id) 1057 return NULL; 1058 1059 return dev_name(dev); 1060 } 1061 1062 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 1063 const char *name) 1064 { 1065 struct bmg160_data *data; 1066 struct iio_dev *indio_dev; 1067 int ret; 1068 1069 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1070 if (!indio_dev) 1071 return -ENOMEM; 1072 1073 data = iio_priv(indio_dev); 1074 dev_set_drvdata(dev, indio_dev); 1075 data->irq = irq; 1076 data->regmap = regmap; 1077 1078 ret = bmg160_chip_init(data); 1079 if (ret < 0) 1080 return ret; 1081 1082 mutex_init(&data->mutex); 1083 1084 if (ACPI_HANDLE(dev)) 1085 name = bmg160_match_acpi_device(dev); 1086 1087 indio_dev->dev.parent = dev; 1088 indio_dev->channels = bmg160_channels; 1089 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1090 indio_dev->name = name; 1091 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 1092 indio_dev->modes = INDIO_DIRECT_MODE; 1093 indio_dev->info = &bmg160_info; 1094 1095 if (data->irq > 0) { 1096 ret = devm_request_threaded_irq(dev, 1097 data->irq, 1098 bmg160_data_rdy_trig_poll, 1099 bmg160_event_handler, 1100 IRQF_TRIGGER_RISING, 1101 BMG160_IRQ_NAME, 1102 indio_dev); 1103 if (ret) 1104 return ret; 1105 1106 data->dready_trig = devm_iio_trigger_alloc(dev, 1107 "%s-dev%d", 1108 indio_dev->name, 1109 indio_dev->id); 1110 if (!data->dready_trig) 1111 return -ENOMEM; 1112 1113 data->motion_trig = devm_iio_trigger_alloc(dev, 1114 "%s-any-motion-dev%d", 1115 indio_dev->name, 1116 indio_dev->id); 1117 if (!data->motion_trig) 1118 return -ENOMEM; 1119 1120 data->dready_trig->dev.parent = dev; 1121 data->dready_trig->ops = &bmg160_trigger_ops; 1122 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1123 ret = iio_trigger_register(data->dready_trig); 1124 if (ret) 1125 return ret; 1126 1127 data->motion_trig->dev.parent = dev; 1128 data->motion_trig->ops = &bmg160_trigger_ops; 1129 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1130 ret = iio_trigger_register(data->motion_trig); 1131 if (ret) { 1132 data->motion_trig = NULL; 1133 goto err_trigger_unregister; 1134 } 1135 } 1136 1137 ret = iio_triggered_buffer_setup(indio_dev, 1138 iio_pollfunc_store_time, 1139 bmg160_trigger_handler, 1140 &bmg160_buffer_setup_ops); 1141 if (ret < 0) { 1142 dev_err(dev, 1143 "iio triggered buffer setup failed\n"); 1144 goto err_trigger_unregister; 1145 } 1146 1147 ret = pm_runtime_set_active(dev); 1148 if (ret) 1149 goto err_buffer_cleanup; 1150 1151 pm_runtime_enable(dev); 1152 pm_runtime_set_autosuspend_delay(dev, 1153 BMG160_AUTO_SUSPEND_DELAY_MS); 1154 pm_runtime_use_autosuspend(dev); 1155 1156 ret = iio_device_register(indio_dev); 1157 if (ret < 0) { 1158 dev_err(dev, "unable to register iio device\n"); 1159 goto err_buffer_cleanup; 1160 } 1161 1162 return 0; 1163 1164 err_buffer_cleanup: 1165 iio_triggered_buffer_cleanup(indio_dev); 1166 err_trigger_unregister: 1167 if (data->dready_trig) 1168 iio_trigger_unregister(data->dready_trig); 1169 if (data->motion_trig) 1170 iio_trigger_unregister(data->motion_trig); 1171 1172 return ret; 1173 } 1174 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1175 1176 void bmg160_core_remove(struct device *dev) 1177 { 1178 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1179 struct bmg160_data *data = iio_priv(indio_dev); 1180 1181 iio_device_unregister(indio_dev); 1182 1183 pm_runtime_disable(dev); 1184 pm_runtime_set_suspended(dev); 1185 pm_runtime_put_noidle(dev); 1186 1187 iio_triggered_buffer_cleanup(indio_dev); 1188 1189 if (data->dready_trig) { 1190 iio_trigger_unregister(data->dready_trig); 1191 iio_trigger_unregister(data->motion_trig); 1192 } 1193 1194 mutex_lock(&data->mutex); 1195 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1196 mutex_unlock(&data->mutex); 1197 } 1198 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1199 1200 #ifdef CONFIG_PM_SLEEP 1201 static int bmg160_suspend(struct device *dev) 1202 { 1203 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1204 struct bmg160_data *data = iio_priv(indio_dev); 1205 1206 mutex_lock(&data->mutex); 1207 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1208 mutex_unlock(&data->mutex); 1209 1210 return 0; 1211 } 1212 1213 static int bmg160_resume(struct device *dev) 1214 { 1215 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1216 struct bmg160_data *data = iio_priv(indio_dev); 1217 1218 mutex_lock(&data->mutex); 1219 if (data->dready_trigger_on || data->motion_trigger_on || 1220 data->ev_enable_state) 1221 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1222 mutex_unlock(&data->mutex); 1223 1224 return 0; 1225 } 1226 #endif 1227 1228 #ifdef CONFIG_PM 1229 static int bmg160_runtime_suspend(struct device *dev) 1230 { 1231 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1232 struct bmg160_data *data = iio_priv(indio_dev); 1233 int ret; 1234 1235 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1236 if (ret < 0) { 1237 dev_err(dev, "set mode failed\n"); 1238 return -EAGAIN; 1239 } 1240 1241 return 0; 1242 } 1243 1244 static int bmg160_runtime_resume(struct device *dev) 1245 { 1246 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1247 struct bmg160_data *data = iio_priv(indio_dev); 1248 int ret; 1249 1250 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1251 if (ret < 0) 1252 return ret; 1253 1254 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1255 1256 return 0; 1257 } 1258 #endif 1259 1260 const struct dev_pm_ops bmg160_pm_ops = { 1261 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1262 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1263 bmg160_runtime_resume, NULL) 1264 }; 1265 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1266 1267 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1268 MODULE_LICENSE("GPL v2"); 1269 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1270