1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BMG160 Gyro Sensor driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/acpi.h> 12 #include <linux/pm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/iio/triggered_buffer.h> 21 #include <linux/regmap.h> 22 #include "bmg160.h" 23 24 #define BMG160_IRQ_NAME "bmg160_event" 25 26 #define BMG160_REG_CHIP_ID 0x00 27 #define BMG160_CHIP_ID_VAL 0x0F 28 29 #define BMG160_REG_PMU_LPW 0x11 30 #define BMG160_MODE_NORMAL 0x00 31 #define BMG160_MODE_DEEP_SUSPEND 0x20 32 #define BMG160_MODE_SUSPEND 0x80 33 34 #define BMG160_REG_RANGE 0x0F 35 36 #define BMG160_RANGE_2000DPS 0 37 #define BMG160_RANGE_1000DPS 1 38 #define BMG160_RANGE_500DPS 2 39 #define BMG160_RANGE_250DPS 3 40 #define BMG160_RANGE_125DPS 4 41 42 #define BMG160_REG_PMU_BW 0x10 43 #define BMG160_NO_FILTER 0 44 #define BMG160_DEF_BW 100 45 #define BMG160_REG_PMU_BW_RES BIT(7) 46 47 #define BMG160_GYRO_REG_RESET 0x14 48 #define BMG160_GYRO_RESET_VAL 0xb6 49 50 #define BMG160_REG_INT_MAP_0 0x17 51 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 52 53 #define BMG160_REG_INT_MAP_1 0x18 54 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 55 56 #define BMG160_REG_INT_RST_LATCH 0x21 57 #define BMG160_INT_MODE_LATCH_RESET 0x80 58 #define BMG160_INT_MODE_LATCH_INT 0x0F 59 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 60 61 #define BMG160_REG_INT_EN_0 0x15 62 #define BMG160_DATA_ENABLE_INT BIT(7) 63 64 #define BMG160_REG_INT_EN_1 0x16 65 #define BMG160_INT1_BIT_OD BIT(1) 66 67 #define BMG160_REG_XOUT_L 0x02 68 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 69 70 #define BMG160_REG_SLOPE_THRES 0x1B 71 #define BMG160_SLOPE_THRES_MASK 0x0F 72 73 #define BMG160_REG_MOTION_INTR 0x1C 74 #define BMG160_INT_MOTION_X BIT(0) 75 #define BMG160_INT_MOTION_Y BIT(1) 76 #define BMG160_INT_MOTION_Z BIT(2) 77 #define BMG160_ANY_DUR_MASK 0x30 78 #define BMG160_ANY_DUR_SHIFT 4 79 80 #define BMG160_REG_INT_STATUS_2 0x0B 81 #define BMG160_ANY_MOTION_MASK 0x07 82 #define BMG160_ANY_MOTION_BIT_X BIT(0) 83 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 84 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 85 86 #define BMG160_REG_TEMP 0x08 87 #define BMG160_TEMP_CENTER_VAL 23 88 89 #define BMG160_MAX_STARTUP_TIME_MS 80 90 91 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 92 93 struct bmg160_data { 94 struct regmap *regmap; 95 struct iio_trigger *dready_trig; 96 struct iio_trigger *motion_trig; 97 struct iio_mount_matrix orientation; 98 struct mutex mutex; 99 s16 buffer[8]; 100 u32 dps_range; 101 int ev_enable_state; 102 int slope_thres; 103 bool dready_trigger_on; 104 bool motion_trigger_on; 105 int irq; 106 }; 107 108 enum bmg160_axis { 109 AXIS_X, 110 AXIS_Y, 111 AXIS_Z, 112 AXIS_MAX, 113 }; 114 115 static const struct { 116 int odr; 117 int filter; 118 int bw_bits; 119 } bmg160_samp_freq_table[] = { {100, 32, 0x07}, 120 {200, 64, 0x06}, 121 {100, 12, 0x05}, 122 {200, 23, 0x04}, 123 {400, 47, 0x03}, 124 {1000, 116, 0x02}, 125 {2000, 230, 0x01} }; 126 127 static const struct { 128 int scale; 129 int dps_range; 130 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 131 { 532, BMG160_RANGE_1000DPS}, 132 { 266, BMG160_RANGE_500DPS}, 133 { 133, BMG160_RANGE_250DPS}, 134 { 66, BMG160_RANGE_125DPS} }; 135 136 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 137 { 138 struct device *dev = regmap_get_device(data->regmap); 139 int ret; 140 141 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 142 if (ret < 0) { 143 dev_err(dev, "Error writing reg_pmu_lpw\n"); 144 return ret; 145 } 146 147 return 0; 148 } 149 150 static int bmg160_convert_freq_to_bit(int val) 151 { 152 int i; 153 154 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 155 if (bmg160_samp_freq_table[i].odr == val) 156 return bmg160_samp_freq_table[i].bw_bits; 157 } 158 159 return -EINVAL; 160 } 161 162 static int bmg160_set_bw(struct bmg160_data *data, int val) 163 { 164 struct device *dev = regmap_get_device(data->regmap); 165 int ret; 166 int bw_bits; 167 168 bw_bits = bmg160_convert_freq_to_bit(val); 169 if (bw_bits < 0) 170 return bw_bits; 171 172 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 173 if (ret < 0) { 174 dev_err(dev, "Error writing reg_pmu_bw\n"); 175 return ret; 176 } 177 178 return 0; 179 } 180 181 static int bmg160_get_filter(struct bmg160_data *data, int *val) 182 { 183 struct device *dev = regmap_get_device(data->regmap); 184 int ret; 185 int i; 186 unsigned int bw_bits; 187 188 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 189 if (ret < 0) { 190 dev_err(dev, "Error reading reg_pmu_bw\n"); 191 return ret; 192 } 193 194 /* Ignore the readonly reserved bit. */ 195 bw_bits &= ~BMG160_REG_PMU_BW_RES; 196 197 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 198 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) 199 break; 200 } 201 202 *val = bmg160_samp_freq_table[i].filter; 203 204 return ret ? ret : IIO_VAL_INT; 205 } 206 207 208 static int bmg160_set_filter(struct bmg160_data *data, int val) 209 { 210 struct device *dev = regmap_get_device(data->regmap); 211 int ret; 212 int i; 213 214 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 215 if (bmg160_samp_freq_table[i].filter == val) 216 break; 217 } 218 219 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, 220 bmg160_samp_freq_table[i].bw_bits); 221 if (ret < 0) { 222 dev_err(dev, "Error writing reg_pmu_bw\n"); 223 return ret; 224 } 225 226 return 0; 227 } 228 229 static int bmg160_chip_init(struct bmg160_data *data) 230 { 231 struct device *dev = regmap_get_device(data->regmap); 232 int ret; 233 unsigned int val; 234 235 /* 236 * Reset chip to get it in a known good state. A delay of 30ms after 237 * reset is required according to the datasheet. 238 */ 239 regmap_write(data->regmap, BMG160_GYRO_REG_RESET, 240 BMG160_GYRO_RESET_VAL); 241 usleep_range(30000, 30700); 242 243 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 244 if (ret < 0) { 245 dev_err(dev, "Error reading reg_chip_id\n"); 246 return ret; 247 } 248 249 dev_dbg(dev, "Chip Id %x\n", val); 250 if (val != BMG160_CHIP_ID_VAL) { 251 dev_err(dev, "invalid chip %x\n", val); 252 return -ENODEV; 253 } 254 255 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 256 if (ret < 0) 257 return ret; 258 259 /* Wait upto 500 ms to be ready after changing mode */ 260 usleep_range(500, 1000); 261 262 /* Set Bandwidth */ 263 ret = bmg160_set_bw(data, BMG160_DEF_BW); 264 if (ret < 0) 265 return ret; 266 267 /* Set Default Range */ 268 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 269 if (ret < 0) { 270 dev_err(dev, "Error writing reg_range\n"); 271 return ret; 272 } 273 data->dps_range = BMG160_RANGE_500DPS; 274 275 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 276 if (ret < 0) { 277 dev_err(dev, "Error reading reg_slope_thres\n"); 278 return ret; 279 } 280 data->slope_thres = val; 281 282 /* Set default interrupt mode */ 283 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 284 BMG160_INT1_BIT_OD, 0); 285 if (ret < 0) { 286 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 287 return ret; 288 } 289 290 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 291 BMG160_INT_MODE_LATCH_INT | 292 BMG160_INT_MODE_LATCH_RESET); 293 if (ret < 0) { 294 dev_err(dev, 295 "Error writing reg_motion_intr\n"); 296 return ret; 297 } 298 299 return 0; 300 } 301 302 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 303 { 304 #ifdef CONFIG_PM 305 struct device *dev = regmap_get_device(data->regmap); 306 int ret; 307 308 if (on) 309 ret = pm_runtime_get_sync(dev); 310 else { 311 pm_runtime_mark_last_busy(dev); 312 ret = pm_runtime_put_autosuspend(dev); 313 } 314 315 if (ret < 0) { 316 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 317 318 if (on) 319 pm_runtime_put_noidle(dev); 320 321 return ret; 322 } 323 #endif 324 325 return 0; 326 } 327 328 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 329 bool status) 330 { 331 struct device *dev = regmap_get_device(data->regmap); 332 int ret; 333 334 /* Enable/Disable INT_MAP0 mapping */ 335 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 336 BMG160_INT_MAP_0_BIT_ANY, 337 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 338 if (ret < 0) { 339 dev_err(dev, "Error updating bits reg_int_map0\n"); 340 return ret; 341 } 342 343 /* Enable/Disable slope interrupts */ 344 if (status) { 345 /* Update slope thres */ 346 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 347 data->slope_thres); 348 if (ret < 0) { 349 dev_err(dev, "Error writing reg_slope_thres\n"); 350 return ret; 351 } 352 353 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 354 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 355 BMG160_INT_MOTION_Z); 356 if (ret < 0) { 357 dev_err(dev, "Error writing reg_motion_intr\n"); 358 return ret; 359 } 360 361 /* 362 * New data interrupt is always non-latched, 363 * which will have higher priority, so no need 364 * to set latched mode, we will be flooded anyway with INTR 365 */ 366 if (!data->dready_trigger_on) { 367 ret = regmap_write(data->regmap, 368 BMG160_REG_INT_RST_LATCH, 369 BMG160_INT_MODE_LATCH_INT | 370 BMG160_INT_MODE_LATCH_RESET); 371 if (ret < 0) { 372 dev_err(dev, "Error writing reg_rst_latch\n"); 373 return ret; 374 } 375 } 376 377 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 378 BMG160_DATA_ENABLE_INT); 379 380 } else { 381 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 382 } 383 384 if (ret < 0) { 385 dev_err(dev, "Error writing reg_int_en0\n"); 386 return ret; 387 } 388 389 return 0; 390 } 391 392 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 393 bool status) 394 { 395 struct device *dev = regmap_get_device(data->regmap); 396 int ret; 397 398 /* Enable/Disable INT_MAP1 mapping */ 399 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 400 BMG160_INT_MAP_1_BIT_NEW_DATA, 401 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 402 if (ret < 0) { 403 dev_err(dev, "Error updating bits in reg_int_map1\n"); 404 return ret; 405 } 406 407 if (status) { 408 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 409 BMG160_INT_MODE_NON_LATCH_INT | 410 BMG160_INT_MODE_LATCH_RESET); 411 if (ret < 0) { 412 dev_err(dev, "Error writing reg_rst_latch\n"); 413 return ret; 414 } 415 416 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 417 BMG160_DATA_ENABLE_INT); 418 419 } else { 420 /* Restore interrupt mode */ 421 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 422 BMG160_INT_MODE_LATCH_INT | 423 BMG160_INT_MODE_LATCH_RESET); 424 if (ret < 0) { 425 dev_err(dev, "Error writing reg_rst_latch\n"); 426 return ret; 427 } 428 429 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 430 } 431 432 if (ret < 0) { 433 dev_err(dev, "Error writing reg_int_en0\n"); 434 return ret; 435 } 436 437 return 0; 438 } 439 440 static int bmg160_get_bw(struct bmg160_data *data, int *val) 441 { 442 struct device *dev = regmap_get_device(data->regmap); 443 int i; 444 unsigned int bw_bits; 445 int ret; 446 447 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 448 if (ret < 0) { 449 dev_err(dev, "Error reading reg_pmu_bw\n"); 450 return ret; 451 } 452 453 /* Ignore the readonly reserved bit. */ 454 bw_bits &= ~BMG160_REG_PMU_BW_RES; 455 456 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 457 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { 458 *val = bmg160_samp_freq_table[i].odr; 459 return IIO_VAL_INT; 460 } 461 } 462 463 return -EINVAL; 464 } 465 466 static int bmg160_set_scale(struct bmg160_data *data, int val) 467 { 468 struct device *dev = regmap_get_device(data->regmap); 469 int ret, i; 470 471 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 472 if (bmg160_scale_table[i].scale == val) { 473 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 474 bmg160_scale_table[i].dps_range); 475 if (ret < 0) { 476 dev_err(dev, "Error writing reg_range\n"); 477 return ret; 478 } 479 data->dps_range = bmg160_scale_table[i].dps_range; 480 return 0; 481 } 482 } 483 484 return -EINVAL; 485 } 486 487 static int bmg160_get_temp(struct bmg160_data *data, int *val) 488 { 489 struct device *dev = regmap_get_device(data->regmap); 490 int ret; 491 unsigned int raw_val; 492 493 mutex_lock(&data->mutex); 494 ret = bmg160_set_power_state(data, true); 495 if (ret < 0) { 496 mutex_unlock(&data->mutex); 497 return ret; 498 } 499 500 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 501 if (ret < 0) { 502 dev_err(dev, "Error reading reg_temp\n"); 503 bmg160_set_power_state(data, false); 504 mutex_unlock(&data->mutex); 505 return ret; 506 } 507 508 *val = sign_extend32(raw_val, 7); 509 ret = bmg160_set_power_state(data, false); 510 mutex_unlock(&data->mutex); 511 if (ret < 0) 512 return ret; 513 514 return IIO_VAL_INT; 515 } 516 517 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 518 { 519 struct device *dev = regmap_get_device(data->regmap); 520 int ret; 521 __le16 raw_val; 522 523 mutex_lock(&data->mutex); 524 ret = bmg160_set_power_state(data, true); 525 if (ret < 0) { 526 mutex_unlock(&data->mutex); 527 return ret; 528 } 529 530 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 531 sizeof(raw_val)); 532 if (ret < 0) { 533 dev_err(dev, "Error reading axis %d\n", axis); 534 bmg160_set_power_state(data, false); 535 mutex_unlock(&data->mutex); 536 return ret; 537 } 538 539 *val = sign_extend32(le16_to_cpu(raw_val), 15); 540 ret = bmg160_set_power_state(data, false); 541 mutex_unlock(&data->mutex); 542 if (ret < 0) 543 return ret; 544 545 return IIO_VAL_INT; 546 } 547 548 static int bmg160_read_raw(struct iio_dev *indio_dev, 549 struct iio_chan_spec const *chan, 550 int *val, int *val2, long mask) 551 { 552 struct bmg160_data *data = iio_priv(indio_dev); 553 int ret; 554 555 switch (mask) { 556 case IIO_CHAN_INFO_RAW: 557 switch (chan->type) { 558 case IIO_TEMP: 559 return bmg160_get_temp(data, val); 560 case IIO_ANGL_VEL: 561 if (iio_buffer_enabled(indio_dev)) 562 return -EBUSY; 563 else 564 return bmg160_get_axis(data, chan->scan_index, 565 val); 566 default: 567 return -EINVAL; 568 } 569 case IIO_CHAN_INFO_OFFSET: 570 if (chan->type == IIO_TEMP) { 571 *val = BMG160_TEMP_CENTER_VAL; 572 return IIO_VAL_INT; 573 } else 574 return -EINVAL; 575 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 576 return bmg160_get_filter(data, val); 577 case IIO_CHAN_INFO_SCALE: 578 switch (chan->type) { 579 case IIO_TEMP: 580 *val = 500; 581 return IIO_VAL_INT; 582 case IIO_ANGL_VEL: 583 { 584 int i; 585 586 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 587 if (bmg160_scale_table[i].dps_range == 588 data->dps_range) { 589 *val = 0; 590 *val2 = bmg160_scale_table[i].scale; 591 return IIO_VAL_INT_PLUS_MICRO; 592 } 593 } 594 return -EINVAL; 595 } 596 default: 597 return -EINVAL; 598 } 599 case IIO_CHAN_INFO_SAMP_FREQ: 600 *val2 = 0; 601 mutex_lock(&data->mutex); 602 ret = bmg160_get_bw(data, val); 603 mutex_unlock(&data->mutex); 604 return ret; 605 default: 606 return -EINVAL; 607 } 608 } 609 610 static int bmg160_write_raw(struct iio_dev *indio_dev, 611 struct iio_chan_spec const *chan, 612 int val, int val2, long mask) 613 { 614 struct bmg160_data *data = iio_priv(indio_dev); 615 int ret; 616 617 switch (mask) { 618 case IIO_CHAN_INFO_SAMP_FREQ: 619 mutex_lock(&data->mutex); 620 /* 621 * Section 4.2 of spec 622 * In suspend mode, the only supported operations are reading 623 * registers as well as writing to the (0x14) softreset 624 * register. Since we will be in suspend mode by default, change 625 * mode to power on for other writes. 626 */ 627 ret = bmg160_set_power_state(data, true); 628 if (ret < 0) { 629 mutex_unlock(&data->mutex); 630 return ret; 631 } 632 ret = bmg160_set_bw(data, val); 633 if (ret < 0) { 634 bmg160_set_power_state(data, false); 635 mutex_unlock(&data->mutex); 636 return ret; 637 } 638 ret = bmg160_set_power_state(data, false); 639 mutex_unlock(&data->mutex); 640 return ret; 641 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 642 if (val2) 643 return -EINVAL; 644 645 mutex_lock(&data->mutex); 646 ret = bmg160_set_power_state(data, true); 647 if (ret < 0) { 648 bmg160_set_power_state(data, false); 649 mutex_unlock(&data->mutex); 650 return ret; 651 } 652 ret = bmg160_set_filter(data, val); 653 if (ret < 0) { 654 bmg160_set_power_state(data, false); 655 mutex_unlock(&data->mutex); 656 return ret; 657 } 658 ret = bmg160_set_power_state(data, false); 659 mutex_unlock(&data->mutex); 660 return ret; 661 case IIO_CHAN_INFO_SCALE: 662 if (val) 663 return -EINVAL; 664 665 mutex_lock(&data->mutex); 666 /* Refer to comments above for the suspend mode ops */ 667 ret = bmg160_set_power_state(data, true); 668 if (ret < 0) { 669 mutex_unlock(&data->mutex); 670 return ret; 671 } 672 ret = bmg160_set_scale(data, val2); 673 if (ret < 0) { 674 bmg160_set_power_state(data, false); 675 mutex_unlock(&data->mutex); 676 return ret; 677 } 678 ret = bmg160_set_power_state(data, false); 679 mutex_unlock(&data->mutex); 680 return ret; 681 default: 682 return -EINVAL; 683 } 684 685 return -EINVAL; 686 } 687 688 static int bmg160_read_event(struct iio_dev *indio_dev, 689 const struct iio_chan_spec *chan, 690 enum iio_event_type type, 691 enum iio_event_direction dir, 692 enum iio_event_info info, 693 int *val, int *val2) 694 { 695 struct bmg160_data *data = iio_priv(indio_dev); 696 697 *val2 = 0; 698 switch (info) { 699 case IIO_EV_INFO_VALUE: 700 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 701 break; 702 default: 703 return -EINVAL; 704 } 705 706 return IIO_VAL_INT; 707 } 708 709 static int bmg160_write_event(struct iio_dev *indio_dev, 710 const struct iio_chan_spec *chan, 711 enum iio_event_type type, 712 enum iio_event_direction dir, 713 enum iio_event_info info, 714 int val, int val2) 715 { 716 struct bmg160_data *data = iio_priv(indio_dev); 717 718 switch (info) { 719 case IIO_EV_INFO_VALUE: 720 if (data->ev_enable_state) 721 return -EBUSY; 722 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 723 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 724 break; 725 default: 726 return -EINVAL; 727 } 728 729 return 0; 730 } 731 732 static int bmg160_read_event_config(struct iio_dev *indio_dev, 733 const struct iio_chan_spec *chan, 734 enum iio_event_type type, 735 enum iio_event_direction dir) 736 { 737 738 struct bmg160_data *data = iio_priv(indio_dev); 739 740 return data->ev_enable_state; 741 } 742 743 static int bmg160_write_event_config(struct iio_dev *indio_dev, 744 const struct iio_chan_spec *chan, 745 enum iio_event_type type, 746 enum iio_event_direction dir, 747 int state) 748 { 749 struct bmg160_data *data = iio_priv(indio_dev); 750 int ret; 751 752 if (state && data->ev_enable_state) 753 return 0; 754 755 mutex_lock(&data->mutex); 756 757 if (!state && data->motion_trigger_on) { 758 data->ev_enable_state = 0; 759 mutex_unlock(&data->mutex); 760 return 0; 761 } 762 /* 763 * We will expect the enable and disable to do operation in 764 * in reverse order. This will happen here anyway as our 765 * resume operation uses sync mode runtime pm calls, the 766 * suspend operation will be delayed by autosuspend delay 767 * So the disable operation will still happen in reverse of 768 * enable operation. When runtime pm is disabled the mode 769 * is always on so sequence doesn't matter 770 */ 771 ret = bmg160_set_power_state(data, state); 772 if (ret < 0) { 773 mutex_unlock(&data->mutex); 774 return ret; 775 } 776 777 ret = bmg160_setup_any_motion_interrupt(data, state); 778 if (ret < 0) { 779 bmg160_set_power_state(data, false); 780 mutex_unlock(&data->mutex); 781 return ret; 782 } 783 784 data->ev_enable_state = state; 785 mutex_unlock(&data->mutex); 786 787 return 0; 788 } 789 790 static const struct iio_mount_matrix * 791 bmg160_get_mount_matrix(const struct iio_dev *indio_dev, 792 const struct iio_chan_spec *chan) 793 { 794 struct bmg160_data *data = iio_priv(indio_dev); 795 796 return &data->orientation; 797 } 798 799 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = { 800 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix), 801 { } 802 }; 803 804 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 805 806 static IIO_CONST_ATTR(in_anglvel_scale_available, 807 "0.001065 0.000532 0.000266 0.000133 0.000066"); 808 809 static struct attribute *bmg160_attributes[] = { 810 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 811 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 812 NULL, 813 }; 814 815 static const struct attribute_group bmg160_attrs_group = { 816 .attrs = bmg160_attributes, 817 }; 818 819 static const struct iio_event_spec bmg160_event = { 820 .type = IIO_EV_TYPE_ROC, 821 .dir = IIO_EV_DIR_EITHER, 822 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 823 BIT(IIO_EV_INFO_ENABLE) 824 }; 825 826 #define BMG160_CHANNEL(_axis) { \ 827 .type = IIO_ANGL_VEL, \ 828 .modified = 1, \ 829 .channel2 = IIO_MOD_##_axis, \ 830 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 831 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 832 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 833 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 834 .scan_index = AXIS_##_axis, \ 835 .scan_type = { \ 836 .sign = 's', \ 837 .realbits = 16, \ 838 .storagebits = 16, \ 839 .endianness = IIO_LE, \ 840 }, \ 841 .ext_info = bmg160_ext_info, \ 842 .event_spec = &bmg160_event, \ 843 .num_event_specs = 1 \ 844 } 845 846 static const struct iio_chan_spec bmg160_channels[] = { 847 { 848 .type = IIO_TEMP, 849 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 850 BIT(IIO_CHAN_INFO_SCALE) | 851 BIT(IIO_CHAN_INFO_OFFSET), 852 .scan_index = -1, 853 }, 854 BMG160_CHANNEL(X), 855 BMG160_CHANNEL(Y), 856 BMG160_CHANNEL(Z), 857 IIO_CHAN_SOFT_TIMESTAMP(3), 858 }; 859 860 static const struct iio_info bmg160_info = { 861 .attrs = &bmg160_attrs_group, 862 .read_raw = bmg160_read_raw, 863 .write_raw = bmg160_write_raw, 864 .read_event_value = bmg160_read_event, 865 .write_event_value = bmg160_write_event, 866 .write_event_config = bmg160_write_event_config, 867 .read_event_config = bmg160_read_event_config, 868 }; 869 870 static const unsigned long bmg160_accel_scan_masks[] = { 871 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 872 0}; 873 874 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 875 { 876 struct iio_poll_func *pf = p; 877 struct iio_dev *indio_dev = pf->indio_dev; 878 struct bmg160_data *data = iio_priv(indio_dev); 879 int ret; 880 881 mutex_lock(&data->mutex); 882 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 883 data->buffer, AXIS_MAX * 2); 884 mutex_unlock(&data->mutex); 885 if (ret < 0) 886 goto err; 887 888 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 889 pf->timestamp); 890 err: 891 iio_trigger_notify_done(indio_dev->trig); 892 893 return IRQ_HANDLED; 894 } 895 896 static void bmg160_trig_reen(struct iio_trigger *trig) 897 { 898 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 899 struct bmg160_data *data = iio_priv(indio_dev); 900 struct device *dev = regmap_get_device(data->regmap); 901 int ret; 902 903 /* new data interrupts don't need ack */ 904 if (data->dready_trigger_on) 905 return; 906 907 /* Set latched mode interrupt and clear any latched interrupt */ 908 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 909 BMG160_INT_MODE_LATCH_INT | 910 BMG160_INT_MODE_LATCH_RESET); 911 if (ret < 0) 912 dev_err(dev, "Error writing reg_rst_latch\n"); 913 } 914 915 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 916 bool state) 917 { 918 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 919 struct bmg160_data *data = iio_priv(indio_dev); 920 int ret; 921 922 mutex_lock(&data->mutex); 923 924 if (!state && data->ev_enable_state && data->motion_trigger_on) { 925 data->motion_trigger_on = false; 926 mutex_unlock(&data->mutex); 927 return 0; 928 } 929 930 /* 931 * Refer to comment in bmg160_write_event_config for 932 * enable/disable operation order 933 */ 934 ret = bmg160_set_power_state(data, state); 935 if (ret < 0) { 936 mutex_unlock(&data->mutex); 937 return ret; 938 } 939 if (data->motion_trig == trig) 940 ret = bmg160_setup_any_motion_interrupt(data, state); 941 else 942 ret = bmg160_setup_new_data_interrupt(data, state); 943 if (ret < 0) { 944 bmg160_set_power_state(data, false); 945 mutex_unlock(&data->mutex); 946 return ret; 947 } 948 if (data->motion_trig == trig) 949 data->motion_trigger_on = state; 950 else 951 data->dready_trigger_on = state; 952 953 mutex_unlock(&data->mutex); 954 955 return 0; 956 } 957 958 static const struct iio_trigger_ops bmg160_trigger_ops = { 959 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 960 .reenable = bmg160_trig_reen, 961 }; 962 963 static irqreturn_t bmg160_event_handler(int irq, void *private) 964 { 965 struct iio_dev *indio_dev = private; 966 struct bmg160_data *data = iio_priv(indio_dev); 967 struct device *dev = regmap_get_device(data->regmap); 968 int ret; 969 int dir; 970 unsigned int val; 971 972 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 973 if (ret < 0) { 974 dev_err(dev, "Error reading reg_int_status2\n"); 975 goto ack_intr_status; 976 } 977 978 if (val & 0x08) 979 dir = IIO_EV_DIR_RISING; 980 else 981 dir = IIO_EV_DIR_FALLING; 982 983 if (val & BMG160_ANY_MOTION_BIT_X) 984 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 985 0, 986 IIO_MOD_X, 987 IIO_EV_TYPE_ROC, 988 dir), 989 iio_get_time_ns(indio_dev)); 990 if (val & BMG160_ANY_MOTION_BIT_Y) 991 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 992 0, 993 IIO_MOD_Y, 994 IIO_EV_TYPE_ROC, 995 dir), 996 iio_get_time_ns(indio_dev)); 997 if (val & BMG160_ANY_MOTION_BIT_Z) 998 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 999 0, 1000 IIO_MOD_Z, 1001 IIO_EV_TYPE_ROC, 1002 dir), 1003 iio_get_time_ns(indio_dev)); 1004 1005 ack_intr_status: 1006 if (!data->dready_trigger_on) { 1007 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 1008 BMG160_INT_MODE_LATCH_INT | 1009 BMG160_INT_MODE_LATCH_RESET); 1010 if (ret < 0) 1011 dev_err(dev, "Error writing reg_rst_latch\n"); 1012 } 1013 1014 return IRQ_HANDLED; 1015 } 1016 1017 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 1018 { 1019 struct iio_dev *indio_dev = private; 1020 struct bmg160_data *data = iio_priv(indio_dev); 1021 1022 if (data->dready_trigger_on) 1023 iio_trigger_poll(data->dready_trig); 1024 else if (data->motion_trigger_on) 1025 iio_trigger_poll(data->motion_trig); 1026 1027 if (data->ev_enable_state) 1028 return IRQ_WAKE_THREAD; 1029 else 1030 return IRQ_HANDLED; 1031 1032 } 1033 1034 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 1035 { 1036 struct bmg160_data *data = iio_priv(indio_dev); 1037 1038 return bmg160_set_power_state(data, true); 1039 } 1040 1041 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 1042 { 1043 struct bmg160_data *data = iio_priv(indio_dev); 1044 1045 return bmg160_set_power_state(data, false); 1046 } 1047 1048 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 1049 .preenable = bmg160_buffer_preenable, 1050 .postdisable = bmg160_buffer_postdisable, 1051 }; 1052 1053 static const char *bmg160_match_acpi_device(struct device *dev) 1054 { 1055 const struct acpi_device_id *id; 1056 1057 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1058 if (!id) 1059 return NULL; 1060 1061 return dev_name(dev); 1062 } 1063 1064 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 1065 const char *name) 1066 { 1067 struct bmg160_data *data; 1068 struct iio_dev *indio_dev; 1069 int ret; 1070 1071 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1072 if (!indio_dev) 1073 return -ENOMEM; 1074 1075 data = iio_priv(indio_dev); 1076 dev_set_drvdata(dev, indio_dev); 1077 data->irq = irq; 1078 data->regmap = regmap; 1079 1080 ret = iio_read_mount_matrix(dev, "mount-matrix", 1081 &data->orientation); 1082 if (ret) 1083 return ret; 1084 1085 ret = bmg160_chip_init(data); 1086 if (ret < 0) 1087 return ret; 1088 1089 mutex_init(&data->mutex); 1090 1091 if (ACPI_HANDLE(dev)) 1092 name = bmg160_match_acpi_device(dev); 1093 1094 indio_dev->channels = bmg160_channels; 1095 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1096 indio_dev->name = name; 1097 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 1098 indio_dev->modes = INDIO_DIRECT_MODE; 1099 indio_dev->info = &bmg160_info; 1100 1101 if (data->irq > 0) { 1102 ret = devm_request_threaded_irq(dev, 1103 data->irq, 1104 bmg160_data_rdy_trig_poll, 1105 bmg160_event_handler, 1106 IRQF_TRIGGER_RISING, 1107 BMG160_IRQ_NAME, 1108 indio_dev); 1109 if (ret) 1110 return ret; 1111 1112 data->dready_trig = devm_iio_trigger_alloc(dev, 1113 "%s-dev%d", 1114 indio_dev->name, 1115 indio_dev->id); 1116 if (!data->dready_trig) 1117 return -ENOMEM; 1118 1119 data->motion_trig = devm_iio_trigger_alloc(dev, 1120 "%s-any-motion-dev%d", 1121 indio_dev->name, 1122 indio_dev->id); 1123 if (!data->motion_trig) 1124 return -ENOMEM; 1125 1126 data->dready_trig->dev.parent = dev; 1127 data->dready_trig->ops = &bmg160_trigger_ops; 1128 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1129 ret = iio_trigger_register(data->dready_trig); 1130 if (ret) 1131 return ret; 1132 1133 data->motion_trig->dev.parent = dev; 1134 data->motion_trig->ops = &bmg160_trigger_ops; 1135 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1136 ret = iio_trigger_register(data->motion_trig); 1137 if (ret) { 1138 data->motion_trig = NULL; 1139 goto err_trigger_unregister; 1140 } 1141 } 1142 1143 ret = iio_triggered_buffer_setup(indio_dev, 1144 iio_pollfunc_store_time, 1145 bmg160_trigger_handler, 1146 &bmg160_buffer_setup_ops); 1147 if (ret < 0) { 1148 dev_err(dev, 1149 "iio triggered buffer setup failed\n"); 1150 goto err_trigger_unregister; 1151 } 1152 1153 ret = pm_runtime_set_active(dev); 1154 if (ret) 1155 goto err_buffer_cleanup; 1156 1157 pm_runtime_enable(dev); 1158 pm_runtime_set_autosuspend_delay(dev, 1159 BMG160_AUTO_SUSPEND_DELAY_MS); 1160 pm_runtime_use_autosuspend(dev); 1161 1162 ret = iio_device_register(indio_dev); 1163 if (ret < 0) { 1164 dev_err(dev, "unable to register iio device\n"); 1165 goto err_buffer_cleanup; 1166 } 1167 1168 return 0; 1169 1170 err_buffer_cleanup: 1171 iio_triggered_buffer_cleanup(indio_dev); 1172 err_trigger_unregister: 1173 if (data->dready_trig) 1174 iio_trigger_unregister(data->dready_trig); 1175 if (data->motion_trig) 1176 iio_trigger_unregister(data->motion_trig); 1177 1178 return ret; 1179 } 1180 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1181 1182 void bmg160_core_remove(struct device *dev) 1183 { 1184 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1185 struct bmg160_data *data = iio_priv(indio_dev); 1186 1187 iio_device_unregister(indio_dev); 1188 1189 pm_runtime_disable(dev); 1190 pm_runtime_set_suspended(dev); 1191 pm_runtime_put_noidle(dev); 1192 1193 iio_triggered_buffer_cleanup(indio_dev); 1194 1195 if (data->dready_trig) { 1196 iio_trigger_unregister(data->dready_trig); 1197 iio_trigger_unregister(data->motion_trig); 1198 } 1199 1200 mutex_lock(&data->mutex); 1201 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1202 mutex_unlock(&data->mutex); 1203 } 1204 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1205 1206 #ifdef CONFIG_PM_SLEEP 1207 static int bmg160_suspend(struct device *dev) 1208 { 1209 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1210 struct bmg160_data *data = iio_priv(indio_dev); 1211 1212 mutex_lock(&data->mutex); 1213 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1214 mutex_unlock(&data->mutex); 1215 1216 return 0; 1217 } 1218 1219 static int bmg160_resume(struct device *dev) 1220 { 1221 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1222 struct bmg160_data *data = iio_priv(indio_dev); 1223 1224 mutex_lock(&data->mutex); 1225 if (data->dready_trigger_on || data->motion_trigger_on || 1226 data->ev_enable_state) 1227 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1228 mutex_unlock(&data->mutex); 1229 1230 return 0; 1231 } 1232 #endif 1233 1234 #ifdef CONFIG_PM 1235 static int bmg160_runtime_suspend(struct device *dev) 1236 { 1237 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1238 struct bmg160_data *data = iio_priv(indio_dev); 1239 int ret; 1240 1241 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1242 if (ret < 0) { 1243 dev_err(dev, "set mode failed\n"); 1244 return -EAGAIN; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int bmg160_runtime_resume(struct device *dev) 1251 { 1252 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1253 struct bmg160_data *data = iio_priv(indio_dev); 1254 int ret; 1255 1256 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1257 if (ret < 0) 1258 return ret; 1259 1260 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1261 1262 return 0; 1263 } 1264 #endif 1265 1266 const struct dev_pm_ops bmg160_pm_ops = { 1267 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1268 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1269 bmg160_runtime_resume, NULL) 1270 }; 1271 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1272 1273 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1274 MODULE_LICENSE("GPL v2"); 1275 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1276