1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BMG160 Gyro Sensor driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/acpi.h> 12 #include <linux/pm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/iio/triggered_buffer.h> 21 #include <linux/regmap.h> 22 #include "bmg160.h" 23 24 #define BMG160_IRQ_NAME "bmg160_event" 25 26 #define BMG160_REG_CHIP_ID 0x00 27 #define BMG160_CHIP_ID_VAL 0x0F 28 29 #define BMG160_REG_PMU_LPW 0x11 30 #define BMG160_MODE_NORMAL 0x00 31 #define BMG160_MODE_DEEP_SUSPEND 0x20 32 #define BMG160_MODE_SUSPEND 0x80 33 34 #define BMG160_REG_RANGE 0x0F 35 36 #define BMG160_RANGE_2000DPS 0 37 #define BMG160_RANGE_1000DPS 1 38 #define BMG160_RANGE_500DPS 2 39 #define BMG160_RANGE_250DPS 3 40 #define BMG160_RANGE_125DPS 4 41 42 #define BMG160_REG_PMU_BW 0x10 43 #define BMG160_NO_FILTER 0 44 #define BMG160_DEF_BW 100 45 #define BMG160_REG_PMU_BW_RES BIT(7) 46 47 #define BMG160_GYRO_REG_RESET 0x14 48 #define BMG160_GYRO_RESET_VAL 0xb6 49 50 #define BMG160_REG_INT_MAP_0 0x17 51 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 52 53 #define BMG160_REG_INT_MAP_1 0x18 54 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 55 56 #define BMG160_REG_INT_RST_LATCH 0x21 57 #define BMG160_INT_MODE_LATCH_RESET 0x80 58 #define BMG160_INT_MODE_LATCH_INT 0x0F 59 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 60 61 #define BMG160_REG_INT_EN_0 0x15 62 #define BMG160_DATA_ENABLE_INT BIT(7) 63 64 #define BMG160_REG_INT_EN_1 0x16 65 #define BMG160_INT1_BIT_OD BIT(1) 66 67 #define BMG160_REG_XOUT_L 0x02 68 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 69 70 #define BMG160_REG_SLOPE_THRES 0x1B 71 #define BMG160_SLOPE_THRES_MASK 0x0F 72 73 #define BMG160_REG_MOTION_INTR 0x1C 74 #define BMG160_INT_MOTION_X BIT(0) 75 #define BMG160_INT_MOTION_Y BIT(1) 76 #define BMG160_INT_MOTION_Z BIT(2) 77 #define BMG160_ANY_DUR_MASK 0x30 78 #define BMG160_ANY_DUR_SHIFT 4 79 80 #define BMG160_REG_INT_STATUS_2 0x0B 81 #define BMG160_ANY_MOTION_MASK 0x07 82 #define BMG160_ANY_MOTION_BIT_X BIT(0) 83 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 84 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 85 86 #define BMG160_REG_TEMP 0x08 87 #define BMG160_TEMP_CENTER_VAL 23 88 89 #define BMG160_MAX_STARTUP_TIME_MS 80 90 91 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 92 93 struct bmg160_data { 94 struct regmap *regmap; 95 struct iio_trigger *dready_trig; 96 struct iio_trigger *motion_trig; 97 struct iio_mount_matrix orientation; 98 struct mutex mutex; 99 s16 buffer[8]; 100 u32 dps_range; 101 int ev_enable_state; 102 int slope_thres; 103 bool dready_trigger_on; 104 bool motion_trigger_on; 105 int irq; 106 }; 107 108 enum bmg160_axis { 109 AXIS_X, 110 AXIS_Y, 111 AXIS_Z, 112 AXIS_MAX, 113 }; 114 115 static const struct { 116 int odr; 117 int filter; 118 int bw_bits; 119 } bmg160_samp_freq_table[] = { {100, 32, 0x07}, 120 {200, 64, 0x06}, 121 {100, 12, 0x05}, 122 {200, 23, 0x04}, 123 {400, 47, 0x03}, 124 {1000, 116, 0x02}, 125 {2000, 230, 0x01} }; 126 127 static const struct { 128 int scale; 129 int dps_range; 130 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 131 { 532, BMG160_RANGE_1000DPS}, 132 { 266, BMG160_RANGE_500DPS}, 133 { 133, BMG160_RANGE_250DPS}, 134 { 66, BMG160_RANGE_125DPS} }; 135 136 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 137 { 138 struct device *dev = regmap_get_device(data->regmap); 139 int ret; 140 141 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 142 if (ret < 0) { 143 dev_err(dev, "Error writing reg_pmu_lpw\n"); 144 return ret; 145 } 146 147 return 0; 148 } 149 150 static int bmg160_convert_freq_to_bit(int val) 151 { 152 int i; 153 154 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 155 if (bmg160_samp_freq_table[i].odr == val) 156 return bmg160_samp_freq_table[i].bw_bits; 157 } 158 159 return -EINVAL; 160 } 161 162 static int bmg160_set_bw(struct bmg160_data *data, int val) 163 { 164 struct device *dev = regmap_get_device(data->regmap); 165 int ret; 166 int bw_bits; 167 168 bw_bits = bmg160_convert_freq_to_bit(val); 169 if (bw_bits < 0) 170 return bw_bits; 171 172 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 173 if (ret < 0) { 174 dev_err(dev, "Error writing reg_pmu_bw\n"); 175 return ret; 176 } 177 178 return 0; 179 } 180 181 static int bmg160_get_filter(struct bmg160_data *data, int *val) 182 { 183 struct device *dev = regmap_get_device(data->regmap); 184 int ret; 185 int i; 186 unsigned int bw_bits; 187 188 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 189 if (ret < 0) { 190 dev_err(dev, "Error reading reg_pmu_bw\n"); 191 return ret; 192 } 193 194 /* Ignore the readonly reserved bit. */ 195 bw_bits &= ~BMG160_REG_PMU_BW_RES; 196 197 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 198 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) 199 break; 200 } 201 202 *val = bmg160_samp_freq_table[i].filter; 203 204 return ret ? ret : IIO_VAL_INT; 205 } 206 207 208 static int bmg160_set_filter(struct bmg160_data *data, int val) 209 { 210 struct device *dev = regmap_get_device(data->regmap); 211 int ret; 212 int i; 213 214 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 215 if (bmg160_samp_freq_table[i].filter == val) 216 break; 217 } 218 219 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, 220 bmg160_samp_freq_table[i].bw_bits); 221 if (ret < 0) { 222 dev_err(dev, "Error writing reg_pmu_bw\n"); 223 return ret; 224 } 225 226 return 0; 227 } 228 229 static int bmg160_chip_init(struct bmg160_data *data) 230 { 231 struct device *dev = regmap_get_device(data->regmap); 232 int ret; 233 unsigned int val; 234 235 /* 236 * Reset chip to get it in a known good state. A delay of 30ms after 237 * reset is required according to the datasheet. 238 */ 239 regmap_write(data->regmap, BMG160_GYRO_REG_RESET, 240 BMG160_GYRO_RESET_VAL); 241 usleep_range(30000, 30700); 242 243 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 244 if (ret < 0) { 245 dev_err(dev, "Error reading reg_chip_id\n"); 246 return ret; 247 } 248 249 dev_dbg(dev, "Chip Id %x\n", val); 250 if (val != BMG160_CHIP_ID_VAL) { 251 dev_err(dev, "invalid chip %x\n", val); 252 return -ENODEV; 253 } 254 255 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 256 if (ret < 0) 257 return ret; 258 259 /* Wait upto 500 ms to be ready after changing mode */ 260 usleep_range(500, 1000); 261 262 /* Set Bandwidth */ 263 ret = bmg160_set_bw(data, BMG160_DEF_BW); 264 if (ret < 0) 265 return ret; 266 267 /* Set Default Range */ 268 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 269 if (ret < 0) { 270 dev_err(dev, "Error writing reg_range\n"); 271 return ret; 272 } 273 data->dps_range = BMG160_RANGE_500DPS; 274 275 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 276 if (ret < 0) { 277 dev_err(dev, "Error reading reg_slope_thres\n"); 278 return ret; 279 } 280 data->slope_thres = val; 281 282 /* Set default interrupt mode */ 283 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 284 BMG160_INT1_BIT_OD, 0); 285 if (ret < 0) { 286 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 287 return ret; 288 } 289 290 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 291 BMG160_INT_MODE_LATCH_INT | 292 BMG160_INT_MODE_LATCH_RESET); 293 if (ret < 0) { 294 dev_err(dev, 295 "Error writing reg_motion_intr\n"); 296 return ret; 297 } 298 299 return 0; 300 } 301 302 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 303 { 304 #ifdef CONFIG_PM 305 struct device *dev = regmap_get_device(data->regmap); 306 int ret; 307 308 if (on) 309 ret = pm_runtime_get_sync(dev); 310 else { 311 pm_runtime_mark_last_busy(dev); 312 ret = pm_runtime_put_autosuspend(dev); 313 } 314 315 if (ret < 0) { 316 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 317 318 if (on) 319 pm_runtime_put_noidle(dev); 320 321 return ret; 322 } 323 #endif 324 325 return 0; 326 } 327 328 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 329 bool status) 330 { 331 struct device *dev = regmap_get_device(data->regmap); 332 int ret; 333 334 /* Enable/Disable INT_MAP0 mapping */ 335 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 336 BMG160_INT_MAP_0_BIT_ANY, 337 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 338 if (ret < 0) { 339 dev_err(dev, "Error updating bits reg_int_map0\n"); 340 return ret; 341 } 342 343 /* Enable/Disable slope interrupts */ 344 if (status) { 345 /* Update slope thres */ 346 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 347 data->slope_thres); 348 if (ret < 0) { 349 dev_err(dev, "Error writing reg_slope_thres\n"); 350 return ret; 351 } 352 353 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 354 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 355 BMG160_INT_MOTION_Z); 356 if (ret < 0) { 357 dev_err(dev, "Error writing reg_motion_intr\n"); 358 return ret; 359 } 360 361 /* 362 * New data interrupt is always non-latched, 363 * which will have higher priority, so no need 364 * to set latched mode, we will be flooded anyway with INTR 365 */ 366 if (!data->dready_trigger_on) { 367 ret = regmap_write(data->regmap, 368 BMG160_REG_INT_RST_LATCH, 369 BMG160_INT_MODE_LATCH_INT | 370 BMG160_INT_MODE_LATCH_RESET); 371 if (ret < 0) { 372 dev_err(dev, "Error writing reg_rst_latch\n"); 373 return ret; 374 } 375 } 376 377 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 378 BMG160_DATA_ENABLE_INT); 379 380 } else { 381 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 382 } 383 384 if (ret < 0) { 385 dev_err(dev, "Error writing reg_int_en0\n"); 386 return ret; 387 } 388 389 return 0; 390 } 391 392 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 393 bool status) 394 { 395 struct device *dev = regmap_get_device(data->regmap); 396 int ret; 397 398 /* Enable/Disable INT_MAP1 mapping */ 399 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 400 BMG160_INT_MAP_1_BIT_NEW_DATA, 401 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 402 if (ret < 0) { 403 dev_err(dev, "Error updating bits in reg_int_map1\n"); 404 return ret; 405 } 406 407 if (status) { 408 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 409 BMG160_INT_MODE_NON_LATCH_INT | 410 BMG160_INT_MODE_LATCH_RESET); 411 if (ret < 0) { 412 dev_err(dev, "Error writing reg_rst_latch\n"); 413 return ret; 414 } 415 416 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 417 BMG160_DATA_ENABLE_INT); 418 419 } else { 420 /* Restore interrupt mode */ 421 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 422 BMG160_INT_MODE_LATCH_INT | 423 BMG160_INT_MODE_LATCH_RESET); 424 if (ret < 0) { 425 dev_err(dev, "Error writing reg_rst_latch\n"); 426 return ret; 427 } 428 429 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 430 } 431 432 if (ret < 0) { 433 dev_err(dev, "Error writing reg_int_en0\n"); 434 return ret; 435 } 436 437 return 0; 438 } 439 440 static int bmg160_get_bw(struct bmg160_data *data, int *val) 441 { 442 struct device *dev = regmap_get_device(data->regmap); 443 int i; 444 unsigned int bw_bits; 445 int ret; 446 447 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 448 if (ret < 0) { 449 dev_err(dev, "Error reading reg_pmu_bw\n"); 450 return ret; 451 } 452 453 /* Ignore the readonly reserved bit. */ 454 bw_bits &= ~BMG160_REG_PMU_BW_RES; 455 456 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 457 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { 458 *val = bmg160_samp_freq_table[i].odr; 459 return IIO_VAL_INT; 460 } 461 } 462 463 return -EINVAL; 464 } 465 466 static int bmg160_set_scale(struct bmg160_data *data, int val) 467 { 468 struct device *dev = regmap_get_device(data->regmap); 469 int ret, i; 470 471 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 472 if (bmg160_scale_table[i].scale == val) { 473 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 474 bmg160_scale_table[i].dps_range); 475 if (ret < 0) { 476 dev_err(dev, "Error writing reg_range\n"); 477 return ret; 478 } 479 data->dps_range = bmg160_scale_table[i].dps_range; 480 return 0; 481 } 482 } 483 484 return -EINVAL; 485 } 486 487 static int bmg160_get_temp(struct bmg160_data *data, int *val) 488 { 489 struct device *dev = regmap_get_device(data->regmap); 490 int ret; 491 unsigned int raw_val; 492 493 mutex_lock(&data->mutex); 494 ret = bmg160_set_power_state(data, true); 495 if (ret < 0) { 496 mutex_unlock(&data->mutex); 497 return ret; 498 } 499 500 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 501 if (ret < 0) { 502 dev_err(dev, "Error reading reg_temp\n"); 503 bmg160_set_power_state(data, false); 504 mutex_unlock(&data->mutex); 505 return ret; 506 } 507 508 *val = sign_extend32(raw_val, 7); 509 ret = bmg160_set_power_state(data, false); 510 mutex_unlock(&data->mutex); 511 if (ret < 0) 512 return ret; 513 514 return IIO_VAL_INT; 515 } 516 517 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 518 { 519 struct device *dev = regmap_get_device(data->regmap); 520 int ret; 521 __le16 raw_val; 522 523 mutex_lock(&data->mutex); 524 ret = bmg160_set_power_state(data, true); 525 if (ret < 0) { 526 mutex_unlock(&data->mutex); 527 return ret; 528 } 529 530 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 531 sizeof(raw_val)); 532 if (ret < 0) { 533 dev_err(dev, "Error reading axis %d\n", axis); 534 bmg160_set_power_state(data, false); 535 mutex_unlock(&data->mutex); 536 return ret; 537 } 538 539 *val = sign_extend32(le16_to_cpu(raw_val), 15); 540 ret = bmg160_set_power_state(data, false); 541 mutex_unlock(&data->mutex); 542 if (ret < 0) 543 return ret; 544 545 return IIO_VAL_INT; 546 } 547 548 static int bmg160_read_raw(struct iio_dev *indio_dev, 549 struct iio_chan_spec const *chan, 550 int *val, int *val2, long mask) 551 { 552 struct bmg160_data *data = iio_priv(indio_dev); 553 int ret; 554 555 switch (mask) { 556 case IIO_CHAN_INFO_RAW: 557 switch (chan->type) { 558 case IIO_TEMP: 559 return bmg160_get_temp(data, val); 560 case IIO_ANGL_VEL: 561 if (iio_buffer_enabled(indio_dev)) 562 return -EBUSY; 563 else 564 return bmg160_get_axis(data, chan->scan_index, 565 val); 566 default: 567 return -EINVAL; 568 } 569 case IIO_CHAN_INFO_OFFSET: 570 if (chan->type == IIO_TEMP) { 571 *val = BMG160_TEMP_CENTER_VAL; 572 return IIO_VAL_INT; 573 } else 574 return -EINVAL; 575 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 576 return bmg160_get_filter(data, val); 577 case IIO_CHAN_INFO_SCALE: 578 switch (chan->type) { 579 case IIO_TEMP: 580 *val = 500; 581 return IIO_VAL_INT; 582 case IIO_ANGL_VEL: 583 { 584 int i; 585 586 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 587 if (bmg160_scale_table[i].dps_range == 588 data->dps_range) { 589 *val = 0; 590 *val2 = bmg160_scale_table[i].scale; 591 return IIO_VAL_INT_PLUS_MICRO; 592 } 593 } 594 return -EINVAL; 595 } 596 default: 597 return -EINVAL; 598 } 599 case IIO_CHAN_INFO_SAMP_FREQ: 600 *val2 = 0; 601 mutex_lock(&data->mutex); 602 ret = bmg160_get_bw(data, val); 603 mutex_unlock(&data->mutex); 604 return ret; 605 default: 606 return -EINVAL; 607 } 608 } 609 610 static int bmg160_write_raw(struct iio_dev *indio_dev, 611 struct iio_chan_spec const *chan, 612 int val, int val2, long mask) 613 { 614 struct bmg160_data *data = iio_priv(indio_dev); 615 int ret; 616 617 switch (mask) { 618 case IIO_CHAN_INFO_SAMP_FREQ: 619 mutex_lock(&data->mutex); 620 /* 621 * Section 4.2 of spec 622 * In suspend mode, the only supported operations are reading 623 * registers as well as writing to the (0x14) softreset 624 * register. Since we will be in suspend mode by default, change 625 * mode to power on for other writes. 626 */ 627 ret = bmg160_set_power_state(data, true); 628 if (ret < 0) { 629 mutex_unlock(&data->mutex); 630 return ret; 631 } 632 ret = bmg160_set_bw(data, val); 633 if (ret < 0) { 634 bmg160_set_power_state(data, false); 635 mutex_unlock(&data->mutex); 636 return ret; 637 } 638 ret = bmg160_set_power_state(data, false); 639 mutex_unlock(&data->mutex); 640 return ret; 641 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 642 if (val2) 643 return -EINVAL; 644 645 mutex_lock(&data->mutex); 646 ret = bmg160_set_power_state(data, true); 647 if (ret < 0) { 648 bmg160_set_power_state(data, false); 649 mutex_unlock(&data->mutex); 650 return ret; 651 } 652 ret = bmg160_set_filter(data, val); 653 if (ret < 0) { 654 bmg160_set_power_state(data, false); 655 mutex_unlock(&data->mutex); 656 return ret; 657 } 658 ret = bmg160_set_power_state(data, false); 659 mutex_unlock(&data->mutex); 660 return ret; 661 case IIO_CHAN_INFO_SCALE: 662 if (val) 663 return -EINVAL; 664 665 mutex_lock(&data->mutex); 666 /* Refer to comments above for the suspend mode ops */ 667 ret = bmg160_set_power_state(data, true); 668 if (ret < 0) { 669 mutex_unlock(&data->mutex); 670 return ret; 671 } 672 ret = bmg160_set_scale(data, val2); 673 if (ret < 0) { 674 bmg160_set_power_state(data, false); 675 mutex_unlock(&data->mutex); 676 return ret; 677 } 678 ret = bmg160_set_power_state(data, false); 679 mutex_unlock(&data->mutex); 680 return ret; 681 default: 682 return -EINVAL; 683 } 684 685 return -EINVAL; 686 } 687 688 static int bmg160_read_event(struct iio_dev *indio_dev, 689 const struct iio_chan_spec *chan, 690 enum iio_event_type type, 691 enum iio_event_direction dir, 692 enum iio_event_info info, 693 int *val, int *val2) 694 { 695 struct bmg160_data *data = iio_priv(indio_dev); 696 697 *val2 = 0; 698 switch (info) { 699 case IIO_EV_INFO_VALUE: 700 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 701 break; 702 default: 703 return -EINVAL; 704 } 705 706 return IIO_VAL_INT; 707 } 708 709 static int bmg160_write_event(struct iio_dev *indio_dev, 710 const struct iio_chan_spec *chan, 711 enum iio_event_type type, 712 enum iio_event_direction dir, 713 enum iio_event_info info, 714 int val, int val2) 715 { 716 struct bmg160_data *data = iio_priv(indio_dev); 717 718 switch (info) { 719 case IIO_EV_INFO_VALUE: 720 if (data->ev_enable_state) 721 return -EBUSY; 722 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 723 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 724 break; 725 default: 726 return -EINVAL; 727 } 728 729 return 0; 730 } 731 732 static int bmg160_read_event_config(struct iio_dev *indio_dev, 733 const struct iio_chan_spec *chan, 734 enum iio_event_type type, 735 enum iio_event_direction dir) 736 { 737 738 struct bmg160_data *data = iio_priv(indio_dev); 739 740 return data->ev_enable_state; 741 } 742 743 static int bmg160_write_event_config(struct iio_dev *indio_dev, 744 const struct iio_chan_spec *chan, 745 enum iio_event_type type, 746 enum iio_event_direction dir, 747 int state) 748 { 749 struct bmg160_data *data = iio_priv(indio_dev); 750 int ret; 751 752 if (state && data->ev_enable_state) 753 return 0; 754 755 mutex_lock(&data->mutex); 756 757 if (!state && data->motion_trigger_on) { 758 data->ev_enable_state = 0; 759 mutex_unlock(&data->mutex); 760 return 0; 761 } 762 /* 763 * We will expect the enable and disable to do operation in 764 * in reverse order. This will happen here anyway as our 765 * resume operation uses sync mode runtime pm calls, the 766 * suspend operation will be delayed by autosuspend delay 767 * So the disable operation will still happen in reverse of 768 * enable operation. When runtime pm is disabled the mode 769 * is always on so sequence doesn't matter 770 */ 771 ret = bmg160_set_power_state(data, state); 772 if (ret < 0) { 773 mutex_unlock(&data->mutex); 774 return ret; 775 } 776 777 ret = bmg160_setup_any_motion_interrupt(data, state); 778 if (ret < 0) { 779 bmg160_set_power_state(data, false); 780 mutex_unlock(&data->mutex); 781 return ret; 782 } 783 784 data->ev_enable_state = state; 785 mutex_unlock(&data->mutex); 786 787 return 0; 788 } 789 790 static const struct iio_mount_matrix * 791 bmg160_get_mount_matrix(const struct iio_dev *indio_dev, 792 const struct iio_chan_spec *chan) 793 { 794 struct bmg160_data *data = iio_priv(indio_dev); 795 796 return &data->orientation; 797 } 798 799 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = { 800 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix), 801 { } 802 }; 803 804 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 805 806 static IIO_CONST_ATTR(in_anglvel_scale_available, 807 "0.001065 0.000532 0.000266 0.000133 0.000066"); 808 809 static struct attribute *bmg160_attributes[] = { 810 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 811 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 812 NULL, 813 }; 814 815 static const struct attribute_group bmg160_attrs_group = { 816 .attrs = bmg160_attributes, 817 }; 818 819 static const struct iio_event_spec bmg160_event = { 820 .type = IIO_EV_TYPE_ROC, 821 .dir = IIO_EV_DIR_EITHER, 822 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 823 BIT(IIO_EV_INFO_ENABLE) 824 }; 825 826 #define BMG160_CHANNEL(_axis) { \ 827 .type = IIO_ANGL_VEL, \ 828 .modified = 1, \ 829 .channel2 = IIO_MOD_##_axis, \ 830 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 831 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 832 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 833 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 834 .scan_index = AXIS_##_axis, \ 835 .scan_type = { \ 836 .sign = 's', \ 837 .realbits = 16, \ 838 .storagebits = 16, \ 839 .endianness = IIO_LE, \ 840 }, \ 841 .ext_info = bmg160_ext_info, \ 842 .event_spec = &bmg160_event, \ 843 .num_event_specs = 1 \ 844 } 845 846 static const struct iio_chan_spec bmg160_channels[] = { 847 { 848 .type = IIO_TEMP, 849 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 850 BIT(IIO_CHAN_INFO_SCALE) | 851 BIT(IIO_CHAN_INFO_OFFSET), 852 .scan_index = -1, 853 }, 854 BMG160_CHANNEL(X), 855 BMG160_CHANNEL(Y), 856 BMG160_CHANNEL(Z), 857 IIO_CHAN_SOFT_TIMESTAMP(3), 858 }; 859 860 static const struct iio_info bmg160_info = { 861 .attrs = &bmg160_attrs_group, 862 .read_raw = bmg160_read_raw, 863 .write_raw = bmg160_write_raw, 864 .read_event_value = bmg160_read_event, 865 .write_event_value = bmg160_write_event, 866 .write_event_config = bmg160_write_event_config, 867 .read_event_config = bmg160_read_event_config, 868 }; 869 870 static const unsigned long bmg160_accel_scan_masks[] = { 871 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 872 0}; 873 874 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 875 { 876 struct iio_poll_func *pf = p; 877 struct iio_dev *indio_dev = pf->indio_dev; 878 struct bmg160_data *data = iio_priv(indio_dev); 879 int ret; 880 881 mutex_lock(&data->mutex); 882 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 883 data->buffer, AXIS_MAX * 2); 884 mutex_unlock(&data->mutex); 885 if (ret < 0) 886 goto err; 887 888 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 889 pf->timestamp); 890 err: 891 iio_trigger_notify_done(indio_dev->trig); 892 893 return IRQ_HANDLED; 894 } 895 896 static int bmg160_trig_try_reen(struct iio_trigger *trig) 897 { 898 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 899 struct bmg160_data *data = iio_priv(indio_dev); 900 struct device *dev = regmap_get_device(data->regmap); 901 int ret; 902 903 /* new data interrupts don't need ack */ 904 if (data->dready_trigger_on) 905 return 0; 906 907 /* Set latched mode interrupt and clear any latched interrupt */ 908 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 909 BMG160_INT_MODE_LATCH_INT | 910 BMG160_INT_MODE_LATCH_RESET); 911 if (ret < 0) { 912 dev_err(dev, "Error writing reg_rst_latch\n"); 913 return ret; 914 } 915 916 return 0; 917 } 918 919 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 920 bool state) 921 { 922 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 923 struct bmg160_data *data = iio_priv(indio_dev); 924 int ret; 925 926 mutex_lock(&data->mutex); 927 928 if (!state && data->ev_enable_state && data->motion_trigger_on) { 929 data->motion_trigger_on = false; 930 mutex_unlock(&data->mutex); 931 return 0; 932 } 933 934 /* 935 * Refer to comment in bmg160_write_event_config for 936 * enable/disable operation order 937 */ 938 ret = bmg160_set_power_state(data, state); 939 if (ret < 0) { 940 mutex_unlock(&data->mutex); 941 return ret; 942 } 943 if (data->motion_trig == trig) 944 ret = bmg160_setup_any_motion_interrupt(data, state); 945 else 946 ret = bmg160_setup_new_data_interrupt(data, state); 947 if (ret < 0) { 948 bmg160_set_power_state(data, false); 949 mutex_unlock(&data->mutex); 950 return ret; 951 } 952 if (data->motion_trig == trig) 953 data->motion_trigger_on = state; 954 else 955 data->dready_trigger_on = state; 956 957 mutex_unlock(&data->mutex); 958 959 return 0; 960 } 961 962 static const struct iio_trigger_ops bmg160_trigger_ops = { 963 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 964 .try_reenable = bmg160_trig_try_reen, 965 }; 966 967 static irqreturn_t bmg160_event_handler(int irq, void *private) 968 { 969 struct iio_dev *indio_dev = private; 970 struct bmg160_data *data = iio_priv(indio_dev); 971 struct device *dev = regmap_get_device(data->regmap); 972 int ret; 973 int dir; 974 unsigned int val; 975 976 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 977 if (ret < 0) { 978 dev_err(dev, "Error reading reg_int_status2\n"); 979 goto ack_intr_status; 980 } 981 982 if (val & 0x08) 983 dir = IIO_EV_DIR_RISING; 984 else 985 dir = IIO_EV_DIR_FALLING; 986 987 if (val & BMG160_ANY_MOTION_BIT_X) 988 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 989 0, 990 IIO_MOD_X, 991 IIO_EV_TYPE_ROC, 992 dir), 993 iio_get_time_ns(indio_dev)); 994 if (val & BMG160_ANY_MOTION_BIT_Y) 995 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 996 0, 997 IIO_MOD_Y, 998 IIO_EV_TYPE_ROC, 999 dir), 1000 iio_get_time_ns(indio_dev)); 1001 if (val & BMG160_ANY_MOTION_BIT_Z) 1002 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 1003 0, 1004 IIO_MOD_Z, 1005 IIO_EV_TYPE_ROC, 1006 dir), 1007 iio_get_time_ns(indio_dev)); 1008 1009 ack_intr_status: 1010 if (!data->dready_trigger_on) { 1011 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 1012 BMG160_INT_MODE_LATCH_INT | 1013 BMG160_INT_MODE_LATCH_RESET); 1014 if (ret < 0) 1015 dev_err(dev, "Error writing reg_rst_latch\n"); 1016 } 1017 1018 return IRQ_HANDLED; 1019 } 1020 1021 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 1022 { 1023 struct iio_dev *indio_dev = private; 1024 struct bmg160_data *data = iio_priv(indio_dev); 1025 1026 if (data->dready_trigger_on) 1027 iio_trigger_poll(data->dready_trig); 1028 else if (data->motion_trigger_on) 1029 iio_trigger_poll(data->motion_trig); 1030 1031 if (data->ev_enable_state) 1032 return IRQ_WAKE_THREAD; 1033 else 1034 return IRQ_HANDLED; 1035 1036 } 1037 1038 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 1039 { 1040 struct bmg160_data *data = iio_priv(indio_dev); 1041 1042 return bmg160_set_power_state(data, true); 1043 } 1044 1045 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 1046 { 1047 struct bmg160_data *data = iio_priv(indio_dev); 1048 1049 return bmg160_set_power_state(data, false); 1050 } 1051 1052 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 1053 .preenable = bmg160_buffer_preenable, 1054 .postdisable = bmg160_buffer_postdisable, 1055 }; 1056 1057 static const char *bmg160_match_acpi_device(struct device *dev) 1058 { 1059 const struct acpi_device_id *id; 1060 1061 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1062 if (!id) 1063 return NULL; 1064 1065 return dev_name(dev); 1066 } 1067 1068 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 1069 const char *name) 1070 { 1071 struct bmg160_data *data; 1072 struct iio_dev *indio_dev; 1073 int ret; 1074 1075 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1076 if (!indio_dev) 1077 return -ENOMEM; 1078 1079 data = iio_priv(indio_dev); 1080 dev_set_drvdata(dev, indio_dev); 1081 data->irq = irq; 1082 data->regmap = regmap; 1083 1084 ret = iio_read_mount_matrix(dev, "mount-matrix", 1085 &data->orientation); 1086 if (ret) 1087 return ret; 1088 1089 ret = bmg160_chip_init(data); 1090 if (ret < 0) 1091 return ret; 1092 1093 mutex_init(&data->mutex); 1094 1095 if (ACPI_HANDLE(dev)) 1096 name = bmg160_match_acpi_device(dev); 1097 1098 indio_dev->channels = bmg160_channels; 1099 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1100 indio_dev->name = name; 1101 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 1102 indio_dev->modes = INDIO_DIRECT_MODE; 1103 indio_dev->info = &bmg160_info; 1104 1105 if (data->irq > 0) { 1106 ret = devm_request_threaded_irq(dev, 1107 data->irq, 1108 bmg160_data_rdy_trig_poll, 1109 bmg160_event_handler, 1110 IRQF_TRIGGER_RISING, 1111 BMG160_IRQ_NAME, 1112 indio_dev); 1113 if (ret) 1114 return ret; 1115 1116 data->dready_trig = devm_iio_trigger_alloc(dev, 1117 "%s-dev%d", 1118 indio_dev->name, 1119 indio_dev->id); 1120 if (!data->dready_trig) 1121 return -ENOMEM; 1122 1123 data->motion_trig = devm_iio_trigger_alloc(dev, 1124 "%s-any-motion-dev%d", 1125 indio_dev->name, 1126 indio_dev->id); 1127 if (!data->motion_trig) 1128 return -ENOMEM; 1129 1130 data->dready_trig->dev.parent = dev; 1131 data->dready_trig->ops = &bmg160_trigger_ops; 1132 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1133 ret = iio_trigger_register(data->dready_trig); 1134 if (ret) 1135 return ret; 1136 1137 data->motion_trig->dev.parent = dev; 1138 data->motion_trig->ops = &bmg160_trigger_ops; 1139 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1140 ret = iio_trigger_register(data->motion_trig); 1141 if (ret) { 1142 data->motion_trig = NULL; 1143 goto err_trigger_unregister; 1144 } 1145 } 1146 1147 ret = iio_triggered_buffer_setup(indio_dev, 1148 iio_pollfunc_store_time, 1149 bmg160_trigger_handler, 1150 &bmg160_buffer_setup_ops); 1151 if (ret < 0) { 1152 dev_err(dev, 1153 "iio triggered buffer setup failed\n"); 1154 goto err_trigger_unregister; 1155 } 1156 1157 ret = pm_runtime_set_active(dev); 1158 if (ret) 1159 goto err_buffer_cleanup; 1160 1161 pm_runtime_enable(dev); 1162 pm_runtime_set_autosuspend_delay(dev, 1163 BMG160_AUTO_SUSPEND_DELAY_MS); 1164 pm_runtime_use_autosuspend(dev); 1165 1166 ret = iio_device_register(indio_dev); 1167 if (ret < 0) { 1168 dev_err(dev, "unable to register iio device\n"); 1169 goto err_buffer_cleanup; 1170 } 1171 1172 return 0; 1173 1174 err_buffer_cleanup: 1175 iio_triggered_buffer_cleanup(indio_dev); 1176 err_trigger_unregister: 1177 if (data->dready_trig) 1178 iio_trigger_unregister(data->dready_trig); 1179 if (data->motion_trig) 1180 iio_trigger_unregister(data->motion_trig); 1181 1182 return ret; 1183 } 1184 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1185 1186 void bmg160_core_remove(struct device *dev) 1187 { 1188 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1189 struct bmg160_data *data = iio_priv(indio_dev); 1190 1191 iio_device_unregister(indio_dev); 1192 1193 pm_runtime_disable(dev); 1194 pm_runtime_set_suspended(dev); 1195 pm_runtime_put_noidle(dev); 1196 1197 iio_triggered_buffer_cleanup(indio_dev); 1198 1199 if (data->dready_trig) { 1200 iio_trigger_unregister(data->dready_trig); 1201 iio_trigger_unregister(data->motion_trig); 1202 } 1203 1204 mutex_lock(&data->mutex); 1205 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1206 mutex_unlock(&data->mutex); 1207 } 1208 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1209 1210 #ifdef CONFIG_PM_SLEEP 1211 static int bmg160_suspend(struct device *dev) 1212 { 1213 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1214 struct bmg160_data *data = iio_priv(indio_dev); 1215 1216 mutex_lock(&data->mutex); 1217 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1218 mutex_unlock(&data->mutex); 1219 1220 return 0; 1221 } 1222 1223 static int bmg160_resume(struct device *dev) 1224 { 1225 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1226 struct bmg160_data *data = iio_priv(indio_dev); 1227 1228 mutex_lock(&data->mutex); 1229 if (data->dready_trigger_on || data->motion_trigger_on || 1230 data->ev_enable_state) 1231 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1232 mutex_unlock(&data->mutex); 1233 1234 return 0; 1235 } 1236 #endif 1237 1238 #ifdef CONFIG_PM 1239 static int bmg160_runtime_suspend(struct device *dev) 1240 { 1241 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1242 struct bmg160_data *data = iio_priv(indio_dev); 1243 int ret; 1244 1245 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1246 if (ret < 0) { 1247 dev_err(dev, "set mode failed\n"); 1248 return -EAGAIN; 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int bmg160_runtime_resume(struct device *dev) 1255 { 1256 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1257 struct bmg160_data *data = iio_priv(indio_dev); 1258 int ret; 1259 1260 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1261 if (ret < 0) 1262 return ret; 1263 1264 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1265 1266 return 0; 1267 } 1268 #endif 1269 1270 const struct dev_pm_ops bmg160_pm_ops = { 1271 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1272 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1273 bmg160_runtime_resume, NULL) 1274 }; 1275 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1276 1277 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1278 MODULE_LICENSE("GPL v2"); 1279 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1280