1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver 4 * 5 * Copyright 2012-2013 Analog Devices Inc. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/kernel.h> 10 #include <linux/slab.h> 11 #include <linux/sysfs.h> 12 #include <linux/spi/spi.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/err.h> 15 #include <linux/module.h> 16 #include <linux/gcd.h> 17 #include <linux/gpio.h> 18 #include <asm/div64.h> 19 #include <linux/clk.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/frequency/adf4350.h> 26 27 enum { 28 ADF4350_FREQ, 29 ADF4350_FREQ_REFIN, 30 ADF4350_FREQ_RESOLUTION, 31 ADF4350_PWRDOWN, 32 }; 33 34 struct adf4350_state { 35 struct spi_device *spi; 36 struct regulator *reg; 37 struct adf4350_platform_data *pdata; 38 struct clk *clk; 39 unsigned long clkin; 40 unsigned long chspc; /* Channel Spacing */ 41 unsigned long fpfd; /* Phase Frequency Detector */ 42 unsigned long min_out_freq; 43 unsigned r0_fract; 44 unsigned r0_int; 45 unsigned r1_mod; 46 unsigned r4_rf_div_sel; 47 unsigned long regs[6]; 48 unsigned long regs_hw[6]; 49 unsigned long long freq_req; 50 /* 51 * DMA (thus cache coherency maintenance) requires the 52 * transfer buffers to live in their own cache lines. 53 */ 54 __be32 val ____cacheline_aligned; 55 }; 56 57 static struct adf4350_platform_data default_pdata = { 58 .channel_spacing = 10000, 59 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS | 60 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500), 61 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0), 62 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) | 63 ADF4350_REG4_MUTE_TILL_LOCK_EN, 64 .gpio_lock_detect = -1, 65 }; 66 67 static int adf4350_sync_config(struct adf4350_state *st) 68 { 69 int ret, i, doublebuf = 0; 70 71 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { 72 if ((st->regs_hw[i] != st->regs[i]) || 73 ((i == ADF4350_REG0) && doublebuf)) { 74 switch (i) { 75 case ADF4350_REG1: 76 case ADF4350_REG4: 77 doublebuf = 1; 78 break; 79 } 80 81 st->val = cpu_to_be32(st->regs[i] | i); 82 ret = spi_write(st->spi, &st->val, 4); 83 if (ret < 0) 84 return ret; 85 st->regs_hw[i] = st->regs[i]; 86 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", 87 i, (u32)st->regs[i] | i); 88 } 89 } 90 return 0; 91 } 92 93 static int adf4350_reg_access(struct iio_dev *indio_dev, 94 unsigned reg, unsigned writeval, 95 unsigned *readval) 96 { 97 struct adf4350_state *st = iio_priv(indio_dev); 98 int ret; 99 100 if (reg > ADF4350_REG5) 101 return -EINVAL; 102 103 mutex_lock(&indio_dev->mlock); 104 if (readval == NULL) { 105 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); 106 ret = adf4350_sync_config(st); 107 } else { 108 *readval = st->regs_hw[reg]; 109 ret = 0; 110 } 111 mutex_unlock(&indio_dev->mlock); 112 113 return ret; 114 } 115 116 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) 117 { 118 struct adf4350_platform_data *pdata = st->pdata; 119 120 do { 121 r_cnt++; 122 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / 123 (r_cnt * (pdata->ref_div2_en ? 2 : 1)); 124 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); 125 126 return r_cnt; 127 } 128 129 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) 130 { 131 struct adf4350_platform_data *pdata = st->pdata; 132 u64 tmp; 133 u32 div_gcd, prescaler, chspc; 134 u16 mdiv, r_cnt = 0; 135 u8 band_sel_div; 136 137 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) 138 return -EINVAL; 139 140 if (freq > ADF4350_MAX_FREQ_45_PRESC) { 141 prescaler = ADF4350_REG1_PRESCALER; 142 mdiv = 75; 143 } else { 144 prescaler = 0; 145 mdiv = 23; 146 } 147 148 st->r4_rf_div_sel = 0; 149 150 while (freq < ADF4350_MIN_VCO_FREQ) { 151 freq <<= 1; 152 st->r4_rf_div_sel++; 153 } 154 155 /* 156 * Allow a predefined reference division factor 157 * if not set, compute our own 158 */ 159 if (pdata->ref_div_factor) 160 r_cnt = pdata->ref_div_factor - 1; 161 162 chspc = st->chspc; 163 164 do { 165 do { 166 do { 167 r_cnt = adf4350_tune_r_cnt(st, r_cnt); 168 st->r1_mod = st->fpfd / chspc; 169 if (r_cnt > ADF4350_MAX_R_CNT) { 170 /* try higher spacing values */ 171 chspc++; 172 r_cnt = 0; 173 } 174 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); 175 } while (r_cnt == 0); 176 177 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); 178 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ 179 st->r0_fract = do_div(tmp, st->r1_mod); 180 st->r0_int = tmp; 181 } while (mdiv > st->r0_int); 182 183 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); 184 185 if (st->r0_fract && st->r1_mod) { 186 div_gcd = gcd(st->r1_mod, st->r0_fract); 187 st->r1_mod /= div_gcd; 188 st->r0_fract /= div_gcd; 189 } else { 190 st->r0_fract = 0; 191 st->r1_mod = 1; 192 } 193 194 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" 195 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n" 196 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n", 197 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, 198 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", 199 band_sel_div); 200 201 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | 202 ADF4350_REG0_FRACT(st->r0_fract); 203 204 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | 205 ADF4350_REG1_MOD(st->r1_mod) | 206 prescaler; 207 208 st->regs[ADF4350_REG2] = 209 ADF4350_REG2_10BIT_R_CNT(r_cnt) | 210 ADF4350_REG2_DOUBLE_BUFF_EN | 211 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) | 212 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) | 213 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS | 214 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N | 215 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) | 216 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3))); 217 218 st->regs[ADF4350_REG3] = pdata->r3_user_settings & 219 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) | 220 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) | 221 ADF4350_REG3_12BIT_CSR_EN | 222 ADF4351_REG3_CHARGE_CANCELLATION_EN | 223 ADF4351_REG3_ANTI_BACKLASH_3ns_EN | 224 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH); 225 226 st->regs[ADF4350_REG4] = 227 ADF4350_REG4_FEEDBACK_FUND | 228 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | 229 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) | 230 ADF4350_REG4_RF_OUT_EN | 231 (pdata->r4_user_settings & 232 (ADF4350_REG4_OUTPUT_PWR(0x3) | 233 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) | 234 ADF4350_REG4_AUX_OUTPUT_EN | 235 ADF4350_REG4_AUX_OUTPUT_FUND | 236 ADF4350_REG4_MUTE_TILL_LOCK_EN)); 237 238 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; 239 st->freq_req = freq; 240 241 return adf4350_sync_config(st); 242 } 243 244 static ssize_t adf4350_write(struct iio_dev *indio_dev, 245 uintptr_t private, 246 const struct iio_chan_spec *chan, 247 const char *buf, size_t len) 248 { 249 struct adf4350_state *st = iio_priv(indio_dev); 250 unsigned long long readin; 251 unsigned long tmp; 252 int ret; 253 254 ret = kstrtoull(buf, 10, &readin); 255 if (ret) 256 return ret; 257 258 mutex_lock(&indio_dev->mlock); 259 switch ((u32)private) { 260 case ADF4350_FREQ: 261 ret = adf4350_set_freq(st, readin); 262 break; 263 case ADF4350_FREQ_REFIN: 264 if (readin > ADF4350_MAX_FREQ_REFIN) { 265 ret = -EINVAL; 266 break; 267 } 268 269 if (st->clk) { 270 tmp = clk_round_rate(st->clk, readin); 271 if (tmp != readin) { 272 ret = -EINVAL; 273 break; 274 } 275 ret = clk_set_rate(st->clk, tmp); 276 if (ret < 0) 277 break; 278 } 279 st->clkin = readin; 280 ret = adf4350_set_freq(st, st->freq_req); 281 break; 282 case ADF4350_FREQ_RESOLUTION: 283 if (readin == 0) 284 ret = -EINVAL; 285 else 286 st->chspc = readin; 287 break; 288 case ADF4350_PWRDOWN: 289 if (readin) 290 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 291 else 292 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; 293 294 adf4350_sync_config(st); 295 break; 296 default: 297 ret = -EINVAL; 298 } 299 mutex_unlock(&indio_dev->mlock); 300 301 return ret ? ret : len; 302 } 303 304 static ssize_t adf4350_read(struct iio_dev *indio_dev, 305 uintptr_t private, 306 const struct iio_chan_spec *chan, 307 char *buf) 308 { 309 struct adf4350_state *st = iio_priv(indio_dev); 310 unsigned long long val; 311 int ret = 0; 312 313 mutex_lock(&indio_dev->mlock); 314 switch ((u32)private) { 315 case ADF4350_FREQ: 316 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * 317 (u64)st->fpfd; 318 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); 319 /* PLL unlocked? return error */ 320 if (gpio_is_valid(st->pdata->gpio_lock_detect)) 321 if (!gpio_get_value(st->pdata->gpio_lock_detect)) { 322 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 323 ret = -EBUSY; 324 } 325 break; 326 case ADF4350_FREQ_REFIN: 327 if (st->clk) 328 st->clkin = clk_get_rate(st->clk); 329 330 val = st->clkin; 331 break; 332 case ADF4350_FREQ_RESOLUTION: 333 val = st->chspc; 334 break; 335 case ADF4350_PWRDOWN: 336 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); 337 break; 338 default: 339 ret = -EINVAL; 340 val = 0; 341 } 342 mutex_unlock(&indio_dev->mlock); 343 344 return ret < 0 ? ret : sprintf(buf, "%llu\n", val); 345 } 346 347 #define _ADF4350_EXT_INFO(_name, _ident) { \ 348 .name = _name, \ 349 .read = adf4350_read, \ 350 .write = adf4350_write, \ 351 .private = _ident, \ 352 .shared = IIO_SEPARATE, \ 353 } 354 355 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = { 356 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are 357 * values > 2^32 in order to support the entire frequency range 358 * in Hz. Using scale is a bit ugly. 359 */ 360 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ), 361 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION), 362 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN), 363 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN), 364 { }, 365 }; 366 367 static const struct iio_chan_spec adf4350_chan = { 368 .type = IIO_ALTVOLTAGE, 369 .indexed = 1, 370 .output = 1, 371 .ext_info = adf4350_ext_info, 372 }; 373 374 static const struct iio_info adf4350_info = { 375 .debugfs_reg_access = &adf4350_reg_access, 376 }; 377 378 #ifdef CONFIG_OF 379 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 380 { 381 struct device_node *np = dev->of_node; 382 struct adf4350_platform_data *pdata; 383 unsigned int tmp; 384 int ret; 385 386 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 387 if (!pdata) 388 return NULL; 389 390 snprintf(&pdata->name[0], SPI_NAME_SIZE - 1, "%pOFn", np); 391 392 tmp = 10000; 393 of_property_read_u32(np, "adi,channel-spacing", &tmp); 394 pdata->channel_spacing = tmp; 395 396 tmp = 0; 397 of_property_read_u32(np, "adi,power-up-frequency", &tmp); 398 pdata->power_up_frequency = tmp; 399 400 tmp = 0; 401 of_property_read_u32(np, "adi,reference-div-factor", &tmp); 402 pdata->ref_div_factor = tmp; 403 404 ret = of_get_gpio(np, 0); 405 if (ret < 0) 406 pdata->gpio_lock_detect = -1; 407 else 408 pdata->gpio_lock_detect = ret; 409 410 pdata->ref_doubler_en = of_property_read_bool(np, 411 "adi,reference-doubler-enable"); 412 pdata->ref_div2_en = of_property_read_bool(np, 413 "adi,reference-div2-enable"); 414 415 /* r2_user_settings */ 416 pdata->r2_user_settings = of_property_read_bool(np, 417 "adi,phase-detector-polarity-positive-enable") ? 418 ADF4350_REG2_PD_POLARITY_POS : 0; 419 pdata->r2_user_settings |= of_property_read_bool(np, 420 "adi,lock-detect-precision-6ns-enable") ? 421 ADF4350_REG2_LDP_6ns : 0; 422 pdata->r2_user_settings |= of_property_read_bool(np, 423 "adi,lock-detect-function-integer-n-enable") ? 424 ADF4350_REG2_LDF_INT_N : 0; 425 426 tmp = 2500; 427 of_property_read_u32(np, "adi,charge-pump-current", &tmp); 428 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); 429 430 tmp = 0; 431 of_property_read_u32(np, "adi,muxout-select", &tmp); 432 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); 433 434 pdata->r2_user_settings |= of_property_read_bool(np, 435 "adi,low-spur-mode-enable") ? 436 ADF4350_REG2_NOISE_MODE(0x3) : 0; 437 438 /* r3_user_settings */ 439 440 pdata->r3_user_settings = of_property_read_bool(np, 441 "adi,cycle-slip-reduction-enable") ? 442 ADF4350_REG3_12BIT_CSR_EN : 0; 443 pdata->r3_user_settings |= of_property_read_bool(np, 444 "adi,charge-cancellation-enable") ? 445 ADF4351_REG3_CHARGE_CANCELLATION_EN : 0; 446 447 pdata->r3_user_settings |= of_property_read_bool(np, 448 "adi,anti-backlash-3ns-enable") ? 449 ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0; 450 pdata->r3_user_settings |= of_property_read_bool(np, 451 "adi,band-select-clock-mode-high-enable") ? 452 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0; 453 454 tmp = 0; 455 of_property_read_u32(np, "adi,12bit-clk-divider", &tmp); 456 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); 457 458 tmp = 0; 459 of_property_read_u32(np, "adi,clk-divider-mode", &tmp); 460 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); 461 462 /* r4_user_settings */ 463 464 pdata->r4_user_settings = of_property_read_bool(np, 465 "adi,aux-output-enable") ? 466 ADF4350_REG4_AUX_OUTPUT_EN : 0; 467 pdata->r4_user_settings |= of_property_read_bool(np, 468 "adi,aux-output-fundamental-enable") ? 469 ADF4350_REG4_AUX_OUTPUT_FUND : 0; 470 pdata->r4_user_settings |= of_property_read_bool(np, 471 "adi,mute-till-lock-enable") ? 472 ADF4350_REG4_MUTE_TILL_LOCK_EN : 0; 473 474 tmp = 0; 475 of_property_read_u32(np, "adi,output-power", &tmp); 476 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); 477 478 tmp = 0; 479 of_property_read_u32(np, "adi,aux-output-power", &tmp); 480 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); 481 482 return pdata; 483 } 484 #else 485 static 486 struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 487 { 488 return NULL; 489 } 490 #endif 491 492 static int adf4350_probe(struct spi_device *spi) 493 { 494 struct adf4350_platform_data *pdata; 495 struct iio_dev *indio_dev; 496 struct adf4350_state *st; 497 struct clk *clk = NULL; 498 int ret; 499 500 if (spi->dev.of_node) { 501 pdata = adf4350_parse_dt(&spi->dev); 502 if (pdata == NULL) 503 return -EINVAL; 504 } else { 505 pdata = spi->dev.platform_data; 506 } 507 508 if (!pdata) { 509 dev_warn(&spi->dev, "no platform data? using default\n"); 510 pdata = &default_pdata; 511 } 512 513 if (!pdata->clkin) { 514 clk = devm_clk_get(&spi->dev, "clkin"); 515 if (IS_ERR(clk)) 516 return -EPROBE_DEFER; 517 518 ret = clk_prepare_enable(clk); 519 if (ret < 0) 520 return ret; 521 } 522 523 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 524 if (indio_dev == NULL) { 525 ret = -ENOMEM; 526 goto error_disable_clk; 527 } 528 529 st = iio_priv(indio_dev); 530 531 st->reg = devm_regulator_get(&spi->dev, "vcc"); 532 if (!IS_ERR(st->reg)) { 533 ret = regulator_enable(st->reg); 534 if (ret) 535 goto error_disable_clk; 536 } 537 538 spi_set_drvdata(spi, indio_dev); 539 st->spi = spi; 540 st->pdata = pdata; 541 542 indio_dev->dev.parent = &spi->dev; 543 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 544 spi_get_device_id(spi)->name; 545 546 indio_dev->info = &adf4350_info; 547 indio_dev->modes = INDIO_DIRECT_MODE; 548 indio_dev->channels = &adf4350_chan; 549 indio_dev->num_channels = 1; 550 551 st->chspc = pdata->channel_spacing; 552 if (clk) { 553 st->clk = clk; 554 st->clkin = clk_get_rate(clk); 555 } else { 556 st->clkin = pdata->clkin; 557 } 558 559 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? 560 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ; 561 562 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 563 564 if (gpio_is_valid(pdata->gpio_lock_detect)) { 565 ret = devm_gpio_request(&spi->dev, pdata->gpio_lock_detect, 566 indio_dev->name); 567 if (ret) { 568 dev_err(&spi->dev, "fail to request lock detect GPIO-%d", 569 pdata->gpio_lock_detect); 570 goto error_disable_reg; 571 } 572 gpio_direction_input(pdata->gpio_lock_detect); 573 } 574 575 if (pdata->power_up_frequency) { 576 ret = adf4350_set_freq(st, pdata->power_up_frequency); 577 if (ret) 578 goto error_disable_reg; 579 } 580 581 ret = iio_device_register(indio_dev); 582 if (ret) 583 goto error_disable_reg; 584 585 return 0; 586 587 error_disable_reg: 588 if (!IS_ERR(st->reg)) 589 regulator_disable(st->reg); 590 error_disable_clk: 591 if (clk) 592 clk_disable_unprepare(clk); 593 594 return ret; 595 } 596 597 static int adf4350_remove(struct spi_device *spi) 598 { 599 struct iio_dev *indio_dev = spi_get_drvdata(spi); 600 struct adf4350_state *st = iio_priv(indio_dev); 601 struct regulator *reg = st->reg; 602 603 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 604 adf4350_sync_config(st); 605 606 iio_device_unregister(indio_dev); 607 608 if (st->clk) 609 clk_disable_unprepare(st->clk); 610 611 if (!IS_ERR(reg)) 612 regulator_disable(reg); 613 614 return 0; 615 } 616 617 static const struct of_device_id adf4350_of_match[] = { 618 { .compatible = "adi,adf4350", }, 619 { .compatible = "adi,adf4351", }, 620 { /* sentinel */ }, 621 }; 622 MODULE_DEVICE_TABLE(of, adf4350_of_match); 623 624 static const struct spi_device_id adf4350_id[] = { 625 {"adf4350", 4350}, 626 {"adf4351", 4351}, 627 {} 628 }; 629 MODULE_DEVICE_TABLE(spi, adf4350_id); 630 631 static struct spi_driver adf4350_driver = { 632 .driver = { 633 .name = "adf4350", 634 .of_match_table = of_match_ptr(adf4350_of_match), 635 }, 636 .probe = adf4350_probe, 637 .remove = adf4350_remove, 638 .id_table = adf4350_id, 639 }; 640 module_spi_driver(adf4350_driver); 641 642 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 643 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL"); 644 MODULE_LICENSE("GPL v2"); 645