1 /* 2 * ADF4350/ADF4351 SPI Wideband Synthesizer driver 3 * 4 * Copyright 2012-2013 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/gcd.h> 18 #include <linux/gpio.h> 19 #include <asm/div64.h> 20 #include <linux/clk.h> 21 #include <linux/of.h> 22 #include <linux/of_gpio.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/frequency/adf4350.h> 27 28 enum { 29 ADF4350_FREQ, 30 ADF4350_FREQ_REFIN, 31 ADF4350_FREQ_RESOLUTION, 32 ADF4350_PWRDOWN, 33 }; 34 35 struct adf4350_state { 36 struct spi_device *spi; 37 struct regulator *reg; 38 struct adf4350_platform_data *pdata; 39 struct clk *clk; 40 unsigned long clkin; 41 unsigned long chspc; /* Channel Spacing */ 42 unsigned long fpfd; /* Phase Frequency Detector */ 43 unsigned long min_out_freq; 44 unsigned r0_fract; 45 unsigned r0_int; 46 unsigned r1_mod; 47 unsigned r4_rf_div_sel; 48 unsigned long regs[6]; 49 unsigned long regs_hw[6]; 50 unsigned long long freq_req; 51 /* 52 * DMA (thus cache coherency maintenance) requires the 53 * transfer buffers to live in their own cache lines. 54 */ 55 __be32 val ____cacheline_aligned; 56 }; 57 58 static struct adf4350_platform_data default_pdata = { 59 .channel_spacing = 10000, 60 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS | 61 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500), 62 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0), 63 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) | 64 ADF4350_REG4_MUTE_TILL_LOCK_EN, 65 .gpio_lock_detect = -1, 66 }; 67 68 static int adf4350_sync_config(struct adf4350_state *st) 69 { 70 int ret, i, doublebuf = 0; 71 72 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { 73 if ((st->regs_hw[i] != st->regs[i]) || 74 ((i == ADF4350_REG0) && doublebuf)) { 75 76 switch (i) { 77 case ADF4350_REG1: 78 case ADF4350_REG4: 79 doublebuf = 1; 80 break; 81 } 82 83 st->val = cpu_to_be32(st->regs[i] | i); 84 ret = spi_write(st->spi, &st->val, 4); 85 if (ret < 0) 86 return ret; 87 st->regs_hw[i] = st->regs[i]; 88 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", 89 i, (u32)st->regs[i] | i); 90 } 91 } 92 return 0; 93 } 94 95 static int adf4350_reg_access(struct iio_dev *indio_dev, 96 unsigned reg, unsigned writeval, 97 unsigned *readval) 98 { 99 struct adf4350_state *st = iio_priv(indio_dev); 100 int ret; 101 102 if (reg > ADF4350_REG5) 103 return -EINVAL; 104 105 mutex_lock(&indio_dev->mlock); 106 if (readval == NULL) { 107 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); 108 ret = adf4350_sync_config(st); 109 } else { 110 *readval = st->regs_hw[reg]; 111 ret = 0; 112 } 113 mutex_unlock(&indio_dev->mlock); 114 115 return ret; 116 } 117 118 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) 119 { 120 struct adf4350_platform_data *pdata = st->pdata; 121 122 do { 123 r_cnt++; 124 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / 125 (r_cnt * (pdata->ref_div2_en ? 2 : 1)); 126 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); 127 128 return r_cnt; 129 } 130 131 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) 132 { 133 struct adf4350_platform_data *pdata = st->pdata; 134 u64 tmp; 135 u32 div_gcd, prescaler, chspc; 136 u16 mdiv, r_cnt = 0; 137 u8 band_sel_div; 138 139 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) 140 return -EINVAL; 141 142 if (freq > ADF4350_MAX_FREQ_45_PRESC) { 143 prescaler = ADF4350_REG1_PRESCALER; 144 mdiv = 75; 145 } else { 146 prescaler = 0; 147 mdiv = 23; 148 } 149 150 st->r4_rf_div_sel = 0; 151 152 while (freq < ADF4350_MIN_VCO_FREQ) { 153 freq <<= 1; 154 st->r4_rf_div_sel++; 155 } 156 157 /* 158 * Allow a predefined reference division factor 159 * if not set, compute our own 160 */ 161 if (pdata->ref_div_factor) 162 r_cnt = pdata->ref_div_factor - 1; 163 164 chspc = st->chspc; 165 166 do { 167 do { 168 do { 169 r_cnt = adf4350_tune_r_cnt(st, r_cnt); 170 st->r1_mod = st->fpfd / chspc; 171 if (r_cnt > ADF4350_MAX_R_CNT) { 172 /* try higher spacing values */ 173 chspc++; 174 r_cnt = 0; 175 } 176 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); 177 } while (r_cnt == 0); 178 179 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); 180 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ 181 st->r0_fract = do_div(tmp, st->r1_mod); 182 st->r0_int = tmp; 183 } while (mdiv > st->r0_int); 184 185 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); 186 187 if (st->r0_fract && st->r1_mod) { 188 div_gcd = gcd(st->r1_mod, st->r0_fract); 189 st->r1_mod /= div_gcd; 190 st->r0_fract /= div_gcd; 191 } else { 192 st->r0_fract = 0; 193 st->r1_mod = 1; 194 } 195 196 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" 197 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n" 198 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n", 199 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, 200 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", 201 band_sel_div); 202 203 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | 204 ADF4350_REG0_FRACT(st->r0_fract); 205 206 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | 207 ADF4350_REG1_MOD(st->r1_mod) | 208 prescaler; 209 210 st->regs[ADF4350_REG2] = 211 ADF4350_REG2_10BIT_R_CNT(r_cnt) | 212 ADF4350_REG2_DOUBLE_BUFF_EN | 213 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) | 214 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) | 215 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS | 216 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N | 217 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) | 218 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3))); 219 220 st->regs[ADF4350_REG3] = pdata->r3_user_settings & 221 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) | 222 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) | 223 ADF4350_REG3_12BIT_CSR_EN | 224 ADF4351_REG3_CHARGE_CANCELLATION_EN | 225 ADF4351_REG3_ANTI_BACKLASH_3ns_EN | 226 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH); 227 228 st->regs[ADF4350_REG4] = 229 ADF4350_REG4_FEEDBACK_FUND | 230 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | 231 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) | 232 ADF4350_REG4_RF_OUT_EN | 233 (pdata->r4_user_settings & 234 (ADF4350_REG4_OUTPUT_PWR(0x3) | 235 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) | 236 ADF4350_REG4_AUX_OUTPUT_EN | 237 ADF4350_REG4_AUX_OUTPUT_FUND | 238 ADF4350_REG4_MUTE_TILL_LOCK_EN)); 239 240 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; 241 st->freq_req = freq; 242 243 return adf4350_sync_config(st); 244 } 245 246 static ssize_t adf4350_write(struct iio_dev *indio_dev, 247 uintptr_t private, 248 const struct iio_chan_spec *chan, 249 const char *buf, size_t len) 250 { 251 struct adf4350_state *st = iio_priv(indio_dev); 252 unsigned long long readin; 253 unsigned long tmp; 254 int ret; 255 256 ret = kstrtoull(buf, 10, &readin); 257 if (ret) 258 return ret; 259 260 mutex_lock(&indio_dev->mlock); 261 switch ((u32)private) { 262 case ADF4350_FREQ: 263 ret = adf4350_set_freq(st, readin); 264 break; 265 case ADF4350_FREQ_REFIN: 266 if (readin > ADF4350_MAX_FREQ_REFIN) { 267 ret = -EINVAL; 268 break; 269 } 270 271 if (st->clk) { 272 tmp = clk_round_rate(st->clk, readin); 273 if (tmp != readin) { 274 ret = -EINVAL; 275 break; 276 } 277 ret = clk_set_rate(st->clk, tmp); 278 if (ret < 0) 279 break; 280 } 281 st->clkin = readin; 282 ret = adf4350_set_freq(st, st->freq_req); 283 break; 284 case ADF4350_FREQ_RESOLUTION: 285 if (readin == 0) 286 ret = -EINVAL; 287 else 288 st->chspc = readin; 289 break; 290 case ADF4350_PWRDOWN: 291 if (readin) 292 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 293 else 294 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; 295 296 adf4350_sync_config(st); 297 break; 298 default: 299 ret = -EINVAL; 300 } 301 mutex_unlock(&indio_dev->mlock); 302 303 return ret ? ret : len; 304 } 305 306 static ssize_t adf4350_read(struct iio_dev *indio_dev, 307 uintptr_t private, 308 const struct iio_chan_spec *chan, 309 char *buf) 310 { 311 struct adf4350_state *st = iio_priv(indio_dev); 312 unsigned long long val; 313 int ret = 0; 314 315 mutex_lock(&indio_dev->mlock); 316 switch ((u32)private) { 317 case ADF4350_FREQ: 318 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * 319 (u64)st->fpfd; 320 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); 321 /* PLL unlocked? return error */ 322 if (gpio_is_valid(st->pdata->gpio_lock_detect)) 323 if (!gpio_get_value(st->pdata->gpio_lock_detect)) { 324 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 325 ret = -EBUSY; 326 } 327 break; 328 case ADF4350_FREQ_REFIN: 329 if (st->clk) 330 st->clkin = clk_get_rate(st->clk); 331 332 val = st->clkin; 333 break; 334 case ADF4350_FREQ_RESOLUTION: 335 val = st->chspc; 336 break; 337 case ADF4350_PWRDOWN: 338 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); 339 break; 340 default: 341 ret = -EINVAL; 342 val = 0; 343 } 344 mutex_unlock(&indio_dev->mlock); 345 346 return ret < 0 ? ret : sprintf(buf, "%llu\n", val); 347 } 348 349 #define _ADF4350_EXT_INFO(_name, _ident) { \ 350 .name = _name, \ 351 .read = adf4350_read, \ 352 .write = adf4350_write, \ 353 .private = _ident, \ 354 } 355 356 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = { 357 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are 358 * values > 2^32 in order to support the entire frequency range 359 * in Hz. Using scale is a bit ugly. 360 */ 361 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ), 362 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION), 363 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN), 364 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN), 365 { }, 366 }; 367 368 static const struct iio_chan_spec adf4350_chan = { 369 .type = IIO_ALTVOLTAGE, 370 .indexed = 1, 371 .output = 1, 372 .ext_info = adf4350_ext_info, 373 }; 374 375 static const struct iio_info adf4350_info = { 376 .debugfs_reg_access = &adf4350_reg_access, 377 .driver_module = THIS_MODULE, 378 }; 379 380 #ifdef CONFIG_OF 381 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 382 { 383 struct device_node *np = dev->of_node; 384 struct adf4350_platform_data *pdata; 385 unsigned int tmp; 386 int ret; 387 388 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 389 if (!pdata) { 390 dev_err(dev, "could not allocate memory for platform data\n"); 391 return NULL; 392 } 393 394 strncpy(&pdata->name[0], np->name, SPI_NAME_SIZE - 1); 395 396 tmp = 10000; 397 of_property_read_u32(np, "adi,channel-spacing", &tmp); 398 pdata->channel_spacing = tmp; 399 400 tmp = 0; 401 of_property_read_u32(np, "adi,power-up-frequency", &tmp); 402 pdata->power_up_frequency = tmp; 403 404 tmp = 0; 405 of_property_read_u32(np, "adi,reference-div-factor", &tmp); 406 pdata->ref_div_factor = tmp; 407 408 ret = of_get_gpio(np, 0); 409 if (ret < 0) 410 pdata->gpio_lock_detect = -1; 411 else 412 pdata->gpio_lock_detect = ret; 413 414 pdata->ref_doubler_en = of_property_read_bool(np, 415 "adi,reference-doubler-enable"); 416 pdata->ref_div2_en = of_property_read_bool(np, 417 "adi,reference-div2-enable"); 418 419 /* r2_user_settings */ 420 pdata->r2_user_settings = of_property_read_bool(np, 421 "adi,phase-detector-polarity-positive-enable") ? 422 ADF4350_REG2_PD_POLARITY_POS : 0; 423 pdata->r2_user_settings |= of_property_read_bool(np, 424 "adi,lock-detect-precision-6ns-enable") ? 425 ADF4350_REG2_LDP_6ns : 0; 426 pdata->r2_user_settings |= of_property_read_bool(np, 427 "adi,lock-detect-function-integer-n-enable") ? 428 ADF4350_REG2_LDF_INT_N : 0; 429 430 tmp = 2500; 431 of_property_read_u32(np, "adi,charge-pump-current", &tmp); 432 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); 433 434 tmp = 0; 435 of_property_read_u32(np, "adi,muxout-select", &tmp); 436 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); 437 438 pdata->r2_user_settings |= of_property_read_bool(np, 439 "adi,low-spur-mode-enable") ? 440 ADF4350_REG2_NOISE_MODE(0x3) : 0; 441 442 /* r3_user_settings */ 443 444 pdata->r3_user_settings = of_property_read_bool(np, 445 "adi,cycle-slip-reduction-enable") ? 446 ADF4350_REG3_12BIT_CSR_EN : 0; 447 pdata->r3_user_settings |= of_property_read_bool(np, 448 "adi,charge-cancellation-enable") ? 449 ADF4351_REG3_CHARGE_CANCELLATION_EN : 0; 450 451 pdata->r3_user_settings |= of_property_read_bool(np, 452 "adi,anti-backlash-3ns-enable") ? 453 ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0; 454 pdata->r3_user_settings |= of_property_read_bool(np, 455 "adi,band-select-clock-mode-high-enable") ? 456 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0; 457 458 tmp = 0; 459 of_property_read_u32(np, "adi,12bit-clk-divider", &tmp); 460 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); 461 462 tmp = 0; 463 of_property_read_u32(np, "adi,clk-divider-mode", &tmp); 464 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); 465 466 /* r4_user_settings */ 467 468 pdata->r4_user_settings = of_property_read_bool(np, 469 "adi,aux-output-enable") ? 470 ADF4350_REG4_AUX_OUTPUT_EN : 0; 471 pdata->r4_user_settings |= of_property_read_bool(np, 472 "adi,aux-output-fundamental-enable") ? 473 ADF4350_REG4_AUX_OUTPUT_FUND : 0; 474 pdata->r4_user_settings |= of_property_read_bool(np, 475 "adi,mute-till-lock-enable") ? 476 ADF4350_REG4_MUTE_TILL_LOCK_EN : 0; 477 478 tmp = 0; 479 of_property_read_u32(np, "adi,output-power", &tmp); 480 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); 481 482 tmp = 0; 483 of_property_read_u32(np, "adi,aux-output-power", &tmp); 484 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); 485 486 return pdata; 487 } 488 #else 489 static 490 struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 491 { 492 return NULL; 493 } 494 #endif 495 496 static int adf4350_probe(struct spi_device *spi) 497 { 498 struct adf4350_platform_data *pdata; 499 struct iio_dev *indio_dev; 500 struct adf4350_state *st; 501 struct clk *clk = NULL; 502 int ret; 503 504 if (spi->dev.of_node) { 505 pdata = adf4350_parse_dt(&spi->dev); 506 if (pdata == NULL) 507 return -EINVAL; 508 } else { 509 pdata = spi->dev.platform_data; 510 } 511 512 if (!pdata) { 513 dev_warn(&spi->dev, "no platform data? using default\n"); 514 pdata = &default_pdata; 515 } 516 517 if (!pdata->clkin) { 518 clk = clk_get(&spi->dev, "clkin"); 519 if (IS_ERR(clk)) 520 return -EPROBE_DEFER; 521 522 ret = clk_prepare_enable(clk); 523 if (ret < 0) 524 return ret; 525 } 526 527 indio_dev = iio_device_alloc(sizeof(*st)); 528 if (indio_dev == NULL) 529 return -ENOMEM; 530 531 st = iio_priv(indio_dev); 532 533 st->reg = regulator_get(&spi->dev, "vcc"); 534 if (!IS_ERR(st->reg)) { 535 ret = regulator_enable(st->reg); 536 if (ret) 537 goto error_put_reg; 538 } 539 540 spi_set_drvdata(spi, indio_dev); 541 st->spi = spi; 542 st->pdata = pdata; 543 544 indio_dev->dev.parent = &spi->dev; 545 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 546 spi_get_device_id(spi)->name; 547 548 indio_dev->info = &adf4350_info; 549 indio_dev->modes = INDIO_DIRECT_MODE; 550 indio_dev->channels = &adf4350_chan; 551 indio_dev->num_channels = 1; 552 553 st->chspc = pdata->channel_spacing; 554 if (clk) { 555 st->clk = clk; 556 st->clkin = clk_get_rate(clk); 557 } else { 558 st->clkin = pdata->clkin; 559 } 560 561 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? 562 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ; 563 564 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 565 566 if (gpio_is_valid(pdata->gpio_lock_detect)) { 567 ret = gpio_request(pdata->gpio_lock_detect, indio_dev->name); 568 if (ret) { 569 dev_err(&spi->dev, "fail to request lock detect GPIO-%d", 570 pdata->gpio_lock_detect); 571 goto error_disable_reg; 572 } 573 gpio_direction_input(pdata->gpio_lock_detect); 574 } 575 576 if (pdata->power_up_frequency) { 577 ret = adf4350_set_freq(st, pdata->power_up_frequency); 578 if (ret) 579 goto error_free_gpio; 580 } 581 582 ret = iio_device_register(indio_dev); 583 if (ret) 584 goto error_free_gpio; 585 586 return 0; 587 588 error_free_gpio: 589 if (gpio_is_valid(pdata->gpio_lock_detect)) 590 gpio_free(pdata->gpio_lock_detect); 591 592 error_disable_reg: 593 if (!IS_ERR(st->reg)) 594 regulator_disable(st->reg); 595 error_put_reg: 596 if (!IS_ERR(st->reg)) 597 regulator_put(st->reg); 598 599 if (clk) 600 clk_disable_unprepare(clk); 601 iio_device_free(indio_dev); 602 603 return ret; 604 } 605 606 static int adf4350_remove(struct spi_device *spi) 607 { 608 struct iio_dev *indio_dev = spi_get_drvdata(spi); 609 struct adf4350_state *st = iio_priv(indio_dev); 610 struct regulator *reg = st->reg; 611 612 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 613 adf4350_sync_config(st); 614 615 iio_device_unregister(indio_dev); 616 617 if (st->clk) 618 clk_disable_unprepare(st->clk); 619 620 if (!IS_ERR(reg)) { 621 regulator_disable(reg); 622 regulator_put(reg); 623 } 624 625 if (gpio_is_valid(st->pdata->gpio_lock_detect)) 626 gpio_free(st->pdata->gpio_lock_detect); 627 628 iio_device_free(indio_dev); 629 630 return 0; 631 } 632 633 static const struct spi_device_id adf4350_id[] = { 634 {"adf4350", 4350}, 635 {"adf4351", 4351}, 636 {} 637 }; 638 639 static struct spi_driver adf4350_driver = { 640 .driver = { 641 .name = "adf4350", 642 .owner = THIS_MODULE, 643 }, 644 .probe = adf4350_probe, 645 .remove = adf4350_remove, 646 .id_table = adf4350_id, 647 }; 648 module_spi_driver(adf4350_driver); 649 650 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 651 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL"); 652 MODULE_LICENSE("GPL v2"); 653