1 /* 2 * AD9523 SPI Low Jitter Clock Generator 3 * 4 * Copyright 2012 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/delay.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/frequency/ad9523.h> 23 24 #define AD9523_READ (1 << 15) 25 #define AD9523_WRITE (0 << 15) 26 #define AD9523_CNT(x) (((x) - 1) << 13) 27 #define AD9523_ADDR(x) ((x) & 0xFFF) 28 29 #define AD9523_R1B (1 << 16) 30 #define AD9523_R2B (2 << 16) 31 #define AD9523_R3B (3 << 16) 32 #define AD9523_TRANSF_LEN(x) ((x) >> 16) 33 34 #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0) 35 #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2) 36 #define AD9523_PART_REGISTER (AD9523_R1B | 0x3) 37 #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4) 38 39 #define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6) 40 41 #define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11) 42 #define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13) 43 #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14) 44 #define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17) 45 #define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19) 46 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A) 47 #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B) 48 #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C) 49 #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D) 50 51 #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0) 52 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1) 53 #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2) 54 #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3) 55 #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4) 56 #define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6) 57 #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7) 58 59 #define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch)) 60 61 #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA) 62 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB) 63 64 #define AD9523_READBACK_0 (AD9523_R1B | 0x22C) 65 #define AD9523_READBACK_1 (AD9523_R1B | 0x22D) 66 67 #define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232) 68 #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233) 69 #define AD9523_IO_UPDATE (AD9523_R1B | 0x234) 70 71 #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00) 72 #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01) 73 #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02) 74 #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03) 75 76 /* AD9523_SERIAL_PORT_CONFIG */ 77 78 #define AD9523_SER_CONF_SDO_ACTIVE (1 << 7) 79 #define AD9523_SER_CONF_SOFT_RESET (1 << 5) 80 81 /* AD9523_READBACK_CTRL */ 82 #define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0) 83 84 /* AD9523_PLL1_CHARGE_PUMP_CTRL */ 85 #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F) 86 #define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7) 87 #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8) 88 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8) 89 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8) 90 #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8) 91 #define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10) 92 #define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10) 93 #define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10) 94 #define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10) 95 96 /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */ 97 #define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7) 98 #define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6) 99 #define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5) 100 #define AD9523_PLL1_REFB_RCV_EN (1 << 4) 101 #define AD9523_PLL1_REFA_RCV_EN (1 << 3) 102 #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2) 103 #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1) 104 #define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0) 105 106 /* AD9523_PLL1_REF_CTRL */ 107 #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7) 108 #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6) 109 #define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5) 110 #define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5) 111 #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4) 112 #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3) 113 #define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2) 114 #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1) 115 #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0) 116 117 /* AD9523_PLL1_MISC_CTRL */ 118 #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7) 119 #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6) 120 #define AD9523_PLL1_REF_MODE(x) ((x) << 2) 121 #define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1) 122 #define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0) 123 124 /* AD9523_PLL1_LOOP_FILTER_CTRL */ 125 #define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF) 126 127 /* AD9523_PLL2_CHARGE_PUMP */ 128 #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500) 129 130 /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */ 131 #define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6) 132 #define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0) 133 #define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a)) 134 135 /* AD9523_PLL2_CTRL */ 136 #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0) 137 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0) 138 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0) 139 #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0) 140 #define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2) 141 #define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2) 142 #define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2) 143 #define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1) 144 #define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4) 145 #define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5) 146 #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7) 147 148 /* AD9523_PLL2_VCO_CTRL */ 149 #define AD9523_PLL2_VCO_CALIBRATE (1 << 1) 150 #define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2) 151 #define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3) 152 #define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4) 153 154 /* AD9523_PLL2_VCO_DIVIDER */ 155 #define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0) 156 #define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4) 157 #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2) 158 #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6) 159 160 /* AD9523_PLL2_LOOP_FILTER_CTRL */ 161 #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0) 162 #define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3) 163 #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6) 164 #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8) 165 166 /* AD9523_PLL2_R2_DIVIDER */ 167 #define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0) 168 169 /* AD9523_CHANNEL_CLOCK_DIST */ 170 #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18) 171 #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F) 172 #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8) 173 #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1) 174 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7) 175 #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6) 176 #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5) 177 #define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4) 178 #define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0) 179 180 /* AD9523_PLL1_OUTPUT_CTRL */ 181 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7) 182 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6) 183 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5) 184 #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4) 185 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0) 186 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0) 187 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0) 188 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0) 189 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0) 190 191 /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */ 192 #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7) 193 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6) 194 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5) 195 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4) 196 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3) 197 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2) 198 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1) 199 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0) 200 201 /* AD9523_READBACK_0 */ 202 #define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7) 203 #define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6) 204 #define AD9523_READBACK_0_STAT_VCXO (1 << 5) 205 #define AD9523_READBACK_0_STAT_REF_TEST (1 << 4) 206 #define AD9523_READBACK_0_STAT_REFB (1 << 3) 207 #define AD9523_READBACK_0_STAT_REFA (1 << 2) 208 #define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1) 209 #define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0) 210 211 /* AD9523_READBACK_1 */ 212 #define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3) 213 #define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2) 214 #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0) 215 216 /* AD9523_STATUS_SIGNALS */ 217 #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16) 218 #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302) 219 /* AD9523_POWER_DOWN_CTRL */ 220 #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2) 221 #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1) 222 #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0) 223 224 /* AD9523_IO_UPDATE */ 225 #define AD9523_IO_UPDATE_EN (1 << 0) 226 227 /* AD9523_EEPROM_DATA_XFER_STATUS */ 228 #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0) 229 230 /* AD9523_EEPROM_ERROR_READBACK */ 231 #define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0) 232 233 /* AD9523_EEPROM_CTRL1 */ 234 #define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1) 235 #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0) 236 237 /* AD9523_EEPROM_CTRL2 */ 238 #define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0) 239 240 #define AD9523_NUM_CHAN 14 241 #define AD9523_NUM_CHAN_ALT_CLK_SRC 10 242 243 /* Helpers to avoid excess line breaks */ 244 #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b) 245 #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0) 246 247 enum { 248 AD9523_STAT_PLL1_LD, 249 AD9523_STAT_PLL2_LD, 250 AD9523_STAT_REFA, 251 AD9523_STAT_REFB, 252 AD9523_STAT_REF_TEST, 253 AD9523_STAT_VCXO, 254 AD9523_STAT_PLL2_FB_CLK, 255 AD9523_STAT_PLL2_REF_CLK, 256 AD9523_SYNC, 257 AD9523_EEPROM, 258 }; 259 260 enum { 261 AD9523_VCO1, 262 AD9523_VCO2, 263 AD9523_VCXO, 264 AD9523_NUM_CLK_SRC, 265 }; 266 267 struct ad9523_state { 268 struct spi_device *spi; 269 struct regulator *reg; 270 struct ad9523_platform_data *pdata; 271 struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN]; 272 struct gpio_desc *pwrdown_gpio; 273 struct gpio_desc *reset_gpio; 274 struct gpio_desc *sync_gpio; 275 276 unsigned long vcxo_freq; 277 unsigned long vco_freq; 278 unsigned long vco_out_freq[AD9523_NUM_CLK_SRC]; 279 unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC]; 280 281 /* 282 * Lock for accessing device registers. Some operations require 283 * multiple consecutive R/W operations, during which the device 284 * shouldn't be interrupted. The buffers are also shared across 285 * all operations so need to be protected on stand alone reads and 286 * writes. 287 */ 288 struct mutex lock; 289 290 /* 291 * DMA (thus cache coherency maintenance) requires the 292 * transfer buffers to live in their own cache lines. 293 */ 294 union { 295 __be32 d32; 296 u8 d8[4]; 297 } data[2] ____cacheline_aligned; 298 }; 299 300 static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr) 301 { 302 struct ad9523_state *st = iio_priv(indio_dev); 303 int ret; 304 305 /* We encode the register size 1..3 bytes into the register address. 306 * On transfer we get the size from the register datum, and make sure 307 * the result is properly aligned. 308 */ 309 310 struct spi_transfer t[] = { 311 { 312 .tx_buf = &st->data[0].d8[2], 313 .len = 2, 314 }, { 315 .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], 316 .len = AD9523_TRANSF_LEN(addr), 317 }, 318 }; 319 320 st->data[0].d32 = cpu_to_be32(AD9523_READ | 321 AD9523_CNT(AD9523_TRANSF_LEN(addr)) | 322 AD9523_ADDR(addr)); 323 324 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 325 if (ret < 0) 326 dev_err(&indio_dev->dev, "read failed (%d)", ret); 327 else 328 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >> 329 (8 * (3 - AD9523_TRANSF_LEN(addr)))); 330 331 return ret; 332 }; 333 334 static int ad9523_write(struct iio_dev *indio_dev, 335 unsigned int addr, unsigned int val) 336 { 337 struct ad9523_state *st = iio_priv(indio_dev); 338 int ret; 339 struct spi_transfer t[] = { 340 { 341 .tx_buf = &st->data[0].d8[2], 342 .len = 2, 343 }, { 344 .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], 345 .len = AD9523_TRANSF_LEN(addr), 346 }, 347 }; 348 349 st->data[0].d32 = cpu_to_be32(AD9523_WRITE | 350 AD9523_CNT(AD9523_TRANSF_LEN(addr)) | 351 AD9523_ADDR(addr)); 352 st->data[1].d32 = cpu_to_be32(val); 353 354 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 355 356 if (ret < 0) 357 dev_err(&indio_dev->dev, "write failed (%d)", ret); 358 359 return ret; 360 } 361 362 static int ad9523_io_update(struct iio_dev *indio_dev) 363 { 364 return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN); 365 } 366 367 static int ad9523_vco_out_map(struct iio_dev *indio_dev, 368 unsigned int ch, unsigned int out) 369 { 370 struct ad9523_state *st = iio_priv(indio_dev); 371 int ret; 372 unsigned int mask; 373 374 switch (ch) { 375 case 0 ... 3: 376 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); 377 if (ret < 0) 378 break; 379 mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch; 380 if (out) { 381 ret |= mask; 382 out = 2; 383 } else { 384 ret &= ~mask; 385 } 386 ret = ad9523_write(indio_dev, 387 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); 388 break; 389 case 4 ... 6: 390 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL); 391 if (ret < 0) 392 break; 393 mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4); 394 if (out) 395 ret |= mask; 396 else 397 ret &= ~mask; 398 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret); 399 break; 400 case 7 ... 9: 401 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); 402 if (ret < 0) 403 break; 404 mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7); 405 if (out) 406 ret |= mask; 407 else 408 ret &= ~mask; 409 ret = ad9523_write(indio_dev, 410 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); 411 break; 412 default: 413 return 0; 414 } 415 416 st->vco_out_map[ch] = out; 417 418 return ret; 419 } 420 421 static int ad9523_set_clock_provider(struct iio_dev *indio_dev, 422 unsigned int ch, unsigned long freq) 423 { 424 struct ad9523_state *st = iio_priv(indio_dev); 425 long tmp1, tmp2; 426 bool use_alt_clk_src; 427 428 switch (ch) { 429 case 0 ... 3: 430 use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]); 431 break; 432 case 4 ... 9: 433 tmp1 = st->vco_out_freq[AD9523_VCO1] / freq; 434 tmp2 = st->vco_out_freq[AD9523_VCO2] / freq; 435 tmp1 *= freq; 436 tmp2 *= freq; 437 use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq)); 438 break; 439 default: 440 /* Ch 10..14: No action required, return success */ 441 return 0; 442 } 443 444 return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src); 445 } 446 447 static int ad9523_store_eeprom(struct iio_dev *indio_dev) 448 { 449 int ret, tmp; 450 451 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 452 AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS); 453 if (ret < 0) 454 return ret; 455 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2, 456 AD9523_EEPROM_CTRL2_REG2EEPROM); 457 if (ret < 0) 458 return ret; 459 460 tmp = 4; 461 do { 462 msleep(20); 463 ret = ad9523_read(indio_dev, 464 AD9523_EEPROM_DATA_XFER_STATUS); 465 if (ret < 0) 466 return ret; 467 } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--); 468 469 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0); 470 if (ret < 0) 471 return ret; 472 473 ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK); 474 if (ret < 0) 475 return ret; 476 477 if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) { 478 dev_err(&indio_dev->dev, "Verify EEPROM failed"); 479 ret = -EIO; 480 } 481 482 return ret; 483 } 484 485 static int ad9523_sync(struct iio_dev *indio_dev) 486 { 487 int ret, tmp; 488 489 ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS); 490 if (ret < 0) 491 return ret; 492 493 tmp = ret; 494 tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; 495 496 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); 497 if (ret < 0) 498 return ret; 499 500 ad9523_io_update(indio_dev); 501 tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; 502 503 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); 504 if (ret < 0) 505 return ret; 506 507 return ad9523_io_update(indio_dev); 508 } 509 510 static ssize_t ad9523_store(struct device *dev, 511 struct device_attribute *attr, 512 const char *buf, size_t len) 513 { 514 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 515 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 516 struct ad9523_state *st = iio_priv(indio_dev); 517 bool state; 518 int ret; 519 520 ret = strtobool(buf, &state); 521 if (ret < 0) 522 return ret; 523 524 if (!state) 525 return len; 526 527 mutex_lock(&st->lock); 528 switch ((u32)this_attr->address) { 529 case AD9523_SYNC: 530 ret = ad9523_sync(indio_dev); 531 break; 532 case AD9523_EEPROM: 533 ret = ad9523_store_eeprom(indio_dev); 534 break; 535 default: 536 ret = -ENODEV; 537 } 538 mutex_unlock(&st->lock); 539 540 return ret ? ret : len; 541 } 542 543 static ssize_t ad9523_show(struct device *dev, 544 struct device_attribute *attr, 545 char *buf) 546 { 547 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 548 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 549 struct ad9523_state *st = iio_priv(indio_dev); 550 int ret; 551 552 mutex_lock(&st->lock); 553 ret = ad9523_read(indio_dev, AD9523_READBACK_0); 554 if (ret >= 0) { 555 ret = sprintf(buf, "%d\n", !!(ret & (1 << 556 (u32)this_attr->address))); 557 } 558 mutex_unlock(&st->lock); 559 560 return ret; 561 } 562 563 static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO, 564 ad9523_show, 565 NULL, 566 AD9523_STAT_PLL1_LD); 567 568 static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO, 569 ad9523_show, 570 NULL, 571 AD9523_STAT_PLL2_LD); 572 573 static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO, 574 ad9523_show, 575 NULL, 576 AD9523_STAT_REFA); 577 578 static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO, 579 ad9523_show, 580 NULL, 581 AD9523_STAT_REFB); 582 583 static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO, 584 ad9523_show, 585 NULL, 586 AD9523_STAT_REF_TEST); 587 588 static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO, 589 ad9523_show, 590 NULL, 591 AD9523_STAT_VCXO); 592 593 static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO, 594 ad9523_show, 595 NULL, 596 AD9523_STAT_PLL2_FB_CLK); 597 598 static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO, 599 ad9523_show, 600 NULL, 601 AD9523_STAT_PLL2_REF_CLK); 602 603 static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR, 604 NULL, 605 ad9523_store, 606 AD9523_SYNC); 607 608 static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR, 609 NULL, 610 ad9523_store, 611 AD9523_EEPROM); 612 613 static struct attribute *ad9523_attributes[] = { 614 &iio_dev_attr_sync_dividers.dev_attr.attr, 615 &iio_dev_attr_store_eeprom.dev_attr.attr, 616 &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr, 617 &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr, 618 &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr, 619 &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr, 620 &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr, 621 &iio_dev_attr_vcxo_clk_present.dev_attr.attr, 622 &iio_dev_attr_pll1_locked.dev_attr.attr, 623 &iio_dev_attr_pll2_locked.dev_attr.attr, 624 NULL, 625 }; 626 627 static const struct attribute_group ad9523_attribute_group = { 628 .attrs = ad9523_attributes, 629 }; 630 631 static int ad9523_read_raw(struct iio_dev *indio_dev, 632 struct iio_chan_spec const *chan, 633 int *val, 634 int *val2, 635 long m) 636 { 637 struct ad9523_state *st = iio_priv(indio_dev); 638 unsigned int code; 639 int ret; 640 641 mutex_lock(&st->lock); 642 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); 643 mutex_unlock(&st->lock); 644 645 if (ret < 0) 646 return ret; 647 648 switch (m) { 649 case IIO_CHAN_INFO_RAW: 650 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN); 651 return IIO_VAL_INT; 652 case IIO_CHAN_INFO_FREQUENCY: 653 *val = st->vco_out_freq[st->vco_out_map[chan->channel]] / 654 AD9523_CLK_DIST_DIV_REV(ret); 655 return IIO_VAL_INT; 656 case IIO_CHAN_INFO_PHASE: 657 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) / 658 AD9523_CLK_DIST_DIV_REV(ret); 659 *val = code / 1000000; 660 *val2 = code % 1000000; 661 return IIO_VAL_INT_PLUS_MICRO; 662 default: 663 return -EINVAL; 664 } 665 }; 666 667 static int ad9523_write_raw(struct iio_dev *indio_dev, 668 struct iio_chan_spec const *chan, 669 int val, 670 int val2, 671 long mask) 672 { 673 struct ad9523_state *st = iio_priv(indio_dev); 674 unsigned int reg; 675 int ret, tmp, code; 676 677 mutex_lock(&st->lock); 678 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); 679 if (ret < 0) 680 goto out; 681 682 reg = ret; 683 684 switch (mask) { 685 case IIO_CHAN_INFO_RAW: 686 if (val) 687 reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN; 688 else 689 reg |= AD9523_CLK_DIST_PWR_DOWN_EN; 690 break; 691 case IIO_CHAN_INFO_FREQUENCY: 692 if (val <= 0) { 693 ret = -EINVAL; 694 goto out; 695 } 696 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val); 697 if (ret < 0) 698 goto out; 699 tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val; 700 tmp = clamp(tmp, 1, 1024); 701 reg &= ~(0x3FF << 8); 702 reg |= AD9523_CLK_DIST_DIV(tmp); 703 break; 704 case IIO_CHAN_INFO_PHASE: 705 code = val * 1000000 + val2 % 1000000; 706 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592; 707 tmp = clamp(tmp, 0, 63); 708 reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0); 709 reg |= AD9523_CLK_DIST_DIV_PHASE(tmp); 710 break; 711 default: 712 ret = -EINVAL; 713 goto out; 714 } 715 716 ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel), 717 reg); 718 if (ret < 0) 719 goto out; 720 721 ad9523_io_update(indio_dev); 722 out: 723 mutex_unlock(&st->lock); 724 return ret; 725 } 726 727 static int ad9523_reg_access(struct iio_dev *indio_dev, 728 unsigned int reg, unsigned int writeval, 729 unsigned int *readval) 730 { 731 struct ad9523_state *st = iio_priv(indio_dev); 732 int ret; 733 734 mutex_lock(&st->lock); 735 if (readval == NULL) { 736 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval); 737 ad9523_io_update(indio_dev); 738 } else { 739 ret = ad9523_read(indio_dev, reg | AD9523_R1B); 740 if (ret < 0) 741 goto out_unlock; 742 *readval = ret; 743 ret = 0; 744 } 745 746 out_unlock: 747 mutex_unlock(&st->lock); 748 749 return ret; 750 } 751 752 static const struct iio_info ad9523_info = { 753 .read_raw = &ad9523_read_raw, 754 .write_raw = &ad9523_write_raw, 755 .debugfs_reg_access = &ad9523_reg_access, 756 .attrs = &ad9523_attribute_group, 757 }; 758 759 static int ad9523_setup(struct iio_dev *indio_dev) 760 { 761 struct ad9523_state *st = iio_priv(indio_dev); 762 struct ad9523_platform_data *pdata = st->pdata; 763 struct ad9523_channel_spec *chan; 764 unsigned long active_mask = 0; 765 int ret, i; 766 767 ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG, 768 AD9523_SER_CONF_SOFT_RESET | 769 (st->spi->mode & SPI_3WIRE ? 0 : 770 AD9523_SER_CONF_SDO_ACTIVE)); 771 if (ret < 0) 772 return ret; 773 774 ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL, 775 AD9523_READBACK_CTRL_READ_BUFFERED); 776 if (ret < 0) 777 return ret; 778 779 ret = ad9523_io_update(indio_dev); 780 if (ret < 0) 781 return ret; 782 783 /* 784 * PLL1 Setup 785 */ 786 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER, 787 pdata->refa_r_div); 788 if (ret < 0) 789 return ret; 790 791 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER, 792 pdata->refb_r_div); 793 if (ret < 0) 794 return ret; 795 796 ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER, 797 pdata->pll1_feedback_div); 798 if (ret < 0) 799 return ret; 800 801 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL, 802 AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata-> 803 pll1_charge_pump_current_nA) | 804 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL | 805 AD9523_PLL1_BACKLASH_PW_MIN); 806 if (ret < 0) 807 return ret; 808 809 ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL, 810 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) | 811 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) | 812 AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) | 813 AD_IF(osc_in_cmos_neg_inp_en, 814 AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) | 815 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) | 816 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN)); 817 if (ret < 0) 818 return ret; 819 820 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL, 821 AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) | 822 AD_IF(zd_in_cmos_neg_inp_en, 823 AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) | 824 AD_IF(zero_delay_mode_internal_en, 825 AD9523_PLL1_ZERO_DELAY_MODE_INT) | 826 AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) | 827 AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) | 828 AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN)); 829 if (ret < 0) 830 return ret; 831 832 ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL, 833 AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN | 834 AD9523_PLL1_REF_MODE(pdata->ref_mode)); 835 if (ret < 0) 836 return ret; 837 838 ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL, 839 AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero)); 840 if (ret < 0) 841 return ret; 842 /* 843 * PLL2 Setup 844 */ 845 846 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP, 847 AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata-> 848 pll2_charge_pump_current_nA)); 849 if (ret < 0) 850 return ret; 851 852 ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB, 853 AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) | 854 AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt)); 855 if (ret < 0) 856 return ret; 857 858 ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL, 859 AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL | 860 AD9523_PLL2_BACKLASH_CTRL_EN | 861 AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN)); 862 if (ret < 0) 863 return ret; 864 865 st->vco_freq = (pdata->vcxo_freq * (pdata->pll2_freq_doubler_en ? 2 : 1) 866 / pdata->pll2_r2_div) * AD9523_PLL2_FB_NDIV(pdata-> 867 pll2_ndiv_a_cnt, pdata->pll2_ndiv_b_cnt); 868 869 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL, 870 AD9523_PLL2_VCO_CALIBRATE); 871 if (ret < 0) 872 return ret; 873 874 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER, 875 AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) | 876 AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) | 877 AD_IFE(pll2_vco_diff_m1, 0, 878 AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) | 879 AD_IFE(pll2_vco_diff_m2, 0, 880 AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN)); 881 if (ret < 0) 882 return ret; 883 884 if (pdata->pll2_vco_diff_m1) 885 st->vco_out_freq[AD9523_VCO1] = 886 st->vco_freq / pdata->pll2_vco_diff_m1; 887 888 if (pdata->pll2_vco_diff_m2) 889 st->vco_out_freq[AD9523_VCO2] = 890 st->vco_freq / pdata->pll2_vco_diff_m2; 891 892 st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq; 893 894 ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER, 895 AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div)); 896 if (ret < 0) 897 return ret; 898 899 ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL, 900 AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) | 901 AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) | 902 AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) | 903 AD_IF(rzero_bypass_en, 904 AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN)); 905 if (ret < 0) 906 return ret; 907 908 for (i = 0; i < pdata->num_channels; i++) { 909 chan = &pdata->channels[i]; 910 if (chan->channel_num < AD9523_NUM_CHAN) { 911 __set_bit(chan->channel_num, &active_mask); 912 ret = ad9523_write(indio_dev, 913 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num), 914 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) | 915 AD9523_CLK_DIST_DIV(chan->channel_divider) | 916 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) | 917 (chan->sync_ignore_en ? 918 AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) | 919 (chan->divider_output_invert_en ? 920 AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) | 921 (chan->low_power_mode_en ? 922 AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) | 923 (chan->output_dis ? 924 AD9523_CLK_DIST_PWR_DOWN_EN : 0)); 925 if (ret < 0) 926 return ret; 927 928 ret = ad9523_vco_out_map(indio_dev, chan->channel_num, 929 chan->use_alt_clock_src); 930 if (ret < 0) 931 return ret; 932 933 st->ad9523_channels[i].type = IIO_ALTVOLTAGE; 934 st->ad9523_channels[i].output = 1; 935 st->ad9523_channels[i].indexed = 1; 936 st->ad9523_channels[i].channel = chan->channel_num; 937 st->ad9523_channels[i].extend_name = 938 chan->extended_name; 939 st->ad9523_channels[i].info_mask_separate = 940 BIT(IIO_CHAN_INFO_RAW) | 941 BIT(IIO_CHAN_INFO_PHASE) | 942 BIT(IIO_CHAN_INFO_FREQUENCY); 943 } 944 } 945 946 for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) 947 ad9523_write(indio_dev, 948 AD9523_CHANNEL_CLOCK_DIST(i), 949 AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) | 950 AD9523_CLK_DIST_PWR_DOWN_EN); 951 952 ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0); 953 if (ret < 0) 954 return ret; 955 956 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, 957 AD9523_STATUS_MONITOR_01_PLL12_LOCKED); 958 if (ret < 0) 959 return ret; 960 961 ret = ad9523_io_update(indio_dev); 962 if (ret < 0) 963 return ret; 964 965 return 0; 966 } 967 968 static int ad9523_probe(struct spi_device *spi) 969 { 970 struct ad9523_platform_data *pdata = spi->dev.platform_data; 971 struct iio_dev *indio_dev; 972 struct ad9523_state *st; 973 int ret; 974 975 if (!pdata) { 976 dev_err(&spi->dev, "no platform data?\n"); 977 return -EINVAL; 978 } 979 980 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 981 if (indio_dev == NULL) 982 return -ENOMEM; 983 984 st = iio_priv(indio_dev); 985 986 mutex_init(&st->lock); 987 988 st->reg = devm_regulator_get(&spi->dev, "vcc"); 989 if (!IS_ERR(st->reg)) { 990 ret = regulator_enable(st->reg); 991 if (ret) 992 return ret; 993 } 994 995 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 996 GPIOD_OUT_HIGH); 997 if (IS_ERR(st->pwrdown_gpio)) { 998 ret = PTR_ERR(st->pwrdown_gpio); 999 goto error_disable_reg; 1000 } 1001 1002 st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 1003 GPIOD_OUT_LOW); 1004 if (IS_ERR(st->reset_gpio)) { 1005 ret = PTR_ERR(st->reset_gpio); 1006 goto error_disable_reg; 1007 } 1008 1009 if (st->reset_gpio) { 1010 udelay(1); 1011 gpiod_direction_output(st->reset_gpio, 1); 1012 } 1013 1014 st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync", 1015 GPIOD_OUT_HIGH); 1016 if (IS_ERR(st->sync_gpio)) { 1017 ret = PTR_ERR(st->sync_gpio); 1018 goto error_disable_reg; 1019 } 1020 1021 spi_set_drvdata(spi, indio_dev); 1022 st->spi = spi; 1023 st->pdata = pdata; 1024 1025 indio_dev->dev.parent = &spi->dev; 1026 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 1027 spi_get_device_id(spi)->name; 1028 indio_dev->info = &ad9523_info; 1029 indio_dev->modes = INDIO_DIRECT_MODE; 1030 indio_dev->channels = st->ad9523_channels; 1031 indio_dev->num_channels = pdata->num_channels; 1032 1033 ret = ad9523_setup(indio_dev); 1034 if (ret < 0) 1035 goto error_disable_reg; 1036 1037 ret = iio_device_register(indio_dev); 1038 if (ret) 1039 goto error_disable_reg; 1040 1041 dev_info(&spi->dev, "probed %s\n", indio_dev->name); 1042 1043 return 0; 1044 1045 error_disable_reg: 1046 if (!IS_ERR(st->reg)) 1047 regulator_disable(st->reg); 1048 1049 return ret; 1050 } 1051 1052 static int ad9523_remove(struct spi_device *spi) 1053 { 1054 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1055 struct ad9523_state *st = iio_priv(indio_dev); 1056 1057 iio_device_unregister(indio_dev); 1058 1059 if (!IS_ERR(st->reg)) 1060 regulator_disable(st->reg); 1061 1062 return 0; 1063 } 1064 1065 static const struct spi_device_id ad9523_id[] = { 1066 {"ad9523-1", 9523}, 1067 {} 1068 }; 1069 MODULE_DEVICE_TABLE(spi, ad9523_id); 1070 1071 static struct spi_driver ad9523_driver = { 1072 .driver = { 1073 .name = "ad9523", 1074 }, 1075 .probe = ad9523_probe, 1076 .remove = ad9523_remove, 1077 .id_table = ad9523_id, 1078 }; 1079 module_spi_driver(ad9523_driver); 1080 1081 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1082 MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL"); 1083 MODULE_LICENSE("GPL v2"); 1084