1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 DAC driver 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Authors: Amelie Delaunay <amelie.delaunay@st.com> 7 * Fabrice Gasnier <fabrice.gasnier@st.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/delay.h> 12 #include <linux/iio/iio.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/string_helpers.h> 20 21 #include "stm32-dac-core.h" 22 23 #define STM32_DAC_CHANNEL_1 1 24 #define STM32_DAC_CHANNEL_2 2 25 #define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1) 26 27 #define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000 28 29 /** 30 * struct stm32_dac - private data of DAC driver 31 * @common: reference to DAC common data 32 * @lock: lock to protect against potential races when reading 33 * and update CR, to keep it in sync with pm_runtime 34 */ 35 struct stm32_dac { 36 struct stm32_dac_common *common; 37 struct mutex lock; 38 }; 39 40 static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel) 41 { 42 struct stm32_dac *dac = iio_priv(indio_dev); 43 u32 en, val; 44 int ret; 45 46 ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val); 47 if (ret < 0) 48 return ret; 49 if (STM32_DAC_IS_CHAN_1(channel)) 50 en = FIELD_GET(STM32_DAC_CR_EN1, val); 51 else 52 en = FIELD_GET(STM32_DAC_CR_EN2, val); 53 54 return !!en; 55 } 56 57 static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch, 58 bool enable) 59 { 60 struct stm32_dac *dac = iio_priv(indio_dev); 61 struct device *dev = indio_dev->dev.parent; 62 u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2; 63 u32 en = enable ? msk : 0; 64 int ret; 65 66 /* already enabled / disabled ? */ 67 mutex_lock(&dac->lock); 68 ret = stm32_dac_is_enabled(indio_dev, ch); 69 if (ret < 0 || enable == !!ret) { 70 mutex_unlock(&dac->lock); 71 return ret < 0 ? ret : 0; 72 } 73 74 if (enable) { 75 ret = pm_runtime_resume_and_get(dev); 76 if (ret < 0) { 77 mutex_unlock(&dac->lock); 78 return ret; 79 } 80 } 81 82 ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en); 83 mutex_unlock(&dac->lock); 84 if (ret < 0) { 85 dev_err(&indio_dev->dev, "%s failed\n", str_enable_disable(en)); 86 goto err_put_pm; 87 } 88 89 /* 90 * When HFSEL is set, it is not allowed to write the DHRx register 91 * during 8 clock cycles after the ENx bit is set. It is not allowed 92 * to make software/hardware trigger during this period either. 93 */ 94 if (en && dac->common->hfsel) 95 udelay(1); 96 97 if (!enable) { 98 pm_runtime_mark_last_busy(dev); 99 pm_runtime_put_autosuspend(dev); 100 } 101 102 return 0; 103 104 err_put_pm: 105 if (enable) { 106 pm_runtime_mark_last_busy(dev); 107 pm_runtime_put_autosuspend(dev); 108 } 109 110 return ret; 111 } 112 113 static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val) 114 { 115 int ret; 116 117 if (STM32_DAC_IS_CHAN_1(channel)) 118 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val); 119 else 120 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val); 121 122 return ret ? ret : IIO_VAL_INT; 123 } 124 125 static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val) 126 { 127 int ret; 128 129 if (STM32_DAC_IS_CHAN_1(channel)) 130 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val); 131 else 132 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val); 133 134 return ret; 135 } 136 137 static int stm32_dac_read_raw(struct iio_dev *indio_dev, 138 struct iio_chan_spec const *chan, 139 int *val, int *val2, long mask) 140 { 141 struct stm32_dac *dac = iio_priv(indio_dev); 142 143 switch (mask) { 144 case IIO_CHAN_INFO_RAW: 145 return stm32_dac_get_value(dac, chan->channel, val); 146 case IIO_CHAN_INFO_SCALE: 147 *val = dac->common->vref_mv; 148 *val2 = chan->scan_type.realbits; 149 return IIO_VAL_FRACTIONAL_LOG2; 150 default: 151 return -EINVAL; 152 } 153 } 154 155 static int stm32_dac_write_raw(struct iio_dev *indio_dev, 156 struct iio_chan_spec const *chan, 157 int val, int val2, long mask) 158 { 159 struct stm32_dac *dac = iio_priv(indio_dev); 160 161 switch (mask) { 162 case IIO_CHAN_INFO_RAW: 163 return stm32_dac_set_value(dac, chan->channel, val); 164 default: 165 return -EINVAL; 166 } 167 } 168 169 static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev, 170 unsigned reg, unsigned writeval, 171 unsigned *readval) 172 { 173 struct stm32_dac *dac = iio_priv(indio_dev); 174 175 if (!readval) 176 return regmap_write(dac->common->regmap, reg, writeval); 177 else 178 return regmap_read(dac->common->regmap, reg, readval); 179 } 180 181 static const struct iio_info stm32_dac_iio_info = { 182 .read_raw = stm32_dac_read_raw, 183 .write_raw = stm32_dac_write_raw, 184 .debugfs_reg_access = stm32_dac_debugfs_reg_access, 185 }; 186 187 static const char * const stm32_dac_powerdown_modes[] = { 188 "three_state", 189 }; 190 191 static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev, 192 const struct iio_chan_spec *chan) 193 { 194 return 0; 195 } 196 197 static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev, 198 const struct iio_chan_spec *chan, 199 unsigned int type) 200 { 201 return 0; 202 } 203 204 static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev, 205 uintptr_t private, 206 const struct iio_chan_spec *chan, 207 char *buf) 208 { 209 int ret = stm32_dac_is_enabled(indio_dev, chan->channel); 210 211 if (ret < 0) 212 return ret; 213 214 return sysfs_emit(buf, "%d\n", ret ? 0 : 1); 215 } 216 217 static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev, 218 uintptr_t private, 219 const struct iio_chan_spec *chan, 220 const char *buf, size_t len) 221 { 222 bool powerdown; 223 int ret; 224 225 ret = kstrtobool(buf, &powerdown); 226 if (ret) 227 return ret; 228 229 ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown); 230 if (ret) 231 return ret; 232 233 return len; 234 } 235 236 static const struct iio_enum stm32_dac_powerdown_mode_en = { 237 .items = stm32_dac_powerdown_modes, 238 .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes), 239 .get = stm32_dac_get_powerdown_mode, 240 .set = stm32_dac_set_powerdown_mode, 241 }; 242 243 static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = { 244 { 245 .name = "powerdown", 246 .read = stm32_dac_read_powerdown, 247 .write = stm32_dac_write_powerdown, 248 .shared = IIO_SEPARATE, 249 }, 250 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en), 251 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en), 252 {}, 253 }; 254 255 #define STM32_DAC_CHANNEL(chan, name) { \ 256 .type = IIO_VOLTAGE, \ 257 .indexed = 1, \ 258 .output = 1, \ 259 .channel = chan, \ 260 .info_mask_separate = \ 261 BIT(IIO_CHAN_INFO_RAW) | \ 262 BIT(IIO_CHAN_INFO_SCALE), \ 263 /* scan_index is always 0 as num_channels is 1 */ \ 264 .scan_type = { \ 265 .sign = 'u', \ 266 .realbits = 12, \ 267 .storagebits = 16, \ 268 }, \ 269 .datasheet_name = name, \ 270 .ext_info = stm32_dac_ext_info \ 271 } 272 273 static const struct iio_chan_spec stm32_dac_channels[] = { 274 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"), 275 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"), 276 }; 277 278 static int stm32_dac_chan_of_init(struct iio_dev *indio_dev) 279 { 280 struct device_node *np = indio_dev->dev.of_node; 281 unsigned int i; 282 u32 channel; 283 int ret; 284 285 ret = of_property_read_u32(np, "reg", &channel); 286 if (ret) { 287 dev_err(&indio_dev->dev, "Failed to read reg property\n"); 288 return ret; 289 } 290 291 for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) { 292 if (stm32_dac_channels[i].channel == channel) 293 break; 294 } 295 if (i >= ARRAY_SIZE(stm32_dac_channels)) { 296 dev_err(&indio_dev->dev, "Invalid reg property\n"); 297 return -EINVAL; 298 } 299 300 indio_dev->channels = &stm32_dac_channels[i]; 301 /* 302 * Expose only one channel here, as they can be used independently, 303 * with separate trigger. Then separate IIO devices are instantiated 304 * to manage this. 305 */ 306 indio_dev->num_channels = 1; 307 308 return 0; 309 }; 310 311 static int stm32_dac_probe(struct platform_device *pdev) 312 { 313 struct device_node *np = pdev->dev.of_node; 314 struct device *dev = &pdev->dev; 315 struct iio_dev *indio_dev; 316 struct stm32_dac *dac; 317 int ret; 318 319 if (!np) 320 return -ENODEV; 321 322 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac)); 323 if (!indio_dev) 324 return -ENOMEM; 325 platform_set_drvdata(pdev, indio_dev); 326 327 dac = iio_priv(indio_dev); 328 dac->common = dev_get_drvdata(pdev->dev.parent); 329 indio_dev->name = dev_name(&pdev->dev); 330 indio_dev->dev.of_node = pdev->dev.of_node; 331 indio_dev->info = &stm32_dac_iio_info; 332 indio_dev->modes = INDIO_DIRECT_MODE; 333 334 mutex_init(&dac->lock); 335 336 ret = stm32_dac_chan_of_init(indio_dev); 337 if (ret < 0) 338 return ret; 339 340 /* Get stm32-dac-core PM online */ 341 pm_runtime_get_noresume(dev); 342 pm_runtime_set_active(dev); 343 pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS); 344 pm_runtime_use_autosuspend(dev); 345 pm_runtime_enable(dev); 346 347 ret = iio_device_register(indio_dev); 348 if (ret) 349 goto err_pm_put; 350 351 pm_runtime_mark_last_busy(dev); 352 pm_runtime_put_autosuspend(dev); 353 354 return 0; 355 356 err_pm_put: 357 pm_runtime_disable(dev); 358 pm_runtime_set_suspended(dev); 359 pm_runtime_put_noidle(dev); 360 361 return ret; 362 } 363 364 static int stm32_dac_remove(struct platform_device *pdev) 365 { 366 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 367 368 pm_runtime_get_sync(&pdev->dev); 369 iio_device_unregister(indio_dev); 370 pm_runtime_disable(&pdev->dev); 371 pm_runtime_set_suspended(&pdev->dev); 372 pm_runtime_put_noidle(&pdev->dev); 373 374 return 0; 375 } 376 377 static int stm32_dac_suspend(struct device *dev) 378 { 379 struct iio_dev *indio_dev = dev_get_drvdata(dev); 380 int channel = indio_dev->channels[0].channel; 381 int ret; 382 383 /* Ensure DAC is disabled before suspend */ 384 ret = stm32_dac_is_enabled(indio_dev, channel); 385 if (ret) 386 return ret < 0 ? ret : -EBUSY; 387 388 return pm_runtime_force_suspend(dev); 389 } 390 391 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend, 392 pm_runtime_force_resume); 393 394 static const struct of_device_id stm32_dac_of_match[] = { 395 { .compatible = "st,stm32-dac", }, 396 {}, 397 }; 398 MODULE_DEVICE_TABLE(of, stm32_dac_of_match); 399 400 static struct platform_driver stm32_dac_driver = { 401 .probe = stm32_dac_probe, 402 .remove = stm32_dac_remove, 403 .driver = { 404 .name = "stm32-dac", 405 .of_match_table = stm32_dac_of_match, 406 .pm = pm_sleep_ptr(&stm32_dac_pm_ops), 407 }, 408 }; 409 module_platform_driver(stm32_dac_driver); 410 411 MODULE_ALIAS("platform:stm32-dac"); 412 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 413 MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver"); 414 MODULE_LICENSE("GPL v2"); 415