1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD5758 Digital to analog converters driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 * 7 * TODO: Currently CRC is not supported in this driver 8 */ 9 #include <linux/bsearch.h> 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/property.h> 14 #include <linux/spi/spi.h> 15 16 #include <linux/iio/iio.h> 17 #include <linux/iio/sysfs.h> 18 19 /* AD5758 registers definition */ 20 #define AD5758_NOP 0x00 21 #define AD5758_DAC_INPUT 0x01 22 #define AD5758_DAC_OUTPUT 0x02 23 #define AD5758_CLEAR_CODE 0x03 24 #define AD5758_USER_GAIN 0x04 25 #define AD5758_USER_OFFSET 0x05 26 #define AD5758_DAC_CONFIG 0x06 27 #define AD5758_SW_LDAC 0x07 28 #define AD5758_KEY 0x08 29 #define AD5758_GP_CONFIG1 0x09 30 #define AD5758_GP_CONFIG2 0x0A 31 #define AD5758_DCDC_CONFIG1 0x0B 32 #define AD5758_DCDC_CONFIG2 0x0C 33 #define AD5758_WDT_CONFIG 0x0F 34 #define AD5758_DIGITAL_DIAG_CONFIG 0x10 35 #define AD5758_ADC_CONFIG 0x11 36 #define AD5758_FAULT_PIN_CONFIG 0x12 37 #define AD5758_TWO_STAGE_READBACK_SELECT 0x13 38 #define AD5758_DIGITAL_DIAG_RESULTS 0x14 39 #define AD5758_ANALOG_DIAG_RESULTS 0x15 40 #define AD5758_STATUS 0x16 41 #define AD5758_CHIP_ID 0x17 42 #define AD5758_FREQ_MONITOR 0x18 43 #define AD5758_DEVICE_ID_0 0x19 44 #define AD5758_DEVICE_ID_1 0x1A 45 #define AD5758_DEVICE_ID_2 0x1B 46 #define AD5758_DEVICE_ID_3 0x1C 47 48 /* AD5758_DAC_CONFIG */ 49 #define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0) 50 #define AD5758_DAC_CONFIG_RANGE_MODE(x) (((x) & 0xF) << 0) 51 #define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5) 52 #define AD5758_DAC_CONFIG_INT_EN_MODE(x) (((x) & 0x1) << 5) 53 #define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6) 54 #define AD5758_DAC_CONFIG_OUT_EN_MODE(x) (((x) & 0x1) << 6) 55 #define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8) 56 #define AD5758_DAC_CONFIG_SR_EN_MODE(x) (((x) & 0x1) << 8) 57 #define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9) 58 #define AD5758_DAC_CONFIG_SR_CLOCK_MODE(x) (((x) & 0xF) << 9) 59 #define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13) 60 #define AD5758_DAC_CONFIG_SR_STEP_MODE(x) (((x) & 0x7) << 13) 61 62 /* AD5758_KEY */ 63 #define AD5758_KEY_CODE_RESET_1 0x15FA 64 #define AD5758_KEY_CODE_RESET_2 0xAF51 65 #define AD5758_KEY_CODE_SINGLE_ADC_CONV 0x1ADC 66 #define AD5758_KEY_CODE_RESET_WDT 0x0D06 67 #define AD5758_KEY_CODE_CALIB_MEM_REFRESH 0xFCBA 68 69 /* AD5758_DCDC_CONFIG1 */ 70 #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0) 71 #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE(x) (((x) & 0x1F) << 0) 72 #define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5) 73 #define AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(x) (((x) & 0x3) << 5) 74 #define AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK BIT(7) 75 #define AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(x) (((x) & 0x1) << 7) 76 77 /* AD5758_DCDC_CONFIG2 */ 78 #define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1) 79 #define AD5758_DCDC_CONFIG2_ILIMIT_MODE(x) (((x) & 0x7) << 1) 80 #define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11) 81 #define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12) 82 83 /* AD5758_DIGITAL_DIAG_RESULTS */ 84 #define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15) 85 86 #define AD5758_WR_FLAG_MSK(x) (0x80 | ((x) & 0x1F)) 87 88 #define AD5758_FULL_SCALE_MICRO 65535000000ULL 89 90 /** 91 * struct ad5758_state - driver instance specific data 92 * @spi: spi_device 93 * @lock: mutex lock 94 * @out_range: struct which stores the output range 95 * @dc_dc_mode: variable which stores the mode of operation 96 * @dc_dc_ilim: variable which stores the dc-to-dc converter current limit 97 * @slew_time: variable which stores the target slew time 98 * @pwr_down: variable which contains whether a channel is powered down or not 99 * @data: spi transfer buffers 100 */ 101 102 struct ad5758_range { 103 int reg; 104 int min; 105 int max; 106 }; 107 108 struct ad5758_state { 109 struct spi_device *spi; 110 struct mutex lock; 111 struct ad5758_range out_range; 112 unsigned int dc_dc_mode; 113 unsigned int dc_dc_ilim; 114 unsigned int slew_time; 115 bool pwr_down; 116 __be32 d32[3]; 117 }; 118 119 /** 120 * Output ranges corresponding to bits [3:0] from DAC_CONFIG register 121 * 0000: 0 V to 5 V voltage range 122 * 0001: 0 V to 10 V voltage range 123 * 0010: ±5 V voltage range 124 * 0011: ±10 V voltage range 125 * 1000: 0 mA to 20 mA current range 126 * 1001: 0 mA to 24 mA current range 127 * 1010: 4 mA to 20 mA current range 128 * 1011: ±20 mA current range 129 * 1100: ±24 mA current range 130 * 1101: -1 mA to +22 mA current range 131 */ 132 enum ad5758_output_range { 133 AD5758_RANGE_0V_5V, 134 AD5758_RANGE_0V_10V, 135 AD5758_RANGE_PLUSMINUS_5V, 136 AD5758_RANGE_PLUSMINUS_10V, 137 AD5758_RANGE_0mA_20mA = 8, 138 AD5758_RANGE_0mA_24mA, 139 AD5758_RANGE_4mA_24mA, 140 AD5758_RANGE_PLUSMINUS_20mA, 141 AD5758_RANGE_PLUSMINUS_24mA, 142 AD5758_RANGE_MINUS_1mA_PLUS_22mA, 143 }; 144 145 enum ad5758_dc_dc_mode { 146 AD5758_DCDC_MODE_POWER_OFF, 147 AD5758_DCDC_MODE_DPC_CURRENT, 148 AD5758_DCDC_MODE_DPC_VOLTAGE, 149 AD5758_DCDC_MODE_PPC_CURRENT, 150 }; 151 152 static const struct ad5758_range ad5758_voltage_range[] = { 153 { AD5758_RANGE_0V_5V, 0, 5000000 }, 154 { AD5758_RANGE_0V_10V, 0, 10000000 }, 155 { AD5758_RANGE_PLUSMINUS_5V, -5000000, 5000000 }, 156 { AD5758_RANGE_PLUSMINUS_10V, -10000000, 10000000 } 157 }; 158 159 static const struct ad5758_range ad5758_current_range[] = { 160 { AD5758_RANGE_0mA_20mA, 0, 20000}, 161 { AD5758_RANGE_0mA_24mA, 0, 24000 }, 162 { AD5758_RANGE_4mA_24mA, 4, 24000 }, 163 { AD5758_RANGE_PLUSMINUS_20mA, -20000, 20000 }, 164 { AD5758_RANGE_PLUSMINUS_24mA, -24000, 24000 }, 165 { AD5758_RANGE_MINUS_1mA_PLUS_22mA, -1000, 22000 }, 166 }; 167 168 static const int ad5758_sr_clk[16] = { 169 240000, 200000, 150000, 128000, 64000, 32000, 16000, 8000, 4000, 2000, 170 1000, 512, 256, 128, 64, 16 171 }; 172 173 static const int ad5758_sr_step[8] = { 174 4, 12, 64, 120, 256, 500, 1820, 2048 175 }; 176 177 static const int ad5758_dc_dc_ilim[6] = { 178 150000, 200000, 250000, 300000, 350000, 400000 179 }; 180 181 static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr) 182 { 183 struct spi_transfer t[] = { 184 { 185 .tx_buf = &st->d32[0], 186 .len = 4, 187 .cs_change = 1, 188 }, { 189 .tx_buf = &st->d32[1], 190 .rx_buf = &st->d32[2], 191 .len = 4, 192 }, 193 }; 194 int ret; 195 196 st->d32[0] = cpu_to_be32( 197 (AD5758_WR_FLAG_MSK(AD5758_TWO_STAGE_READBACK_SELECT) << 24) | 198 (addr << 8)); 199 st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24); 200 201 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 202 if (ret < 0) 203 return ret; 204 205 return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF; 206 } 207 208 static int ad5758_spi_reg_write(struct ad5758_state *st, 209 unsigned int addr, 210 unsigned int val) 211 { 212 st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) | 213 ((val & 0xFFFF) << 8)); 214 215 return spi_write(st->spi, &st->d32[0], sizeof(st->d32[0])); 216 } 217 218 static int ad5758_spi_write_mask(struct ad5758_state *st, 219 unsigned int addr, 220 unsigned long int mask, 221 unsigned int val) 222 { 223 int regval; 224 225 regval = ad5758_spi_reg_read(st, addr); 226 if (regval < 0) 227 return regval; 228 229 regval &= ~mask; 230 regval |= val; 231 232 return ad5758_spi_reg_write(st, addr, regval); 233 } 234 235 static int cmpfunc(const void *a, const void *b) 236 { 237 return *(int *)a - *(int *)b; 238 } 239 240 static int ad5758_find_closest_match(const int *array, 241 unsigned int size, int val) 242 { 243 int i; 244 245 for (i = 0; i < size; i++) { 246 if (val <= array[i]) 247 return i; 248 } 249 250 return size - 1; 251 } 252 253 static int ad5758_wait_for_task_complete(struct ad5758_state *st, 254 unsigned int reg, 255 unsigned int mask) 256 { 257 unsigned int timeout; 258 int ret; 259 260 timeout = 10; 261 do { 262 ret = ad5758_spi_reg_read(st, reg); 263 if (ret < 0) 264 return ret; 265 266 if (!(ret & mask)) 267 return 0; 268 269 usleep_range(100, 1000); 270 } while (--timeout); 271 272 dev_err(&st->spi->dev, 273 "Error reading bit 0x%x in 0x%x register\n", mask, reg); 274 275 return -EIO; 276 } 277 278 static int ad5758_calib_mem_refresh(struct ad5758_state *st) 279 { 280 int ret; 281 282 ret = ad5758_spi_reg_write(st, AD5758_KEY, 283 AD5758_KEY_CODE_CALIB_MEM_REFRESH); 284 if (ret < 0) { 285 dev_err(&st->spi->dev, 286 "Failed to initiate a calibration memory refresh\n"); 287 return ret; 288 } 289 290 /* Wait to allow time for the internal calibrations to complete */ 291 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 292 AD5758_CAL_MEM_UNREFRESHED_MSK); 293 } 294 295 static int ad5758_soft_reset(struct ad5758_state *st) 296 { 297 int ret; 298 299 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_1); 300 if (ret < 0) 301 return ret; 302 303 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_2); 304 305 /* Perform a software reset and wait at least 100us */ 306 usleep_range(100, 1000); 307 308 return ret; 309 } 310 311 static int ad5758_set_dc_dc_conv_mode(struct ad5758_state *st, 312 enum ad5758_dc_dc_mode mode) 313 { 314 int ret; 315 316 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 317 AD5758_DCDC_CONFIG1_DCDC_MODE_MSK, 318 AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(mode)); 319 if (ret < 0) 320 return ret; 321 322 /* 323 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 324 * This allows the 3-wire interface communication to complete. 325 */ 326 ret = ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 327 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 328 if (ret < 0) 329 return ret; 330 331 st->dc_dc_mode = mode; 332 333 return ret; 334 } 335 336 static int ad5758_set_dc_dc_ilim(struct ad5758_state *st, unsigned int ilim) 337 { 338 int ret; 339 340 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG2, 341 AD5758_DCDC_CONFIG2_ILIMIT_MSK, 342 AD5758_DCDC_CONFIG2_ILIMIT_MODE(ilim)); 343 if (ret < 0) 344 return ret; 345 /* 346 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 347 * This allows the 3-wire interface communication to complete. 348 */ 349 return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 350 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 351 } 352 353 static int ad5758_slew_rate_set(struct ad5758_state *st, 354 unsigned int sr_clk_idx, 355 unsigned int sr_step_idx) 356 { 357 unsigned int mode; 358 unsigned long int mask; 359 int ret; 360 361 mask = AD5758_DAC_CONFIG_SR_EN_MSK | 362 AD5758_DAC_CONFIG_SR_CLOCK_MSK | 363 AD5758_DAC_CONFIG_SR_STEP_MSK; 364 mode = AD5758_DAC_CONFIG_SR_EN_MODE(1) | 365 AD5758_DAC_CONFIG_SR_STEP_MODE(sr_step_idx) | 366 AD5758_DAC_CONFIG_SR_CLOCK_MODE(sr_clk_idx); 367 368 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode); 369 if (ret < 0) 370 return ret; 371 372 /* Wait to allow time for the internal calibrations to complete */ 373 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 374 AD5758_CAL_MEM_UNREFRESHED_MSK); 375 } 376 377 static int ad5758_slew_rate_config(struct ad5758_state *st) 378 { 379 unsigned int sr_clk_idx, sr_step_idx; 380 int i, res; 381 s64 diff_new, diff_old; 382 u64 sr_step, calc_slew_time; 383 384 sr_clk_idx = 0; 385 sr_step_idx = 0; 386 diff_old = S64_MAX; 387 /* 388 * The slew time can be determined by using the formula: 389 * Slew Time = (Full Scale Out / (Step Size x Update Clk Freq)) 390 * where Slew time is expressed in microseconds 391 * Given the desired slew time, the following algorithm determines the 392 * best match for the step size and the update clock frequency. 393 */ 394 for (i = 0; i < ARRAY_SIZE(ad5758_sr_clk); i++) { 395 /* 396 * Go through each valid update clock freq and determine a raw 397 * value for the step size by using the formula: 398 * Step Size = Full Scale Out / (Update Clk Freq * Slew Time) 399 */ 400 sr_step = AD5758_FULL_SCALE_MICRO; 401 do_div(sr_step, ad5758_sr_clk[i]); 402 do_div(sr_step, st->slew_time); 403 /* 404 * After a raw value for step size was determined, find the 405 * closest valid match 406 */ 407 res = ad5758_find_closest_match(ad5758_sr_step, 408 ARRAY_SIZE(ad5758_sr_step), 409 sr_step); 410 /* Calculate the slew time */ 411 calc_slew_time = AD5758_FULL_SCALE_MICRO; 412 do_div(calc_slew_time, ad5758_sr_step[res]); 413 do_div(calc_slew_time, ad5758_sr_clk[i]); 414 /* 415 * Determine with how many microseconds the calculated slew time 416 * is different from the desired slew time and store the diff 417 * for the next iteration 418 */ 419 diff_new = abs(st->slew_time - calc_slew_time); 420 if (diff_new < diff_old) { 421 diff_old = diff_new; 422 sr_clk_idx = i; 423 sr_step_idx = res; 424 } 425 } 426 427 return ad5758_slew_rate_set(st, sr_clk_idx, sr_step_idx); 428 } 429 430 static int ad5758_set_out_range(struct ad5758_state *st, int range) 431 { 432 int ret; 433 434 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 435 AD5758_DAC_CONFIG_RANGE_MSK, 436 AD5758_DAC_CONFIG_RANGE_MODE(range)); 437 if (ret < 0) 438 return ret; 439 440 /* Wait to allow time for the internal calibrations to complete */ 441 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 442 AD5758_CAL_MEM_UNREFRESHED_MSK); 443 } 444 445 static int ad5758_fault_prot_switch_en(struct ad5758_state *st, bool enable) 446 { 447 int ret; 448 449 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 450 AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK, 451 AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(enable)); 452 if (ret < 0) 453 return ret; 454 /* 455 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 456 * This allows the 3-wire interface communication to complete. 457 */ 458 return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 459 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 460 } 461 462 static int ad5758_internal_buffers_en(struct ad5758_state *st, bool enable) 463 { 464 int ret; 465 466 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 467 AD5758_DAC_CONFIG_INT_EN_MSK, 468 AD5758_DAC_CONFIG_INT_EN_MODE(enable)); 469 if (ret < 0) 470 return ret; 471 472 /* Wait to allow time for the internal calibrations to complete */ 473 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 474 AD5758_CAL_MEM_UNREFRESHED_MSK); 475 } 476 477 static int ad5758_reg_access(struct iio_dev *indio_dev, 478 unsigned int reg, 479 unsigned int writeval, 480 unsigned int *readval) 481 { 482 struct ad5758_state *st = iio_priv(indio_dev); 483 int ret; 484 485 mutex_lock(&st->lock); 486 if (readval) { 487 ret = ad5758_spi_reg_read(st, reg); 488 if (ret < 0) { 489 mutex_unlock(&st->lock); 490 return ret; 491 } 492 493 *readval = ret; 494 ret = 0; 495 } else { 496 ret = ad5758_spi_reg_write(st, reg, writeval); 497 } 498 mutex_unlock(&st->lock); 499 500 return ret; 501 } 502 503 static int ad5758_read_raw(struct iio_dev *indio_dev, 504 struct iio_chan_spec const *chan, 505 int *val, int *val2, long info) 506 { 507 struct ad5758_state *st = iio_priv(indio_dev); 508 int max, min, ret; 509 510 switch (info) { 511 case IIO_CHAN_INFO_RAW: 512 mutex_lock(&st->lock); 513 ret = ad5758_spi_reg_read(st, AD5758_DAC_INPUT); 514 mutex_unlock(&st->lock); 515 if (ret < 0) 516 return ret; 517 518 *val = ret; 519 return IIO_VAL_INT; 520 case IIO_CHAN_INFO_SCALE: 521 min = st->out_range.min; 522 max = st->out_range.max; 523 *val = (max - min) / 1000; 524 *val2 = 16; 525 return IIO_VAL_FRACTIONAL_LOG2; 526 case IIO_CHAN_INFO_OFFSET: 527 min = st->out_range.min; 528 max = st->out_range.max; 529 *val = ((min * (1 << 16)) / (max - min)) / 1000; 530 return IIO_VAL_INT; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 static int ad5758_write_raw(struct iio_dev *indio_dev, 537 struct iio_chan_spec const *chan, 538 int val, int val2, long info) 539 { 540 struct ad5758_state *st = iio_priv(indio_dev); 541 int ret; 542 543 switch (info) { 544 case IIO_CHAN_INFO_RAW: 545 mutex_lock(&st->lock); 546 ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val); 547 mutex_unlock(&st->lock); 548 return ret; 549 default: 550 return -EINVAL; 551 } 552 } 553 554 static ssize_t ad5758_read_powerdown(struct iio_dev *indio_dev, 555 uintptr_t priv, 556 const struct iio_chan_spec *chan, 557 char *buf) 558 { 559 struct ad5758_state *st = iio_priv(indio_dev); 560 561 return sprintf(buf, "%d\n", st->pwr_down); 562 } 563 564 static ssize_t ad5758_write_powerdown(struct iio_dev *indio_dev, 565 uintptr_t priv, 566 struct iio_chan_spec const *chan, 567 const char *buf, size_t len) 568 { 569 struct ad5758_state *st = iio_priv(indio_dev); 570 bool pwr_down; 571 unsigned int dcdc_config1_mode, dc_dc_mode, dac_config_mode, val; 572 unsigned long int dcdc_config1_msk, dac_config_msk; 573 int ret; 574 575 ret = kstrtobool(buf, &pwr_down); 576 if (ret) 577 return ret; 578 579 mutex_lock(&st->lock); 580 if (pwr_down) { 581 dc_dc_mode = AD5758_DCDC_MODE_POWER_OFF; 582 val = 0; 583 } else { 584 dc_dc_mode = st->dc_dc_mode; 585 val = 1; 586 } 587 588 dcdc_config1_mode = AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(dc_dc_mode) | 589 AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(val); 590 dcdc_config1_msk = AD5758_DCDC_CONFIG1_DCDC_MODE_MSK | 591 AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK; 592 593 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 594 dcdc_config1_msk, 595 dcdc_config1_mode); 596 if (ret < 0) 597 goto err_unlock; 598 599 dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) | 600 AD5758_DAC_CONFIG_INT_EN_MODE(val); 601 dac_config_msk = AD5758_DAC_CONFIG_OUT_EN_MSK | 602 AD5758_DAC_CONFIG_INT_EN_MSK; 603 604 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 605 dac_config_msk, 606 dac_config_mode); 607 if (ret < 0) 608 goto err_unlock; 609 610 st->pwr_down = pwr_down; 611 612 err_unlock: 613 mutex_unlock(&st->lock); 614 615 return ret ? ret : len; 616 } 617 618 static const struct iio_info ad5758_info = { 619 .read_raw = ad5758_read_raw, 620 .write_raw = ad5758_write_raw, 621 .debugfs_reg_access = &ad5758_reg_access, 622 }; 623 624 static const struct iio_chan_spec_ext_info ad5758_ext_info[] = { 625 { 626 .name = "powerdown", 627 .read = ad5758_read_powerdown, 628 .write = ad5758_write_powerdown, 629 .shared = IIO_SHARED_BY_TYPE, 630 }, 631 { } 632 }; 633 634 #define AD5758_DAC_CHAN(_chan_type) { \ 635 .type = (_chan_type), \ 636 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ 637 BIT(IIO_CHAN_INFO_SCALE) | \ 638 BIT(IIO_CHAN_INFO_OFFSET), \ 639 .indexed = 1, \ 640 .output = 1, \ 641 .ext_info = ad5758_ext_info, \ 642 } 643 644 static const struct iio_chan_spec ad5758_voltage_ch[] = { 645 AD5758_DAC_CHAN(IIO_VOLTAGE) 646 }; 647 648 static const struct iio_chan_spec ad5758_current_ch[] = { 649 AD5758_DAC_CHAN(IIO_CURRENT) 650 }; 651 652 static bool ad5758_is_valid_mode(enum ad5758_dc_dc_mode mode) 653 { 654 switch (mode) { 655 case AD5758_DCDC_MODE_DPC_CURRENT: 656 case AD5758_DCDC_MODE_DPC_VOLTAGE: 657 case AD5758_DCDC_MODE_PPC_CURRENT: 658 return true; 659 default: 660 return false; 661 } 662 } 663 664 static int ad5758_crc_disable(struct ad5758_state *st) 665 { 666 unsigned int mask; 667 668 mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A; 669 st->d32[0] = cpu_to_be32(mask); 670 671 return spi_write(st->spi, &st->d32[0], 4); 672 } 673 674 static int ad5758_find_out_range(struct ad5758_state *st, 675 const struct ad5758_range *range, 676 unsigned int size, 677 int min, int max) 678 { 679 int i; 680 681 for (i = 0; i < size; i++) { 682 if ((min == range[i].min) && (max == range[i].max)) { 683 st->out_range.reg = range[i].reg; 684 st->out_range.min = range[i].min; 685 st->out_range.max = range[i].max; 686 687 return 0; 688 } 689 } 690 691 return -EINVAL; 692 } 693 694 static int ad5758_parse_dt(struct ad5758_state *st) 695 { 696 unsigned int tmp, tmparray[2], size; 697 const struct ad5758_range *range; 698 int *index, ret; 699 700 st->dc_dc_ilim = 0; 701 ret = device_property_read_u32(&st->spi->dev, 702 "adi,dc-dc-ilim-microamp", &tmp); 703 if (ret) { 704 dev_dbg(&st->spi->dev, 705 "Missing \"dc-dc-ilim-microamp\" property\n"); 706 } else { 707 index = bsearch(&tmp, ad5758_dc_dc_ilim, 708 ARRAY_SIZE(ad5758_dc_dc_ilim), 709 sizeof(int), cmpfunc); 710 if (!index) 711 dev_dbg(&st->spi->dev, "dc-dc-ilim out of range\n"); 712 else 713 st->dc_dc_ilim = index - ad5758_dc_dc_ilim; 714 } 715 716 ret = device_property_read_u32(&st->spi->dev, "adi,dc-dc-mode", 717 &st->dc_dc_mode); 718 if (ret) { 719 dev_err(&st->spi->dev, "Missing \"dc-dc-mode\" property\n"); 720 return ret; 721 } 722 723 if (!ad5758_is_valid_mode(st->dc_dc_mode)) 724 return -EINVAL; 725 726 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) { 727 ret = device_property_read_u32_array(&st->spi->dev, 728 "adi,range-microvolt", 729 tmparray, 2); 730 if (ret) { 731 dev_err(&st->spi->dev, 732 "Missing \"range-microvolt\" property\n"); 733 return ret; 734 } 735 range = ad5758_voltage_range; 736 size = ARRAY_SIZE(ad5758_voltage_range); 737 } else { 738 ret = device_property_read_u32_array(&st->spi->dev, 739 "adi,range-microamp", 740 tmparray, 2); 741 if (ret) { 742 dev_err(&st->spi->dev, 743 "Missing \"range-microamp\" property\n"); 744 return ret; 745 } 746 range = ad5758_current_range; 747 size = ARRAY_SIZE(ad5758_current_range); 748 } 749 750 ret = ad5758_find_out_range(st, range, size, tmparray[0], tmparray[1]); 751 if (ret) { 752 dev_err(&st->spi->dev, "range invalid\n"); 753 return ret; 754 } 755 756 ret = device_property_read_u32(&st->spi->dev, "adi,slew-time-us", &tmp); 757 if (ret) { 758 dev_dbg(&st->spi->dev, "Missing \"slew-time-us\" property\n"); 759 st->slew_time = 0; 760 } else { 761 st->slew_time = tmp; 762 } 763 764 return 0; 765 } 766 767 static int ad5758_init(struct ad5758_state *st) 768 { 769 int regval, ret; 770 771 /* Disable CRC checks */ 772 ret = ad5758_crc_disable(st); 773 if (ret < 0) 774 return ret; 775 776 /* Perform a software reset */ 777 ret = ad5758_soft_reset(st); 778 if (ret < 0) 779 return ret; 780 781 /* Disable CRC checks */ 782 ret = ad5758_crc_disable(st); 783 if (ret < 0) 784 return ret; 785 786 /* Perform a calibration memory refresh */ 787 ret = ad5758_calib_mem_refresh(st); 788 if (ret < 0) 789 return ret; 790 791 regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS); 792 if (regval < 0) 793 return regval; 794 795 /* Clear all the error flags */ 796 ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval); 797 if (ret < 0) 798 return ret; 799 800 /* Set the dc-to-dc current limit */ 801 ret = ad5758_set_dc_dc_ilim(st, st->dc_dc_ilim); 802 if (ret < 0) 803 return ret; 804 805 /* Configure the dc-to-dc controller mode */ 806 ret = ad5758_set_dc_dc_conv_mode(st, st->dc_dc_mode); 807 if (ret < 0) 808 return ret; 809 810 /* Configure the output range */ 811 ret = ad5758_set_out_range(st, st->out_range.reg); 812 if (ret < 0) 813 return ret; 814 815 /* Enable Slew Rate Control, set the slew rate clock and step */ 816 if (st->slew_time) { 817 ret = ad5758_slew_rate_config(st); 818 if (ret < 0) 819 return ret; 820 } 821 822 /* Enable the VIOUT fault protection switch (FPS is closed) */ 823 ret = ad5758_fault_prot_switch_en(st, 1); 824 if (ret < 0) 825 return ret; 826 827 /* Power up the DAC and internal (INT) amplifiers */ 828 ret = ad5758_internal_buffers_en(st, 1); 829 if (ret < 0) 830 return ret; 831 832 /* Enable VIOUT */ 833 return ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 834 AD5758_DAC_CONFIG_OUT_EN_MSK, 835 AD5758_DAC_CONFIG_OUT_EN_MODE(1)); 836 } 837 838 static int ad5758_probe(struct spi_device *spi) 839 { 840 struct ad5758_state *st; 841 struct iio_dev *indio_dev; 842 int ret; 843 844 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 845 if (!indio_dev) 846 return -ENOMEM; 847 848 st = iio_priv(indio_dev); 849 spi_set_drvdata(spi, indio_dev); 850 851 st->spi = spi; 852 853 mutex_init(&st->lock); 854 855 indio_dev->dev.parent = &spi->dev; 856 indio_dev->name = spi_get_device_id(spi)->name; 857 indio_dev->info = &ad5758_info; 858 indio_dev->modes = INDIO_DIRECT_MODE; 859 indio_dev->num_channels = 1; 860 861 ret = ad5758_parse_dt(st); 862 if (ret < 0) 863 return ret; 864 865 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) 866 indio_dev->channels = ad5758_voltage_ch; 867 else 868 indio_dev->channels = ad5758_current_ch; 869 870 ret = ad5758_init(st); 871 if (ret < 0) { 872 dev_err(&spi->dev, "AD5758 init failed\n"); 873 return ret; 874 } 875 876 return devm_iio_device_register(&st->spi->dev, indio_dev); 877 } 878 879 static const struct spi_device_id ad5758_id[] = { 880 { "ad5758", 0 }, 881 {} 882 }; 883 MODULE_DEVICE_TABLE(spi, ad5758_id); 884 885 static struct spi_driver ad5758_driver = { 886 .driver = { 887 .name = KBUILD_MODNAME, 888 }, 889 .probe = ad5758_probe, 890 .id_table = ad5758_id, 891 }; 892 893 module_spi_driver(ad5758_driver); 894 895 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 896 MODULE_DESCRIPTION("Analog Devices AD5758 DAC"); 897 MODULE_LICENSE("GPL v2"); 898