1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD5758 Digital to analog converters driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 * 7 * TODO: Currently CRC is not supported in this driver 8 */ 9 #include <linux/bsearch.h> 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/property.h> 14 #include <linux/spi/spi.h> 15 #include <linux/gpio/consumer.h> 16 17 #include <linux/iio/iio.h> 18 #include <linux/iio/sysfs.h> 19 20 /* AD5758 registers definition */ 21 #define AD5758_NOP 0x00 22 #define AD5758_DAC_INPUT 0x01 23 #define AD5758_DAC_OUTPUT 0x02 24 #define AD5758_CLEAR_CODE 0x03 25 #define AD5758_USER_GAIN 0x04 26 #define AD5758_USER_OFFSET 0x05 27 #define AD5758_DAC_CONFIG 0x06 28 #define AD5758_SW_LDAC 0x07 29 #define AD5758_KEY 0x08 30 #define AD5758_GP_CONFIG1 0x09 31 #define AD5758_GP_CONFIG2 0x0A 32 #define AD5758_DCDC_CONFIG1 0x0B 33 #define AD5758_DCDC_CONFIG2 0x0C 34 #define AD5758_WDT_CONFIG 0x0F 35 #define AD5758_DIGITAL_DIAG_CONFIG 0x10 36 #define AD5758_ADC_CONFIG 0x11 37 #define AD5758_FAULT_PIN_CONFIG 0x12 38 #define AD5758_TWO_STAGE_READBACK_SELECT 0x13 39 #define AD5758_DIGITAL_DIAG_RESULTS 0x14 40 #define AD5758_ANALOG_DIAG_RESULTS 0x15 41 #define AD5758_STATUS 0x16 42 #define AD5758_CHIP_ID 0x17 43 #define AD5758_FREQ_MONITOR 0x18 44 #define AD5758_DEVICE_ID_0 0x19 45 #define AD5758_DEVICE_ID_1 0x1A 46 #define AD5758_DEVICE_ID_2 0x1B 47 #define AD5758_DEVICE_ID_3 0x1C 48 49 /* AD5758_DAC_CONFIG */ 50 #define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0) 51 #define AD5758_DAC_CONFIG_RANGE_MODE(x) (((x) & 0xF) << 0) 52 #define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5) 53 #define AD5758_DAC_CONFIG_INT_EN_MODE(x) (((x) & 0x1) << 5) 54 #define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6) 55 #define AD5758_DAC_CONFIG_OUT_EN_MODE(x) (((x) & 0x1) << 6) 56 #define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8) 57 #define AD5758_DAC_CONFIG_SR_EN_MODE(x) (((x) & 0x1) << 8) 58 #define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9) 59 #define AD5758_DAC_CONFIG_SR_CLOCK_MODE(x) (((x) & 0xF) << 9) 60 #define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13) 61 #define AD5758_DAC_CONFIG_SR_STEP_MODE(x) (((x) & 0x7) << 13) 62 63 /* AD5758_KEY */ 64 #define AD5758_KEY_CODE_RESET_1 0x15FA 65 #define AD5758_KEY_CODE_RESET_2 0xAF51 66 #define AD5758_KEY_CODE_SINGLE_ADC_CONV 0x1ADC 67 #define AD5758_KEY_CODE_RESET_WDT 0x0D06 68 #define AD5758_KEY_CODE_CALIB_MEM_REFRESH 0xFCBA 69 70 /* AD5758_DCDC_CONFIG1 */ 71 #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0) 72 #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE(x) (((x) & 0x1F) << 0) 73 #define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5) 74 #define AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(x) (((x) & 0x3) << 5) 75 #define AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK BIT(7) 76 #define AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(x) (((x) & 0x1) << 7) 77 78 /* AD5758_DCDC_CONFIG2 */ 79 #define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1) 80 #define AD5758_DCDC_CONFIG2_ILIMIT_MODE(x) (((x) & 0x7) << 1) 81 #define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11) 82 #define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12) 83 84 /* AD5758_DIGITAL_DIAG_RESULTS */ 85 #define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15) 86 87 #define AD5758_WR_FLAG_MSK(x) (0x80 | ((x) & 0x1F)) 88 89 #define AD5758_FULL_SCALE_MICRO 65535000000ULL 90 91 /** 92 * struct ad5758_state - driver instance specific data 93 * @spi: spi_device 94 * @lock: mutex lock 95 * @out_range: struct which stores the output range 96 * @dc_dc_mode: variable which stores the mode of operation 97 * @dc_dc_ilim: variable which stores the dc-to-dc converter current limit 98 * @slew_time: variable which stores the target slew time 99 * @pwr_down: variable which contains whether a channel is powered down or not 100 * @data: spi transfer buffers 101 */ 102 103 struct ad5758_range { 104 int reg; 105 int min; 106 int max; 107 }; 108 109 struct ad5758_state { 110 struct spi_device *spi; 111 struct mutex lock; 112 struct gpio_desc *gpio_reset; 113 struct ad5758_range out_range; 114 unsigned int dc_dc_mode; 115 unsigned int dc_dc_ilim; 116 unsigned int slew_time; 117 bool pwr_down; 118 __be32 d32[3]; 119 }; 120 121 /** 122 * Output ranges corresponding to bits [3:0] from DAC_CONFIG register 123 * 0000: 0 V to 5 V voltage range 124 * 0001: 0 V to 10 V voltage range 125 * 0010: ±5 V voltage range 126 * 0011: ±10 V voltage range 127 * 1000: 0 mA to 20 mA current range 128 * 1001: 0 mA to 24 mA current range 129 * 1010: 4 mA to 20 mA current range 130 * 1011: ±20 mA current range 131 * 1100: ±24 mA current range 132 * 1101: -1 mA to +22 mA current range 133 */ 134 enum ad5758_output_range { 135 AD5758_RANGE_0V_5V, 136 AD5758_RANGE_0V_10V, 137 AD5758_RANGE_PLUSMINUS_5V, 138 AD5758_RANGE_PLUSMINUS_10V, 139 AD5758_RANGE_0mA_20mA = 8, 140 AD5758_RANGE_0mA_24mA, 141 AD5758_RANGE_4mA_24mA, 142 AD5758_RANGE_PLUSMINUS_20mA, 143 AD5758_RANGE_PLUSMINUS_24mA, 144 AD5758_RANGE_MINUS_1mA_PLUS_22mA, 145 }; 146 147 enum ad5758_dc_dc_mode { 148 AD5758_DCDC_MODE_POWER_OFF, 149 AD5758_DCDC_MODE_DPC_CURRENT, 150 AD5758_DCDC_MODE_DPC_VOLTAGE, 151 AD5758_DCDC_MODE_PPC_CURRENT, 152 }; 153 154 static const struct ad5758_range ad5758_voltage_range[] = { 155 { AD5758_RANGE_0V_5V, 0, 5000000 }, 156 { AD5758_RANGE_0V_10V, 0, 10000000 }, 157 { AD5758_RANGE_PLUSMINUS_5V, -5000000, 5000000 }, 158 { AD5758_RANGE_PLUSMINUS_10V, -10000000, 10000000 } 159 }; 160 161 static const struct ad5758_range ad5758_current_range[] = { 162 { AD5758_RANGE_0mA_20mA, 0, 20000}, 163 { AD5758_RANGE_0mA_24mA, 0, 24000 }, 164 { AD5758_RANGE_4mA_24mA, 4, 24000 }, 165 { AD5758_RANGE_PLUSMINUS_20mA, -20000, 20000 }, 166 { AD5758_RANGE_PLUSMINUS_24mA, -24000, 24000 }, 167 { AD5758_RANGE_MINUS_1mA_PLUS_22mA, -1000, 22000 }, 168 }; 169 170 static const int ad5758_sr_clk[16] = { 171 240000, 200000, 150000, 128000, 64000, 32000, 16000, 8000, 4000, 2000, 172 1000, 512, 256, 128, 64, 16 173 }; 174 175 static const int ad5758_sr_step[8] = { 176 4, 12, 64, 120, 256, 500, 1820, 2048 177 }; 178 179 static const int ad5758_dc_dc_ilim[6] = { 180 150000, 200000, 250000, 300000, 350000, 400000 181 }; 182 183 static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr) 184 { 185 struct spi_transfer t[] = { 186 { 187 .tx_buf = &st->d32[0], 188 .len = 4, 189 .cs_change = 1, 190 }, { 191 .tx_buf = &st->d32[1], 192 .rx_buf = &st->d32[2], 193 .len = 4, 194 }, 195 }; 196 int ret; 197 198 st->d32[0] = cpu_to_be32( 199 (AD5758_WR_FLAG_MSK(AD5758_TWO_STAGE_READBACK_SELECT) << 24) | 200 (addr << 8)); 201 st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24); 202 203 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 204 if (ret < 0) 205 return ret; 206 207 return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF; 208 } 209 210 static int ad5758_spi_reg_write(struct ad5758_state *st, 211 unsigned int addr, 212 unsigned int val) 213 { 214 st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) | 215 ((val & 0xFFFF) << 8)); 216 217 return spi_write(st->spi, &st->d32[0], sizeof(st->d32[0])); 218 } 219 220 static int ad5758_spi_write_mask(struct ad5758_state *st, 221 unsigned int addr, 222 unsigned long int mask, 223 unsigned int val) 224 { 225 int regval; 226 227 regval = ad5758_spi_reg_read(st, addr); 228 if (regval < 0) 229 return regval; 230 231 regval &= ~mask; 232 regval |= val; 233 234 return ad5758_spi_reg_write(st, addr, regval); 235 } 236 237 static int cmpfunc(const void *a, const void *b) 238 { 239 return *(int *)a - *(int *)b; 240 } 241 242 static int ad5758_find_closest_match(const int *array, 243 unsigned int size, int val) 244 { 245 int i; 246 247 for (i = 0; i < size; i++) { 248 if (val <= array[i]) 249 return i; 250 } 251 252 return size - 1; 253 } 254 255 static int ad5758_wait_for_task_complete(struct ad5758_state *st, 256 unsigned int reg, 257 unsigned int mask) 258 { 259 unsigned int timeout; 260 int ret; 261 262 timeout = 10; 263 do { 264 ret = ad5758_spi_reg_read(st, reg); 265 if (ret < 0) 266 return ret; 267 268 if (!(ret & mask)) 269 return 0; 270 271 usleep_range(100, 1000); 272 } while (--timeout); 273 274 dev_err(&st->spi->dev, 275 "Error reading bit 0x%x in 0x%x register\n", mask, reg); 276 277 return -EIO; 278 } 279 280 static int ad5758_calib_mem_refresh(struct ad5758_state *st) 281 { 282 int ret; 283 284 ret = ad5758_spi_reg_write(st, AD5758_KEY, 285 AD5758_KEY_CODE_CALIB_MEM_REFRESH); 286 if (ret < 0) { 287 dev_err(&st->spi->dev, 288 "Failed to initiate a calibration memory refresh\n"); 289 return ret; 290 } 291 292 /* Wait to allow time for the internal calibrations to complete */ 293 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 294 AD5758_CAL_MEM_UNREFRESHED_MSK); 295 } 296 297 static int ad5758_soft_reset(struct ad5758_state *st) 298 { 299 int ret; 300 301 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_1); 302 if (ret < 0) 303 return ret; 304 305 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_2); 306 307 /* Perform a software reset and wait at least 100us */ 308 usleep_range(100, 1000); 309 310 return ret; 311 } 312 313 static int ad5758_set_dc_dc_conv_mode(struct ad5758_state *st, 314 enum ad5758_dc_dc_mode mode) 315 { 316 int ret; 317 318 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 319 AD5758_DCDC_CONFIG1_DCDC_MODE_MSK, 320 AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(mode)); 321 if (ret < 0) 322 return ret; 323 324 /* 325 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 326 * This allows the 3-wire interface communication to complete. 327 */ 328 ret = ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 329 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 330 if (ret < 0) 331 return ret; 332 333 st->dc_dc_mode = mode; 334 335 return ret; 336 } 337 338 static int ad5758_set_dc_dc_ilim(struct ad5758_state *st, unsigned int ilim) 339 { 340 int ret; 341 342 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG2, 343 AD5758_DCDC_CONFIG2_ILIMIT_MSK, 344 AD5758_DCDC_CONFIG2_ILIMIT_MODE(ilim)); 345 if (ret < 0) 346 return ret; 347 /* 348 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 349 * This allows the 3-wire interface communication to complete. 350 */ 351 return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 352 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 353 } 354 355 static int ad5758_slew_rate_set(struct ad5758_state *st, 356 unsigned int sr_clk_idx, 357 unsigned int sr_step_idx) 358 { 359 unsigned int mode; 360 unsigned long int mask; 361 int ret; 362 363 mask = AD5758_DAC_CONFIG_SR_EN_MSK | 364 AD5758_DAC_CONFIG_SR_CLOCK_MSK | 365 AD5758_DAC_CONFIG_SR_STEP_MSK; 366 mode = AD5758_DAC_CONFIG_SR_EN_MODE(1) | 367 AD5758_DAC_CONFIG_SR_STEP_MODE(sr_step_idx) | 368 AD5758_DAC_CONFIG_SR_CLOCK_MODE(sr_clk_idx); 369 370 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode); 371 if (ret < 0) 372 return ret; 373 374 /* Wait to allow time for the internal calibrations to complete */ 375 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 376 AD5758_CAL_MEM_UNREFRESHED_MSK); 377 } 378 379 static int ad5758_slew_rate_config(struct ad5758_state *st) 380 { 381 unsigned int sr_clk_idx, sr_step_idx; 382 int i, res; 383 s64 diff_new, diff_old; 384 u64 sr_step, calc_slew_time; 385 386 sr_clk_idx = 0; 387 sr_step_idx = 0; 388 diff_old = S64_MAX; 389 /* 390 * The slew time can be determined by using the formula: 391 * Slew Time = (Full Scale Out / (Step Size x Update Clk Freq)) 392 * where Slew time is expressed in microseconds 393 * Given the desired slew time, the following algorithm determines the 394 * best match for the step size and the update clock frequency. 395 */ 396 for (i = 0; i < ARRAY_SIZE(ad5758_sr_clk); i++) { 397 /* 398 * Go through each valid update clock freq and determine a raw 399 * value for the step size by using the formula: 400 * Step Size = Full Scale Out / (Update Clk Freq * Slew Time) 401 */ 402 sr_step = AD5758_FULL_SCALE_MICRO; 403 do_div(sr_step, ad5758_sr_clk[i]); 404 do_div(sr_step, st->slew_time); 405 /* 406 * After a raw value for step size was determined, find the 407 * closest valid match 408 */ 409 res = ad5758_find_closest_match(ad5758_sr_step, 410 ARRAY_SIZE(ad5758_sr_step), 411 sr_step); 412 /* Calculate the slew time */ 413 calc_slew_time = AD5758_FULL_SCALE_MICRO; 414 do_div(calc_slew_time, ad5758_sr_step[res]); 415 do_div(calc_slew_time, ad5758_sr_clk[i]); 416 /* 417 * Determine with how many microseconds the calculated slew time 418 * is different from the desired slew time and store the diff 419 * for the next iteration 420 */ 421 diff_new = abs(st->slew_time - calc_slew_time); 422 if (diff_new < diff_old) { 423 diff_old = diff_new; 424 sr_clk_idx = i; 425 sr_step_idx = res; 426 } 427 } 428 429 return ad5758_slew_rate_set(st, sr_clk_idx, sr_step_idx); 430 } 431 432 static int ad5758_set_out_range(struct ad5758_state *st, int range) 433 { 434 int ret; 435 436 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 437 AD5758_DAC_CONFIG_RANGE_MSK, 438 AD5758_DAC_CONFIG_RANGE_MODE(range)); 439 if (ret < 0) 440 return ret; 441 442 /* Wait to allow time for the internal calibrations to complete */ 443 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 444 AD5758_CAL_MEM_UNREFRESHED_MSK); 445 } 446 447 static int ad5758_fault_prot_switch_en(struct ad5758_state *st, bool enable) 448 { 449 int ret; 450 451 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 452 AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK, 453 AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(enable)); 454 if (ret < 0) 455 return ret; 456 /* 457 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 458 * This allows the 3-wire interface communication to complete. 459 */ 460 return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2, 461 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK); 462 } 463 464 static int ad5758_internal_buffers_en(struct ad5758_state *st, bool enable) 465 { 466 int ret; 467 468 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 469 AD5758_DAC_CONFIG_INT_EN_MSK, 470 AD5758_DAC_CONFIG_INT_EN_MODE(enable)); 471 if (ret < 0) 472 return ret; 473 474 /* Wait to allow time for the internal calibrations to complete */ 475 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS, 476 AD5758_CAL_MEM_UNREFRESHED_MSK); 477 } 478 479 static int ad5758_reset(struct ad5758_state *st) 480 { 481 if (st->gpio_reset) { 482 gpiod_set_value(st->gpio_reset, 0); 483 usleep_range(100, 1000); 484 gpiod_set_value(st->gpio_reset, 1); 485 usleep_range(100, 1000); 486 487 return 0; 488 } else { 489 /* Perform a software reset */ 490 return ad5758_soft_reset(st); 491 } 492 } 493 494 static int ad5758_reg_access(struct iio_dev *indio_dev, 495 unsigned int reg, 496 unsigned int writeval, 497 unsigned int *readval) 498 { 499 struct ad5758_state *st = iio_priv(indio_dev); 500 int ret; 501 502 mutex_lock(&st->lock); 503 if (readval) { 504 ret = ad5758_spi_reg_read(st, reg); 505 if (ret < 0) { 506 mutex_unlock(&st->lock); 507 return ret; 508 } 509 510 *readval = ret; 511 ret = 0; 512 } else { 513 ret = ad5758_spi_reg_write(st, reg, writeval); 514 } 515 mutex_unlock(&st->lock); 516 517 return ret; 518 } 519 520 static int ad5758_read_raw(struct iio_dev *indio_dev, 521 struct iio_chan_spec const *chan, 522 int *val, int *val2, long info) 523 { 524 struct ad5758_state *st = iio_priv(indio_dev); 525 int max, min, ret; 526 527 switch (info) { 528 case IIO_CHAN_INFO_RAW: 529 mutex_lock(&st->lock); 530 ret = ad5758_spi_reg_read(st, AD5758_DAC_INPUT); 531 mutex_unlock(&st->lock); 532 if (ret < 0) 533 return ret; 534 535 *val = ret; 536 return IIO_VAL_INT; 537 case IIO_CHAN_INFO_SCALE: 538 min = st->out_range.min; 539 max = st->out_range.max; 540 *val = (max - min) / 1000; 541 *val2 = 16; 542 return IIO_VAL_FRACTIONAL_LOG2; 543 case IIO_CHAN_INFO_OFFSET: 544 min = st->out_range.min; 545 max = st->out_range.max; 546 *val = ((min * (1 << 16)) / (max - min)) / 1000; 547 return IIO_VAL_INT; 548 default: 549 return -EINVAL; 550 } 551 } 552 553 static int ad5758_write_raw(struct iio_dev *indio_dev, 554 struct iio_chan_spec const *chan, 555 int val, int val2, long info) 556 { 557 struct ad5758_state *st = iio_priv(indio_dev); 558 int ret; 559 560 switch (info) { 561 case IIO_CHAN_INFO_RAW: 562 mutex_lock(&st->lock); 563 ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val); 564 mutex_unlock(&st->lock); 565 return ret; 566 default: 567 return -EINVAL; 568 } 569 } 570 571 static ssize_t ad5758_read_powerdown(struct iio_dev *indio_dev, 572 uintptr_t priv, 573 const struct iio_chan_spec *chan, 574 char *buf) 575 { 576 struct ad5758_state *st = iio_priv(indio_dev); 577 578 return sprintf(buf, "%d\n", st->pwr_down); 579 } 580 581 static ssize_t ad5758_write_powerdown(struct iio_dev *indio_dev, 582 uintptr_t priv, 583 struct iio_chan_spec const *chan, 584 const char *buf, size_t len) 585 { 586 struct ad5758_state *st = iio_priv(indio_dev); 587 bool pwr_down; 588 unsigned int dcdc_config1_mode, dc_dc_mode, dac_config_mode, val; 589 unsigned long int dcdc_config1_msk, dac_config_msk; 590 int ret; 591 592 ret = kstrtobool(buf, &pwr_down); 593 if (ret) 594 return ret; 595 596 mutex_lock(&st->lock); 597 if (pwr_down) { 598 dc_dc_mode = AD5758_DCDC_MODE_POWER_OFF; 599 val = 0; 600 } else { 601 dc_dc_mode = st->dc_dc_mode; 602 val = 1; 603 } 604 605 dcdc_config1_mode = AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(dc_dc_mode) | 606 AD5758_DCDC_CONFIG1_PROT_SW_EN_MODE(val); 607 dcdc_config1_msk = AD5758_DCDC_CONFIG1_DCDC_MODE_MSK | 608 AD5758_DCDC_CONFIG1_PROT_SW_EN_MSK; 609 610 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1, 611 dcdc_config1_msk, 612 dcdc_config1_mode); 613 if (ret < 0) 614 goto err_unlock; 615 616 dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) | 617 AD5758_DAC_CONFIG_INT_EN_MODE(val); 618 dac_config_msk = AD5758_DAC_CONFIG_OUT_EN_MSK | 619 AD5758_DAC_CONFIG_INT_EN_MSK; 620 621 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 622 dac_config_msk, 623 dac_config_mode); 624 if (ret < 0) 625 goto err_unlock; 626 627 st->pwr_down = pwr_down; 628 629 err_unlock: 630 mutex_unlock(&st->lock); 631 632 return ret ? ret : len; 633 } 634 635 static const struct iio_info ad5758_info = { 636 .read_raw = ad5758_read_raw, 637 .write_raw = ad5758_write_raw, 638 .debugfs_reg_access = &ad5758_reg_access, 639 }; 640 641 static const struct iio_chan_spec_ext_info ad5758_ext_info[] = { 642 { 643 .name = "powerdown", 644 .read = ad5758_read_powerdown, 645 .write = ad5758_write_powerdown, 646 .shared = IIO_SHARED_BY_TYPE, 647 }, 648 { } 649 }; 650 651 #define AD5758_DAC_CHAN(_chan_type) { \ 652 .type = (_chan_type), \ 653 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ 654 BIT(IIO_CHAN_INFO_SCALE) | \ 655 BIT(IIO_CHAN_INFO_OFFSET), \ 656 .indexed = 1, \ 657 .output = 1, \ 658 .ext_info = ad5758_ext_info, \ 659 } 660 661 static const struct iio_chan_spec ad5758_voltage_ch[] = { 662 AD5758_DAC_CHAN(IIO_VOLTAGE) 663 }; 664 665 static const struct iio_chan_spec ad5758_current_ch[] = { 666 AD5758_DAC_CHAN(IIO_CURRENT) 667 }; 668 669 static bool ad5758_is_valid_mode(enum ad5758_dc_dc_mode mode) 670 { 671 switch (mode) { 672 case AD5758_DCDC_MODE_DPC_CURRENT: 673 case AD5758_DCDC_MODE_DPC_VOLTAGE: 674 case AD5758_DCDC_MODE_PPC_CURRENT: 675 return true; 676 default: 677 return false; 678 } 679 } 680 681 static int ad5758_crc_disable(struct ad5758_state *st) 682 { 683 unsigned int mask; 684 685 mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A; 686 st->d32[0] = cpu_to_be32(mask); 687 688 return spi_write(st->spi, &st->d32[0], 4); 689 } 690 691 static int ad5758_find_out_range(struct ad5758_state *st, 692 const struct ad5758_range *range, 693 unsigned int size, 694 int min, int max) 695 { 696 int i; 697 698 for (i = 0; i < size; i++) { 699 if ((min == range[i].min) && (max == range[i].max)) { 700 st->out_range.reg = range[i].reg; 701 st->out_range.min = range[i].min; 702 st->out_range.max = range[i].max; 703 704 return 0; 705 } 706 } 707 708 return -EINVAL; 709 } 710 711 static int ad5758_parse_dt(struct ad5758_state *st) 712 { 713 unsigned int tmp, tmparray[2], size; 714 const struct ad5758_range *range; 715 int *index, ret; 716 717 st->dc_dc_ilim = 0; 718 ret = device_property_read_u32(&st->spi->dev, 719 "adi,dc-dc-ilim-microamp", &tmp); 720 if (ret) { 721 dev_dbg(&st->spi->dev, 722 "Missing \"dc-dc-ilim-microamp\" property\n"); 723 } else { 724 index = bsearch(&tmp, ad5758_dc_dc_ilim, 725 ARRAY_SIZE(ad5758_dc_dc_ilim), 726 sizeof(int), cmpfunc); 727 if (!index) 728 dev_dbg(&st->spi->dev, "dc-dc-ilim out of range\n"); 729 else 730 st->dc_dc_ilim = index - ad5758_dc_dc_ilim; 731 } 732 733 ret = device_property_read_u32(&st->spi->dev, "adi,dc-dc-mode", 734 &st->dc_dc_mode); 735 if (ret) { 736 dev_err(&st->spi->dev, "Missing \"dc-dc-mode\" property\n"); 737 return ret; 738 } 739 740 if (!ad5758_is_valid_mode(st->dc_dc_mode)) 741 return -EINVAL; 742 743 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) { 744 ret = device_property_read_u32_array(&st->spi->dev, 745 "adi,range-microvolt", 746 tmparray, 2); 747 if (ret) { 748 dev_err(&st->spi->dev, 749 "Missing \"range-microvolt\" property\n"); 750 return ret; 751 } 752 range = ad5758_voltage_range; 753 size = ARRAY_SIZE(ad5758_voltage_range); 754 } else { 755 ret = device_property_read_u32_array(&st->spi->dev, 756 "adi,range-microamp", 757 tmparray, 2); 758 if (ret) { 759 dev_err(&st->spi->dev, 760 "Missing \"range-microamp\" property\n"); 761 return ret; 762 } 763 range = ad5758_current_range; 764 size = ARRAY_SIZE(ad5758_current_range); 765 } 766 767 ret = ad5758_find_out_range(st, range, size, tmparray[0], tmparray[1]); 768 if (ret) { 769 dev_err(&st->spi->dev, "range invalid\n"); 770 return ret; 771 } 772 773 ret = device_property_read_u32(&st->spi->dev, "adi,slew-time-us", &tmp); 774 if (ret) { 775 dev_dbg(&st->spi->dev, "Missing \"slew-time-us\" property\n"); 776 st->slew_time = 0; 777 } else { 778 st->slew_time = tmp; 779 } 780 781 return 0; 782 } 783 784 static int ad5758_init(struct ad5758_state *st) 785 { 786 int regval, ret; 787 788 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 789 GPIOD_OUT_HIGH); 790 if (IS_ERR(st->gpio_reset)) 791 return PTR_ERR(st->gpio_reset); 792 793 /* Disable CRC checks */ 794 ret = ad5758_crc_disable(st); 795 if (ret < 0) 796 return ret; 797 798 /* Perform a reset */ 799 ret = ad5758_reset(st); 800 if (ret < 0) 801 return ret; 802 803 /* Disable CRC checks */ 804 ret = ad5758_crc_disable(st); 805 if (ret < 0) 806 return ret; 807 808 /* Perform a calibration memory refresh */ 809 ret = ad5758_calib_mem_refresh(st); 810 if (ret < 0) 811 return ret; 812 813 regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS); 814 if (regval < 0) 815 return regval; 816 817 /* Clear all the error flags */ 818 ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval); 819 if (ret < 0) 820 return ret; 821 822 /* Set the dc-to-dc current limit */ 823 ret = ad5758_set_dc_dc_ilim(st, st->dc_dc_ilim); 824 if (ret < 0) 825 return ret; 826 827 /* Configure the dc-to-dc controller mode */ 828 ret = ad5758_set_dc_dc_conv_mode(st, st->dc_dc_mode); 829 if (ret < 0) 830 return ret; 831 832 /* Configure the output range */ 833 ret = ad5758_set_out_range(st, st->out_range.reg); 834 if (ret < 0) 835 return ret; 836 837 /* Enable Slew Rate Control, set the slew rate clock and step */ 838 if (st->slew_time) { 839 ret = ad5758_slew_rate_config(st); 840 if (ret < 0) 841 return ret; 842 } 843 844 /* Enable the VIOUT fault protection switch (FPS is closed) */ 845 ret = ad5758_fault_prot_switch_en(st, 1); 846 if (ret < 0) 847 return ret; 848 849 /* Power up the DAC and internal (INT) amplifiers */ 850 ret = ad5758_internal_buffers_en(st, 1); 851 if (ret < 0) 852 return ret; 853 854 /* Enable VIOUT */ 855 return ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, 856 AD5758_DAC_CONFIG_OUT_EN_MSK, 857 AD5758_DAC_CONFIG_OUT_EN_MODE(1)); 858 } 859 860 static int ad5758_probe(struct spi_device *spi) 861 { 862 struct ad5758_state *st; 863 struct iio_dev *indio_dev; 864 int ret; 865 866 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 867 if (!indio_dev) 868 return -ENOMEM; 869 870 st = iio_priv(indio_dev); 871 spi_set_drvdata(spi, indio_dev); 872 873 st->spi = spi; 874 875 mutex_init(&st->lock); 876 877 indio_dev->dev.parent = &spi->dev; 878 indio_dev->name = spi_get_device_id(spi)->name; 879 indio_dev->info = &ad5758_info; 880 indio_dev->modes = INDIO_DIRECT_MODE; 881 indio_dev->num_channels = 1; 882 883 ret = ad5758_parse_dt(st); 884 if (ret < 0) 885 return ret; 886 887 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) 888 indio_dev->channels = ad5758_voltage_ch; 889 else 890 indio_dev->channels = ad5758_current_ch; 891 892 ret = ad5758_init(st); 893 if (ret < 0) { 894 dev_err(&spi->dev, "AD5758 init failed\n"); 895 return ret; 896 } 897 898 return devm_iio_device_register(&st->spi->dev, indio_dev); 899 } 900 901 static const struct spi_device_id ad5758_id[] = { 902 { "ad5758", 0 }, 903 {} 904 }; 905 MODULE_DEVICE_TABLE(spi, ad5758_id); 906 907 static struct spi_driver ad5758_driver = { 908 .driver = { 909 .name = KBUILD_MODNAME, 910 }, 911 .probe = ad5758_probe, 912 .id_table = ad5758_id, 913 }; 914 915 module_spi_driver(ad5758_driver); 916 917 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 918 MODULE_DESCRIPTION("Analog Devices AD5758 DAC"); 919 MODULE_LICENSE("GPL v2"); 920