1cbd5dd38SStefan Popa /* SPDX-License-Identifier: GPL-2.0 */ 20357e488SStefan Popa /* 30357e488SStefan Popa * This file is part of AD5686 DAC driver 40357e488SStefan Popa * 50357e488SStefan Popa * Copyright 2018 Analog Devices Inc. 60357e488SStefan Popa */ 70357e488SStefan Popa 80357e488SStefan Popa #ifndef __DRIVERS_IIO_DAC_AD5686_H__ 90357e488SStefan Popa #define __DRIVERS_IIO_DAC_AD5686_H__ 100357e488SStefan Popa 110357e488SStefan Popa #include <linux/types.h> 120357e488SStefan Popa #include <linux/cache.h> 130357e488SStefan Popa #include <linux/mutex.h> 140357e488SStefan Popa #include <linux/kernel.h> 150357e488SStefan Popa 1612d323cfSStefan Popa #define AD5310_CMD(x) ((x) << 12) 1712d323cfSStefan Popa 181dbae4c6SStefan Popa #define AD5683_DATA(x) ((x) << 4) 1912d323cfSStefan Popa 200357e488SStefan Popa #define AD5686_ADDR(x) ((x) << 16) 210357e488SStefan Popa #define AD5686_CMD(x) ((x) << 20) 220357e488SStefan Popa 230357e488SStefan Popa #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) 240357e488SStefan Popa #define AD5686_ADDR_ALL_DAC 0xF 250357e488SStefan Popa 260357e488SStefan Popa #define AD5686_CMD_NOOP 0x0 270357e488SStefan Popa #define AD5686_CMD_WRITE_INPUT_N 0x1 280357e488SStefan Popa #define AD5686_CMD_UPDATE_DAC_N 0x2 290357e488SStefan Popa #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 300357e488SStefan Popa #define AD5686_CMD_POWERDOWN_DAC 0x4 310357e488SStefan Popa #define AD5686_CMD_LDAC_MASK 0x5 320357e488SStefan Popa #define AD5686_CMD_RESET 0x6 330357e488SStefan Popa #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 340357e488SStefan Popa #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 350357e488SStefan Popa #define AD5686_CMD_READBACK_ENABLE 0x9 360357e488SStefan Popa 370357e488SStefan Popa #define AD5686_LDAC_PWRDN_NONE 0x0 380357e488SStefan Popa #define AD5686_LDAC_PWRDN_1K 0x1 390357e488SStefan Popa #define AD5686_LDAC_PWRDN_100K 0x2 400357e488SStefan Popa #define AD5686_LDAC_PWRDN_3STATE 0x3 410357e488SStefan Popa 42be1b24d2SStefan Popa #define AD5686_CMD_CONTROL_REG 0x4 431dbae4c6SStefan Popa #define AD5686_CMD_READBACK_ENABLE_V2 0x5 4412d323cfSStefan Popa 4512d323cfSStefan Popa #define AD5310_REF_BIT_MSK BIT(8) 461dbae4c6SStefan Popa #define AD5683_REF_BIT_MSK BIT(12) 47be1b24d2SStefan Popa #define AD5693_REF_BIT_MSK BIT(12) 48be1b24d2SStefan Popa 490357e488SStefan Popa /** 500357e488SStefan Popa * ad5686_supported_device_ids: 510357e488SStefan Popa */ 520357e488SStefan Popa enum ad5686_supported_device_ids { 5312d323cfSStefan Popa ID_AD5310R, 54d8084a04SStefan Popa ID_AD5311R, 554177381bSStefan Popa ID_AD5671R, 560357e488SStefan Popa ID_AD5672R, 57192778fbSMircea Caprioru ID_AD5674R, 584177381bSStefan Popa ID_AD5675R, 590357e488SStefan Popa ID_AD5676, 600357e488SStefan Popa ID_AD5676R, 61192778fbSMircea Caprioru ID_AD5679R, 621dbae4c6SStefan Popa ID_AD5681R, 631dbae4c6SStefan Popa ID_AD5682R, 641dbae4c6SStefan Popa ID_AD5683, 651dbae4c6SStefan Popa ID_AD5683R, 660357e488SStefan Popa ID_AD5684, 670357e488SStefan Popa ID_AD5684R, 680357e488SStefan Popa ID_AD5685R, 690357e488SStefan Popa ID_AD5686, 700357e488SStefan Popa ID_AD5686R, 71be1b24d2SStefan Popa ID_AD5691R, 72be1b24d2SStefan Popa ID_AD5692R, 73be1b24d2SStefan Popa ID_AD5693, 74be1b24d2SStefan Popa ID_AD5693R, 754177381bSStefan Popa ID_AD5694, 764177381bSStefan Popa ID_AD5694R, 774177381bSStefan Popa ID_AD5695R, 784177381bSStefan Popa ID_AD5696, 794177381bSStefan Popa ID_AD5696R, 800357e488SStefan Popa }; 810357e488SStefan Popa 82be1b24d2SStefan Popa enum ad5686_regmap_type { 8312d323cfSStefan Popa AD5310_REGMAP, 841dbae4c6SStefan Popa AD5683_REGMAP, 85be1b24d2SStefan Popa AD5686_REGMAP, 86be1b24d2SStefan Popa AD5693_REGMAP 87be1b24d2SStefan Popa }; 88be1b24d2SStefan Popa 890357e488SStefan Popa struct ad5686_state; 900357e488SStefan Popa 910357e488SStefan Popa typedef int (*ad5686_write_func)(struct ad5686_state *st, 920357e488SStefan Popa u8 cmd, u8 addr, u16 val); 930357e488SStefan Popa 940357e488SStefan Popa typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr); 950357e488SStefan Popa 960357e488SStefan Popa /** 970357e488SStefan Popa * struct ad5686_chip_info - chip specific information 980357e488SStefan Popa * @int_vref_mv: AD5620/40/60: the internal reference voltage 990357e488SStefan Popa * @num_channels: number of channels 1000357e488SStefan Popa * @channel: channel specification 101be1b24d2SStefan Popa * @regmap_type: register map layout variant 1020357e488SStefan Popa */ 1030357e488SStefan Popa 1040357e488SStefan Popa struct ad5686_chip_info { 1050357e488SStefan Popa u16 int_vref_mv; 1060357e488SStefan Popa unsigned int num_channels; 10759713492SRikard Falkeborn const struct iio_chan_spec *channels; 108be1b24d2SStefan Popa enum ad5686_regmap_type regmap_type; 1090357e488SStefan Popa }; 1100357e488SStefan Popa 1110357e488SStefan Popa /** 1120357e488SStefan Popa * struct ad5446_state - driver instance specific data 1130357e488SStefan Popa * @spi: spi_device 1140357e488SStefan Popa * @chip_info: chip model specific constants, available modes etc 1150357e488SStefan Popa * @reg: supply regulator 1160357e488SStefan Popa * @vref_mv: actual reference voltage used 1170357e488SStefan Popa * @pwr_down_mask: power down mask 1180357e488SStefan Popa * @pwr_down_mode: current power down mode 119be1b24d2SStefan Popa * @use_internal_vref: set to true if the internal reference voltage is used 1200b2884efSSergiu Cuciurean * @lock lock to protect the data buffer during regmap ops 1210357e488SStefan Popa * @data: spi transfer buffers 1220357e488SStefan Popa */ 1230357e488SStefan Popa 1240357e488SStefan Popa struct ad5686_state { 1250357e488SStefan Popa struct device *dev; 1260357e488SStefan Popa const struct ad5686_chip_info *chip_info; 1270357e488SStefan Popa struct regulator *reg; 1280357e488SStefan Popa unsigned short vref_mv; 1290357e488SStefan Popa unsigned int pwr_down_mask; 1300357e488SStefan Popa unsigned int pwr_down_mode; 1310357e488SStefan Popa ad5686_write_func write; 1320357e488SStefan Popa ad5686_read_func read; 133be1b24d2SStefan Popa bool use_internal_vref; 1340b2884efSSergiu Cuciurean struct mutex lock; 1350357e488SStefan Popa 1360357e488SStefan Popa /* 1370357e488SStefan Popa * DMA (thus cache coherency maintenance) requires the 1380357e488SStefan Popa * transfer buffers to live in their own cache lines. 1390357e488SStefan Popa */ 1400357e488SStefan Popa 1410357e488SStefan Popa union { 1420357e488SStefan Popa __be32 d32; 1430357e488SStefan Popa __be16 d16; 1440357e488SStefan Popa u8 d8[4]; 1450357e488SStefan Popa } data[3] ____cacheline_aligned; 1460357e488SStefan Popa }; 1470357e488SStefan Popa 1480357e488SStefan Popa 1490357e488SStefan Popa int ad5686_probe(struct device *dev, 1500357e488SStefan Popa enum ad5686_supported_device_ids chip_type, 1510357e488SStefan Popa const char *name, ad5686_write_func write, 1520357e488SStefan Popa ad5686_read_func read); 1530357e488SStefan Popa 1540357e488SStefan Popa int ad5686_remove(struct device *dev); 1550357e488SStefan Popa 1560357e488SStefan Popa 1570357e488SStefan Popa #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */ 158