1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5592R Digital <-> Analog converters driver 4 * 5 * Copyright 2014-2016 Analog Devices Inc. 6 * Author: Paul Cercueil <paul.cercueil@analog.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/iio/iio.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/property.h> 18 19 #include <dt-bindings/iio/adi,ad5592r.h> 20 21 #include "ad5592r-base.h" 22 23 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset) 24 { 25 struct ad5592r_state *st = gpiochip_get_data(chip); 26 int ret = 0; 27 u8 val; 28 29 mutex_lock(&st->gpio_lock); 30 31 if (st->gpio_out & BIT(offset)) 32 val = st->gpio_val; 33 else 34 ret = st->ops->gpio_read(st, &val); 35 36 mutex_unlock(&st->gpio_lock); 37 38 if (ret < 0) 39 return ret; 40 41 return !!(val & BIT(offset)); 42 } 43 44 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 45 { 46 struct ad5592r_state *st = gpiochip_get_data(chip); 47 48 mutex_lock(&st->gpio_lock); 49 50 if (value) 51 st->gpio_val |= BIT(offset); 52 else 53 st->gpio_val &= ~BIT(offset); 54 55 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 56 57 mutex_unlock(&st->gpio_lock); 58 } 59 60 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 61 { 62 struct ad5592r_state *st = gpiochip_get_data(chip); 63 int ret; 64 65 mutex_lock(&st->gpio_lock); 66 67 st->gpio_out &= ~BIT(offset); 68 st->gpio_in |= BIT(offset); 69 70 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 71 if (ret < 0) 72 goto err_unlock; 73 74 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 75 76 err_unlock: 77 mutex_unlock(&st->gpio_lock); 78 79 return ret; 80 } 81 82 static int ad5592r_gpio_direction_output(struct gpio_chip *chip, 83 unsigned offset, int value) 84 { 85 struct ad5592r_state *st = gpiochip_get_data(chip); 86 int ret; 87 88 mutex_lock(&st->gpio_lock); 89 90 if (value) 91 st->gpio_val |= BIT(offset); 92 else 93 st->gpio_val &= ~BIT(offset); 94 95 st->gpio_in &= ~BIT(offset); 96 st->gpio_out |= BIT(offset); 97 98 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 99 if (ret < 0) 100 goto err_unlock; 101 102 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 103 if (ret < 0) 104 goto err_unlock; 105 106 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 107 108 err_unlock: 109 mutex_unlock(&st->gpio_lock); 110 111 return ret; 112 } 113 114 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) 115 { 116 struct ad5592r_state *st = gpiochip_get_data(chip); 117 118 if (!(st->gpio_map & BIT(offset))) { 119 dev_err(st->dev, "GPIO %d is reserved by alternate function\n", 120 offset); 121 return -ENODEV; 122 } 123 124 return 0; 125 } 126 127 static int ad5592r_gpio_init(struct ad5592r_state *st) 128 { 129 if (!st->gpio_map) 130 return 0; 131 132 st->gpiochip.label = dev_name(st->dev); 133 st->gpiochip.base = -1; 134 st->gpiochip.ngpio = 8; 135 st->gpiochip.parent = st->dev; 136 st->gpiochip.can_sleep = true; 137 st->gpiochip.direction_input = ad5592r_gpio_direction_input; 138 st->gpiochip.direction_output = ad5592r_gpio_direction_output; 139 st->gpiochip.get = ad5592r_gpio_get; 140 st->gpiochip.set = ad5592r_gpio_set; 141 st->gpiochip.request = ad5592r_gpio_request; 142 st->gpiochip.owner = THIS_MODULE; 143 144 mutex_init(&st->gpio_lock); 145 146 return gpiochip_add_data(&st->gpiochip, st); 147 } 148 149 static void ad5592r_gpio_cleanup(struct ad5592r_state *st) 150 { 151 if (st->gpio_map) 152 gpiochip_remove(&st->gpiochip); 153 } 154 155 static int ad5592r_reset(struct ad5592r_state *st) 156 { 157 struct gpio_desc *gpio; 158 159 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 160 if (IS_ERR(gpio)) 161 return PTR_ERR(gpio); 162 163 if (gpio) { 164 udelay(1); 165 gpiod_set_value(gpio, 1); 166 } else { 167 mutex_lock(&st->lock); 168 /* Writing this magic value resets the device */ 169 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); 170 mutex_unlock(&st->lock); 171 } 172 173 udelay(250); 174 175 return 0; 176 } 177 178 static int ad5592r_get_vref(struct ad5592r_state *st) 179 { 180 int ret; 181 182 if (st->reg) { 183 ret = regulator_get_voltage(st->reg); 184 if (ret < 0) 185 return ret; 186 187 return ret / 1000; 188 } else { 189 return 2500; 190 } 191 } 192 193 static int ad5592r_set_channel_modes(struct ad5592r_state *st) 194 { 195 const struct ad5592r_rw_ops *ops = st->ops; 196 int ret; 197 unsigned i; 198 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; 199 u16 read_back; 200 201 for (i = 0; i < st->num_channels; i++) { 202 switch (st->channel_modes[i]) { 203 case CH_MODE_DAC: 204 dac |= BIT(i); 205 break; 206 207 case CH_MODE_ADC: 208 adc |= BIT(i); 209 break; 210 211 case CH_MODE_DAC_AND_ADC: 212 dac |= BIT(i); 213 adc |= BIT(i); 214 break; 215 216 case CH_MODE_GPIO: 217 st->gpio_map |= BIT(i); 218 st->gpio_in |= BIT(i); /* Default to input */ 219 break; 220 221 case CH_MODE_UNUSED: 222 default: 223 switch (st->channel_offstate[i]) { 224 case CH_OFFSTATE_OUT_TRISTATE: 225 tristate |= BIT(i); 226 break; 227 228 case CH_OFFSTATE_OUT_LOW: 229 st->gpio_out |= BIT(i); 230 break; 231 232 case CH_OFFSTATE_OUT_HIGH: 233 st->gpio_out |= BIT(i); 234 st->gpio_val |= BIT(i); 235 break; 236 237 case CH_OFFSTATE_PULLDOWN: 238 default: 239 pulldown |= BIT(i); 240 break; 241 } 242 } 243 } 244 245 mutex_lock(&st->lock); 246 247 /* Pull down unused pins to GND */ 248 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); 249 if (ret) 250 goto err_unlock; 251 252 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); 253 if (ret) 254 goto err_unlock; 255 256 /* Configure pins that we use */ 257 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); 258 if (ret) 259 goto err_unlock; 260 261 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc); 262 if (ret) 263 goto err_unlock; 264 265 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 266 if (ret) 267 goto err_unlock; 268 269 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 270 if (ret) 271 goto err_unlock; 272 273 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 274 if (ret) 275 goto err_unlock; 276 277 /* Verify that we can read back at least one register */ 278 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); 279 if (!ret && (read_back & 0xff) != adc) 280 ret = -EIO; 281 282 err_unlock: 283 mutex_unlock(&st->lock); 284 return ret; 285 } 286 287 static int ad5592r_reset_channel_modes(struct ad5592r_state *st) 288 { 289 int i; 290 291 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++) 292 st->channel_modes[i] = CH_MODE_UNUSED; 293 294 return ad5592r_set_channel_modes(st); 295 } 296 297 static int ad5592r_write_raw(struct iio_dev *iio_dev, 298 struct iio_chan_spec const *chan, int val, int val2, long mask) 299 { 300 struct ad5592r_state *st = iio_priv(iio_dev); 301 int ret; 302 303 switch (mask) { 304 case IIO_CHAN_INFO_RAW: 305 306 if (val >= (1 << chan->scan_type.realbits) || val < 0) 307 return -EINVAL; 308 309 if (!chan->output) 310 return -EINVAL; 311 312 mutex_lock(&st->lock); 313 ret = st->ops->write_dac(st, chan->channel, val); 314 if (!ret) 315 st->cached_dac[chan->channel] = val; 316 mutex_unlock(&st->lock); 317 return ret; 318 case IIO_CHAN_INFO_SCALE: 319 if (chan->type == IIO_VOLTAGE) { 320 bool gain; 321 322 if (val == st->scale_avail[0][0] && 323 val2 == st->scale_avail[0][1]) 324 gain = false; 325 else if (val == st->scale_avail[1][0] && 326 val2 == st->scale_avail[1][1]) 327 gain = true; 328 else 329 return -EINVAL; 330 331 mutex_lock(&st->lock); 332 333 ret = st->ops->reg_read(st, AD5592R_REG_CTRL, 334 &st->cached_gp_ctrl); 335 if (ret < 0) { 336 mutex_unlock(&st->lock); 337 return ret; 338 } 339 340 if (chan->output) { 341 if (gain) 342 st->cached_gp_ctrl |= 343 AD5592R_REG_CTRL_DAC_RANGE; 344 else 345 st->cached_gp_ctrl &= 346 ~AD5592R_REG_CTRL_DAC_RANGE; 347 } else { 348 if (gain) 349 st->cached_gp_ctrl |= 350 AD5592R_REG_CTRL_ADC_RANGE; 351 else 352 st->cached_gp_ctrl &= 353 ~AD5592R_REG_CTRL_ADC_RANGE; 354 } 355 356 ret = st->ops->reg_write(st, AD5592R_REG_CTRL, 357 st->cached_gp_ctrl); 358 mutex_unlock(&st->lock); 359 360 return ret; 361 } 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 return 0; 368 } 369 370 static int ad5592r_read_raw(struct iio_dev *iio_dev, 371 struct iio_chan_spec const *chan, 372 int *val, int *val2, long m) 373 { 374 struct ad5592r_state *st = iio_priv(iio_dev); 375 u16 read_val; 376 int ret, mult; 377 378 switch (m) { 379 case IIO_CHAN_INFO_RAW: 380 if (!chan->output) { 381 mutex_lock(&st->lock); 382 ret = st->ops->read_adc(st, chan->channel, &read_val); 383 mutex_unlock(&st->lock); 384 if (ret) 385 return ret; 386 387 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) { 388 dev_err(st->dev, "Error while reading channel %u\n", 389 chan->channel); 390 return -EIO; 391 } 392 393 read_val &= GENMASK(11, 0); 394 395 } else { 396 mutex_lock(&st->lock); 397 read_val = st->cached_dac[chan->channel]; 398 mutex_unlock(&st->lock); 399 } 400 401 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", 402 chan->channel, read_val); 403 404 *val = (int) read_val; 405 return IIO_VAL_INT; 406 case IIO_CHAN_INFO_SCALE: 407 *val = ad5592r_get_vref(st); 408 409 if (chan->type == IIO_TEMP) { 410 s64 tmp = *val * (3767897513LL / 25LL); 411 *val = div_s64_rem(tmp, 1000000000LL, val2); 412 413 return IIO_VAL_INT_PLUS_MICRO; 414 } 415 416 mutex_lock(&st->lock); 417 418 if (chan->output) 419 mult = !!(st->cached_gp_ctrl & 420 AD5592R_REG_CTRL_DAC_RANGE); 421 else 422 mult = !!(st->cached_gp_ctrl & 423 AD5592R_REG_CTRL_ADC_RANGE); 424 425 mutex_unlock(&st->lock); 426 427 *val *= ++mult; 428 429 *val2 = chan->scan_type.realbits; 430 431 return IIO_VAL_FRACTIONAL_LOG2; 432 case IIO_CHAN_INFO_OFFSET: 433 ret = ad5592r_get_vref(st); 434 435 mutex_lock(&st->lock); 436 437 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) 438 *val = (-34365 * 25) / ret; 439 else 440 *val = (-75365 * 25) / ret; 441 442 mutex_unlock(&st->lock); 443 444 return IIO_VAL_INT; 445 default: 446 return -EINVAL; 447 } 448 } 449 450 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev, 451 struct iio_chan_spec const *chan, long mask) 452 { 453 switch (mask) { 454 case IIO_CHAN_INFO_SCALE: 455 return IIO_VAL_INT_PLUS_NANO; 456 457 default: 458 return IIO_VAL_INT_PLUS_MICRO; 459 } 460 461 return -EINVAL; 462 } 463 464 static const struct iio_info ad5592r_info = { 465 .read_raw = ad5592r_read_raw, 466 .write_raw = ad5592r_write_raw, 467 .write_raw_get_fmt = ad5592r_write_raw_get_fmt, 468 }; 469 470 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, 471 uintptr_t private, 472 const struct iio_chan_spec *chan, 473 char *buf) 474 { 475 struct ad5592r_state *st = iio_priv(iio_dev); 476 477 return sprintf(buf, "%d.%09u %d.%09u\n", 478 st->scale_avail[0][0], st->scale_avail[0][1], 479 st->scale_avail[1][0], st->scale_avail[1][1]); 480 } 481 482 static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = { 483 { 484 .name = "scale_available", 485 .read = ad5592r_show_scale_available, 486 .shared = IIO_SHARED_BY_TYPE, 487 }, 488 {}, 489 }; 490 491 static void ad5592r_setup_channel(struct iio_dev *iio_dev, 492 struct iio_chan_spec *chan, bool output, unsigned id) 493 { 494 chan->type = IIO_VOLTAGE; 495 chan->indexed = 1; 496 chan->output = output; 497 chan->channel = id; 498 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 499 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 500 chan->scan_type.sign = 'u'; 501 chan->scan_type.realbits = 12; 502 chan->scan_type.storagebits = 16; 503 chan->ext_info = ad5592r_ext_info; 504 } 505 506 static int ad5592r_alloc_channels(struct iio_dev *iio_dev) 507 { 508 struct ad5592r_state *st = iio_priv(iio_dev); 509 unsigned i, curr_channel = 0, 510 num_channels = st->num_channels; 511 struct iio_chan_spec *channels; 512 struct fwnode_handle *child; 513 u32 reg, tmp; 514 int ret; 515 516 device_for_each_child_node(st->dev, child) { 517 ret = fwnode_property_read_u32(child, "reg", ®); 518 if (ret || reg >= ARRAY_SIZE(st->channel_modes)) 519 continue; 520 521 ret = fwnode_property_read_u32(child, "adi,mode", &tmp); 522 if (!ret) 523 st->channel_modes[reg] = tmp; 524 525 ret = fwnode_property_read_u32(child, "adi,off-state", &tmp); 526 if (!ret) 527 st->channel_offstate[reg] = tmp; 528 } 529 530 channels = devm_kcalloc(st->dev, 531 1 + 2 * num_channels, sizeof(*channels), 532 GFP_KERNEL); 533 if (!channels) 534 return -ENOMEM; 535 536 for (i = 0; i < num_channels; i++) { 537 switch (st->channel_modes[i]) { 538 case CH_MODE_DAC: 539 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 540 true, i); 541 curr_channel++; 542 break; 543 544 case CH_MODE_ADC: 545 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 546 false, i); 547 curr_channel++; 548 break; 549 550 case CH_MODE_DAC_AND_ADC: 551 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 552 true, i); 553 curr_channel++; 554 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 555 false, i); 556 curr_channel++; 557 break; 558 559 default: 560 continue; 561 } 562 } 563 564 channels[curr_channel].type = IIO_TEMP; 565 channels[curr_channel].channel = 8; 566 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 567 BIT(IIO_CHAN_INFO_SCALE) | 568 BIT(IIO_CHAN_INFO_OFFSET); 569 curr_channel++; 570 571 iio_dev->num_channels = curr_channel; 572 iio_dev->channels = channels; 573 574 return 0; 575 } 576 577 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV) 578 { 579 s64 tmp = (s64)vref_mV * 1000000000LL >> 12; 580 581 st->scale_avail[0][0] = 582 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]); 583 st->scale_avail[1][0] = 584 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]); 585 } 586 587 int ad5592r_probe(struct device *dev, const char *name, 588 const struct ad5592r_rw_ops *ops) 589 { 590 struct iio_dev *iio_dev; 591 struct ad5592r_state *st; 592 int ret; 593 594 iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 595 if (!iio_dev) 596 return -ENOMEM; 597 598 st = iio_priv(iio_dev); 599 st->dev = dev; 600 st->ops = ops; 601 st->num_channels = 8; 602 dev_set_drvdata(dev, iio_dev); 603 604 st->reg = devm_regulator_get_optional(dev, "vref"); 605 if (IS_ERR(st->reg)) { 606 if ((PTR_ERR(st->reg) != -ENODEV) && dev_fwnode(dev)) 607 return PTR_ERR(st->reg); 608 609 st->reg = NULL; 610 } else { 611 ret = regulator_enable(st->reg); 612 if (ret) 613 return ret; 614 } 615 616 iio_dev->name = name; 617 iio_dev->info = &ad5592r_info; 618 iio_dev->modes = INDIO_DIRECT_MODE; 619 620 mutex_init(&st->lock); 621 622 ad5592r_init_scales(st, ad5592r_get_vref(st)); 623 624 ret = ad5592r_reset(st); 625 if (ret) 626 goto error_disable_reg; 627 628 ret = ops->reg_write(st, AD5592R_REG_PD, 629 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); 630 if (ret) 631 goto error_disable_reg; 632 633 ret = ad5592r_alloc_channels(iio_dev); 634 if (ret) 635 goto error_disable_reg; 636 637 ret = ad5592r_set_channel_modes(st); 638 if (ret) 639 goto error_reset_ch_modes; 640 641 ret = iio_device_register(iio_dev); 642 if (ret) 643 goto error_reset_ch_modes; 644 645 ret = ad5592r_gpio_init(st); 646 if (ret) 647 goto error_dev_unregister; 648 649 return 0; 650 651 error_dev_unregister: 652 iio_device_unregister(iio_dev); 653 654 error_reset_ch_modes: 655 ad5592r_reset_channel_modes(st); 656 657 error_disable_reg: 658 if (st->reg) 659 regulator_disable(st->reg); 660 661 return ret; 662 } 663 EXPORT_SYMBOL_NS_GPL(ad5592r_probe, IIO_AD5592R); 664 665 void ad5592r_remove(struct device *dev) 666 { 667 struct iio_dev *iio_dev = dev_get_drvdata(dev); 668 struct ad5592r_state *st = iio_priv(iio_dev); 669 670 iio_device_unregister(iio_dev); 671 ad5592r_reset_channel_modes(st); 672 ad5592r_gpio_cleanup(st); 673 674 if (st->reg) 675 regulator_disable(st->reg); 676 } 677 EXPORT_SYMBOL_NS_GPL(ad5592r_remove, IIO_AD5592R); 678 679 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>"); 680 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); 681 MODULE_LICENSE("GPL v2"); 682