1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5592R Digital <-> Analog converters driver 4 * 5 * Copyright 2014-2016 Analog Devices Inc. 6 * Author: Paul Cercueil <paul.cercueil@analog.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/iio/iio.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/property.h> 19 20 #include <dt-bindings/iio/adi,ad5592r.h> 21 22 #include "ad5592r-base.h" 23 24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset) 25 { 26 struct ad5592r_state *st = gpiochip_get_data(chip); 27 int ret = 0; 28 u8 val; 29 30 mutex_lock(&st->gpio_lock); 31 32 if (st->gpio_out & BIT(offset)) 33 val = st->gpio_val; 34 else 35 ret = st->ops->gpio_read(st, &val); 36 37 mutex_unlock(&st->gpio_lock); 38 39 if (ret < 0) 40 return ret; 41 42 return !!(val & BIT(offset)); 43 } 44 45 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 46 { 47 struct ad5592r_state *st = gpiochip_get_data(chip); 48 49 mutex_lock(&st->gpio_lock); 50 51 if (value) 52 st->gpio_val |= BIT(offset); 53 else 54 st->gpio_val &= ~BIT(offset); 55 56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 57 58 mutex_unlock(&st->gpio_lock); 59 } 60 61 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 62 { 63 struct ad5592r_state *st = gpiochip_get_data(chip); 64 int ret; 65 66 mutex_lock(&st->gpio_lock); 67 68 st->gpio_out &= ~BIT(offset); 69 st->gpio_in |= BIT(offset); 70 71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 72 if (ret < 0) 73 goto err_unlock; 74 75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 76 77 err_unlock: 78 mutex_unlock(&st->gpio_lock); 79 80 return ret; 81 } 82 83 static int ad5592r_gpio_direction_output(struct gpio_chip *chip, 84 unsigned offset, int value) 85 { 86 struct ad5592r_state *st = gpiochip_get_data(chip); 87 int ret; 88 89 mutex_lock(&st->gpio_lock); 90 91 if (value) 92 st->gpio_val |= BIT(offset); 93 else 94 st->gpio_val &= ~BIT(offset); 95 96 st->gpio_in &= ~BIT(offset); 97 st->gpio_out |= BIT(offset); 98 99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 100 if (ret < 0) 101 goto err_unlock; 102 103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 104 if (ret < 0) 105 goto err_unlock; 106 107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 108 109 err_unlock: 110 mutex_unlock(&st->gpio_lock); 111 112 return ret; 113 } 114 115 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) 116 { 117 struct ad5592r_state *st = gpiochip_get_data(chip); 118 119 if (!(st->gpio_map & BIT(offset))) { 120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n", 121 offset); 122 return -ENODEV; 123 } 124 125 return 0; 126 } 127 128 static int ad5592r_gpio_init(struct ad5592r_state *st) 129 { 130 if (!st->gpio_map) 131 return 0; 132 133 st->gpiochip.label = dev_name(st->dev); 134 st->gpiochip.base = -1; 135 st->gpiochip.ngpio = 8; 136 st->gpiochip.parent = st->dev; 137 st->gpiochip.can_sleep = true; 138 st->gpiochip.direction_input = ad5592r_gpio_direction_input; 139 st->gpiochip.direction_output = ad5592r_gpio_direction_output; 140 st->gpiochip.get = ad5592r_gpio_get; 141 st->gpiochip.set = ad5592r_gpio_set; 142 st->gpiochip.request = ad5592r_gpio_request; 143 st->gpiochip.owner = THIS_MODULE; 144 145 mutex_init(&st->gpio_lock); 146 147 return gpiochip_add_data(&st->gpiochip, st); 148 } 149 150 static void ad5592r_gpio_cleanup(struct ad5592r_state *st) 151 { 152 if (st->gpio_map) 153 gpiochip_remove(&st->gpiochip); 154 } 155 156 static int ad5592r_reset(struct ad5592r_state *st) 157 { 158 struct gpio_desc *gpio; 159 160 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 161 if (IS_ERR(gpio)) 162 return PTR_ERR(gpio); 163 164 if (gpio) { 165 udelay(1); 166 gpiod_set_value(gpio, 1); 167 } else { 168 mutex_lock(&st->lock); 169 /* Writing this magic value resets the device */ 170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); 171 mutex_unlock(&st->lock); 172 } 173 174 udelay(250); 175 176 return 0; 177 } 178 179 static int ad5592r_get_vref(struct ad5592r_state *st) 180 { 181 int ret; 182 183 if (st->reg) { 184 ret = regulator_get_voltage(st->reg); 185 if (ret < 0) 186 return ret; 187 188 return ret / 1000; 189 } else { 190 return 2500; 191 } 192 } 193 194 static int ad5592r_set_channel_modes(struct ad5592r_state *st) 195 { 196 const struct ad5592r_rw_ops *ops = st->ops; 197 int ret; 198 unsigned i; 199 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; 200 u16 read_back; 201 202 for (i = 0; i < st->num_channels; i++) { 203 switch (st->channel_modes[i]) { 204 case CH_MODE_DAC: 205 dac |= BIT(i); 206 break; 207 208 case CH_MODE_ADC: 209 adc |= BIT(i); 210 break; 211 212 case CH_MODE_DAC_AND_ADC: 213 dac |= BIT(i); 214 adc |= BIT(i); 215 break; 216 217 case CH_MODE_GPIO: 218 st->gpio_map |= BIT(i); 219 st->gpio_in |= BIT(i); /* Default to input */ 220 break; 221 222 case CH_MODE_UNUSED: 223 default: 224 switch (st->channel_offstate[i]) { 225 case CH_OFFSTATE_OUT_TRISTATE: 226 tristate |= BIT(i); 227 break; 228 229 case CH_OFFSTATE_OUT_LOW: 230 st->gpio_out |= BIT(i); 231 break; 232 233 case CH_OFFSTATE_OUT_HIGH: 234 st->gpio_out |= BIT(i); 235 st->gpio_val |= BIT(i); 236 break; 237 238 case CH_OFFSTATE_PULLDOWN: 239 default: 240 pulldown |= BIT(i); 241 break; 242 } 243 } 244 } 245 246 mutex_lock(&st->lock); 247 248 /* Pull down unused pins to GND */ 249 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); 250 if (ret) 251 goto err_unlock; 252 253 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); 254 if (ret) 255 goto err_unlock; 256 257 /* Configure pins that we use */ 258 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); 259 if (ret) 260 goto err_unlock; 261 262 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc); 263 if (ret) 264 goto err_unlock; 265 266 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 267 if (ret) 268 goto err_unlock; 269 270 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 271 if (ret) 272 goto err_unlock; 273 274 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 275 if (ret) 276 goto err_unlock; 277 278 /* Verify that we can read back at least one register */ 279 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); 280 if (!ret && (read_back & 0xff) != adc) 281 ret = -EIO; 282 283 err_unlock: 284 mutex_unlock(&st->lock); 285 return ret; 286 } 287 288 static int ad5592r_reset_channel_modes(struct ad5592r_state *st) 289 { 290 int i; 291 292 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++) 293 st->channel_modes[i] = CH_MODE_UNUSED; 294 295 return ad5592r_set_channel_modes(st); 296 } 297 298 static int ad5592r_write_raw(struct iio_dev *iio_dev, 299 struct iio_chan_spec const *chan, int val, int val2, long mask) 300 { 301 struct ad5592r_state *st = iio_priv(iio_dev); 302 int ret; 303 304 switch (mask) { 305 case IIO_CHAN_INFO_RAW: 306 307 if (val >= (1 << chan->scan_type.realbits) || val < 0) 308 return -EINVAL; 309 310 if (!chan->output) 311 return -EINVAL; 312 313 mutex_lock(&st->lock); 314 ret = st->ops->write_dac(st, chan->channel, val); 315 if (!ret) 316 st->cached_dac[chan->channel] = val; 317 mutex_unlock(&st->lock); 318 return ret; 319 case IIO_CHAN_INFO_SCALE: 320 if (chan->type == IIO_VOLTAGE) { 321 bool gain; 322 323 if (val == st->scale_avail[0][0] && 324 val2 == st->scale_avail[0][1]) 325 gain = false; 326 else if (val == st->scale_avail[1][0] && 327 val2 == st->scale_avail[1][1]) 328 gain = true; 329 else 330 return -EINVAL; 331 332 mutex_lock(&st->lock); 333 334 ret = st->ops->reg_read(st, AD5592R_REG_CTRL, 335 &st->cached_gp_ctrl); 336 if (ret < 0) { 337 mutex_unlock(&st->lock); 338 return ret; 339 } 340 341 if (chan->output) { 342 if (gain) 343 st->cached_gp_ctrl |= 344 AD5592R_REG_CTRL_DAC_RANGE; 345 else 346 st->cached_gp_ctrl &= 347 ~AD5592R_REG_CTRL_DAC_RANGE; 348 } else { 349 if (gain) 350 st->cached_gp_ctrl |= 351 AD5592R_REG_CTRL_ADC_RANGE; 352 else 353 st->cached_gp_ctrl &= 354 ~AD5592R_REG_CTRL_ADC_RANGE; 355 } 356 357 ret = st->ops->reg_write(st, AD5592R_REG_CTRL, 358 st->cached_gp_ctrl); 359 mutex_unlock(&st->lock); 360 361 return ret; 362 } 363 break; 364 default: 365 return -EINVAL; 366 } 367 368 return 0; 369 } 370 371 static int ad5592r_read_raw(struct iio_dev *iio_dev, 372 struct iio_chan_spec const *chan, 373 int *val, int *val2, long m) 374 { 375 struct ad5592r_state *st = iio_priv(iio_dev); 376 u16 read_val; 377 int ret; 378 379 switch (m) { 380 case IIO_CHAN_INFO_RAW: 381 mutex_lock(&st->lock); 382 383 if (!chan->output) { 384 ret = st->ops->read_adc(st, chan->channel, &read_val); 385 if (ret) 386 goto unlock; 387 388 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) { 389 dev_err(st->dev, "Error while reading channel %u\n", 390 chan->channel); 391 ret = -EIO; 392 goto unlock; 393 } 394 395 read_val &= GENMASK(11, 0); 396 397 } else { 398 read_val = st->cached_dac[chan->channel]; 399 } 400 401 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", 402 chan->channel, read_val); 403 404 *val = (int) read_val; 405 ret = IIO_VAL_INT; 406 break; 407 case IIO_CHAN_INFO_SCALE: 408 *val = ad5592r_get_vref(st); 409 410 if (chan->type == IIO_TEMP) { 411 s64 tmp = *val * (3767897513LL / 25LL); 412 *val = div_s64_rem(tmp, 1000000000LL, val2); 413 414 return IIO_VAL_INT_PLUS_MICRO; 415 } else { 416 int mult; 417 418 mutex_lock(&st->lock); 419 420 if (chan->output) 421 mult = !!(st->cached_gp_ctrl & 422 AD5592R_REG_CTRL_DAC_RANGE); 423 else 424 mult = !!(st->cached_gp_ctrl & 425 AD5592R_REG_CTRL_ADC_RANGE); 426 427 *val *= ++mult; 428 429 *val2 = chan->scan_type.realbits; 430 ret = IIO_VAL_FRACTIONAL_LOG2; 431 } 432 break; 433 case IIO_CHAN_INFO_OFFSET: 434 ret = ad5592r_get_vref(st); 435 436 mutex_lock(&st->lock); 437 438 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) 439 *val = (-34365 * 25) / ret; 440 else 441 *val = (-75365 * 25) / ret; 442 ret = IIO_VAL_INT; 443 break; 444 default: 445 return -EINVAL; 446 } 447 448 unlock: 449 mutex_unlock(&st->lock); 450 return ret; 451 } 452 453 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev, 454 struct iio_chan_spec const *chan, long mask) 455 { 456 switch (mask) { 457 case IIO_CHAN_INFO_SCALE: 458 return IIO_VAL_INT_PLUS_NANO; 459 460 default: 461 return IIO_VAL_INT_PLUS_MICRO; 462 } 463 464 return -EINVAL; 465 } 466 467 static const struct iio_info ad5592r_info = { 468 .read_raw = ad5592r_read_raw, 469 .write_raw = ad5592r_write_raw, 470 .write_raw_get_fmt = ad5592r_write_raw_get_fmt, 471 }; 472 473 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, 474 uintptr_t private, 475 const struct iio_chan_spec *chan, 476 char *buf) 477 { 478 struct ad5592r_state *st = iio_priv(iio_dev); 479 480 return sprintf(buf, "%d.%09u %d.%09u\n", 481 st->scale_avail[0][0], st->scale_avail[0][1], 482 st->scale_avail[1][0], st->scale_avail[1][1]); 483 } 484 485 static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = { 486 { 487 .name = "scale_available", 488 .read = ad5592r_show_scale_available, 489 .shared = true, 490 }, 491 {}, 492 }; 493 494 static void ad5592r_setup_channel(struct iio_dev *iio_dev, 495 struct iio_chan_spec *chan, bool output, unsigned id) 496 { 497 chan->type = IIO_VOLTAGE; 498 chan->indexed = 1; 499 chan->output = output; 500 chan->channel = id; 501 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 502 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 503 chan->scan_type.sign = 'u'; 504 chan->scan_type.realbits = 12; 505 chan->scan_type.storagebits = 16; 506 chan->ext_info = ad5592r_ext_info; 507 } 508 509 static int ad5592r_alloc_channels(struct iio_dev *iio_dev) 510 { 511 struct ad5592r_state *st = iio_priv(iio_dev); 512 unsigned i, curr_channel = 0, 513 num_channels = st->num_channels; 514 struct iio_chan_spec *channels; 515 struct fwnode_handle *child; 516 u32 reg, tmp; 517 int ret; 518 519 device_for_each_child_node(st->dev, child) { 520 ret = fwnode_property_read_u32(child, "reg", ®); 521 if (ret || reg >= ARRAY_SIZE(st->channel_modes)) 522 continue; 523 524 ret = fwnode_property_read_u32(child, "adi,mode", &tmp); 525 if (!ret) 526 st->channel_modes[reg] = tmp; 527 528 fwnode_property_read_u32(child, "adi,off-state", &tmp); 529 if (!ret) 530 st->channel_offstate[reg] = tmp; 531 } 532 533 channels = devm_kcalloc(st->dev, 534 1 + 2 * num_channels, sizeof(*channels), 535 GFP_KERNEL); 536 if (!channels) 537 return -ENOMEM; 538 539 for (i = 0; i < num_channels; i++) { 540 switch (st->channel_modes[i]) { 541 case CH_MODE_DAC: 542 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 543 true, i); 544 curr_channel++; 545 break; 546 547 case CH_MODE_ADC: 548 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 549 false, i); 550 curr_channel++; 551 break; 552 553 case CH_MODE_DAC_AND_ADC: 554 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 555 true, i); 556 curr_channel++; 557 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 558 false, i); 559 curr_channel++; 560 break; 561 562 default: 563 continue; 564 } 565 } 566 567 channels[curr_channel].type = IIO_TEMP; 568 channels[curr_channel].channel = 8; 569 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 570 BIT(IIO_CHAN_INFO_SCALE) | 571 BIT(IIO_CHAN_INFO_OFFSET); 572 curr_channel++; 573 574 iio_dev->num_channels = curr_channel; 575 iio_dev->channels = channels; 576 577 return 0; 578 } 579 580 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV) 581 { 582 s64 tmp = (s64)vref_mV * 1000000000LL >> 12; 583 584 st->scale_avail[0][0] = 585 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]); 586 st->scale_avail[1][0] = 587 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]); 588 } 589 590 int ad5592r_probe(struct device *dev, const char *name, 591 const struct ad5592r_rw_ops *ops) 592 { 593 struct iio_dev *iio_dev; 594 struct ad5592r_state *st; 595 int ret; 596 597 iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 598 if (!iio_dev) 599 return -ENOMEM; 600 601 st = iio_priv(iio_dev); 602 st->dev = dev; 603 st->ops = ops; 604 st->num_channels = 8; 605 dev_set_drvdata(dev, iio_dev); 606 607 st->reg = devm_regulator_get_optional(dev, "vref"); 608 if (IS_ERR(st->reg)) { 609 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) 610 return PTR_ERR(st->reg); 611 612 st->reg = NULL; 613 } else { 614 ret = regulator_enable(st->reg); 615 if (ret) 616 return ret; 617 } 618 619 iio_dev->name = name; 620 iio_dev->info = &ad5592r_info; 621 iio_dev->modes = INDIO_DIRECT_MODE; 622 623 mutex_init(&st->lock); 624 625 ad5592r_init_scales(st, ad5592r_get_vref(st)); 626 627 ret = ad5592r_reset(st); 628 if (ret) 629 goto error_disable_reg; 630 631 ret = ops->reg_write(st, AD5592R_REG_PD, 632 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); 633 if (ret) 634 goto error_disable_reg; 635 636 ret = ad5592r_alloc_channels(iio_dev); 637 if (ret) 638 goto error_disable_reg; 639 640 ret = ad5592r_set_channel_modes(st); 641 if (ret) 642 goto error_reset_ch_modes; 643 644 ret = iio_device_register(iio_dev); 645 if (ret) 646 goto error_reset_ch_modes; 647 648 ret = ad5592r_gpio_init(st); 649 if (ret) 650 goto error_dev_unregister; 651 652 return 0; 653 654 error_dev_unregister: 655 iio_device_unregister(iio_dev); 656 657 error_reset_ch_modes: 658 ad5592r_reset_channel_modes(st); 659 660 error_disable_reg: 661 if (st->reg) 662 regulator_disable(st->reg); 663 664 return ret; 665 } 666 EXPORT_SYMBOL_GPL(ad5592r_probe); 667 668 int ad5592r_remove(struct device *dev) 669 { 670 struct iio_dev *iio_dev = dev_get_drvdata(dev); 671 struct ad5592r_state *st = iio_priv(iio_dev); 672 673 iio_device_unregister(iio_dev); 674 ad5592r_reset_channel_modes(st); 675 ad5592r_gpio_cleanup(st); 676 677 if (st->reg) 678 regulator_disable(st->reg); 679 680 return 0; 681 } 682 EXPORT_SYMBOL_GPL(ad5592r_remove); 683 684 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>"); 685 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); 686 MODULE_LICENSE("GPL v2"); 687