1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5592R Digital <-> Analog converters driver 4 * 5 * Copyright 2014-2016 Analog Devices Inc. 6 * Author: Paul Cercueil <paul.cercueil@analog.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/iio/iio.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/property.h> 19 20 #include <dt-bindings/iio/adi,ad5592r.h> 21 22 #include "ad5592r-base.h" 23 24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset) 25 { 26 struct ad5592r_state *st = gpiochip_get_data(chip); 27 int ret = 0; 28 u8 val; 29 30 mutex_lock(&st->gpio_lock); 31 32 if (st->gpio_out & BIT(offset)) 33 val = st->gpio_val; 34 else 35 ret = st->ops->gpio_read(st, &val); 36 37 mutex_unlock(&st->gpio_lock); 38 39 if (ret < 0) 40 return ret; 41 42 return !!(val & BIT(offset)); 43 } 44 45 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 46 { 47 struct ad5592r_state *st = gpiochip_get_data(chip); 48 49 mutex_lock(&st->gpio_lock); 50 51 if (value) 52 st->gpio_val |= BIT(offset); 53 else 54 st->gpio_val &= ~BIT(offset); 55 56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 57 58 mutex_unlock(&st->gpio_lock); 59 } 60 61 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 62 { 63 struct ad5592r_state *st = gpiochip_get_data(chip); 64 int ret; 65 66 mutex_lock(&st->gpio_lock); 67 68 st->gpio_out &= ~BIT(offset); 69 st->gpio_in |= BIT(offset); 70 71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 72 if (ret < 0) 73 goto err_unlock; 74 75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 76 77 err_unlock: 78 mutex_unlock(&st->gpio_lock); 79 80 return ret; 81 } 82 83 static int ad5592r_gpio_direction_output(struct gpio_chip *chip, 84 unsigned offset, int value) 85 { 86 struct ad5592r_state *st = gpiochip_get_data(chip); 87 int ret; 88 89 mutex_lock(&st->gpio_lock); 90 91 if (value) 92 st->gpio_val |= BIT(offset); 93 else 94 st->gpio_val &= ~BIT(offset); 95 96 st->gpio_in &= ~BIT(offset); 97 st->gpio_out |= BIT(offset); 98 99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 100 if (ret < 0) 101 goto err_unlock; 102 103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 104 if (ret < 0) 105 goto err_unlock; 106 107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 108 109 err_unlock: 110 mutex_unlock(&st->gpio_lock); 111 112 return ret; 113 } 114 115 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) 116 { 117 struct ad5592r_state *st = gpiochip_get_data(chip); 118 119 if (!(st->gpio_map & BIT(offset))) { 120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n", 121 offset); 122 return -ENODEV; 123 } 124 125 return 0; 126 } 127 128 static int ad5592r_gpio_init(struct ad5592r_state *st) 129 { 130 if (!st->gpio_map) 131 return 0; 132 133 st->gpiochip.label = dev_name(st->dev); 134 st->gpiochip.base = -1; 135 st->gpiochip.ngpio = 8; 136 st->gpiochip.parent = st->dev; 137 st->gpiochip.can_sleep = true; 138 st->gpiochip.direction_input = ad5592r_gpio_direction_input; 139 st->gpiochip.direction_output = ad5592r_gpio_direction_output; 140 st->gpiochip.get = ad5592r_gpio_get; 141 st->gpiochip.set = ad5592r_gpio_set; 142 st->gpiochip.request = ad5592r_gpio_request; 143 st->gpiochip.owner = THIS_MODULE; 144 145 mutex_init(&st->gpio_lock); 146 147 return gpiochip_add_data(&st->gpiochip, st); 148 } 149 150 static void ad5592r_gpio_cleanup(struct ad5592r_state *st) 151 { 152 if (st->gpio_map) 153 gpiochip_remove(&st->gpiochip); 154 } 155 156 static int ad5592r_reset(struct ad5592r_state *st) 157 { 158 struct gpio_desc *gpio; 159 160 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 161 if (IS_ERR(gpio)) 162 return PTR_ERR(gpio); 163 164 if (gpio) { 165 udelay(1); 166 gpiod_set_value(gpio, 1); 167 } else { 168 mutex_lock(&st->lock); 169 /* Writing this magic value resets the device */ 170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); 171 mutex_unlock(&st->lock); 172 } 173 174 udelay(250); 175 176 return 0; 177 } 178 179 static int ad5592r_get_vref(struct ad5592r_state *st) 180 { 181 int ret; 182 183 if (st->reg) { 184 ret = regulator_get_voltage(st->reg); 185 if (ret < 0) 186 return ret; 187 188 return ret / 1000; 189 } else { 190 return 2500; 191 } 192 } 193 194 static int ad5592r_set_channel_modes(struct ad5592r_state *st) 195 { 196 const struct ad5592r_rw_ops *ops = st->ops; 197 int ret; 198 unsigned i; 199 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; 200 u16 read_back; 201 202 for (i = 0; i < st->num_channels; i++) { 203 switch (st->channel_modes[i]) { 204 case CH_MODE_DAC: 205 dac |= BIT(i); 206 break; 207 208 case CH_MODE_ADC: 209 adc |= BIT(i); 210 break; 211 212 case CH_MODE_DAC_AND_ADC: 213 dac |= BIT(i); 214 adc |= BIT(i); 215 break; 216 217 case CH_MODE_GPIO: 218 st->gpio_map |= BIT(i); 219 st->gpio_in |= BIT(i); /* Default to input */ 220 break; 221 222 case CH_MODE_UNUSED: 223 /* fall-through */ 224 default: 225 switch (st->channel_offstate[i]) { 226 case CH_OFFSTATE_OUT_TRISTATE: 227 tristate |= BIT(i); 228 break; 229 230 case CH_OFFSTATE_OUT_LOW: 231 st->gpio_out |= BIT(i); 232 break; 233 234 case CH_OFFSTATE_OUT_HIGH: 235 st->gpio_out |= BIT(i); 236 st->gpio_val |= BIT(i); 237 break; 238 239 case CH_OFFSTATE_PULLDOWN: 240 /* fall-through */ 241 default: 242 pulldown |= BIT(i); 243 break; 244 } 245 } 246 } 247 248 mutex_lock(&st->lock); 249 250 /* Pull down unused pins to GND */ 251 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); 252 if (ret) 253 goto err_unlock; 254 255 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); 256 if (ret) 257 goto err_unlock; 258 259 /* Configure pins that we use */ 260 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); 261 if (ret) 262 goto err_unlock; 263 264 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc); 265 if (ret) 266 goto err_unlock; 267 268 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 269 if (ret) 270 goto err_unlock; 271 272 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 273 if (ret) 274 goto err_unlock; 275 276 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 277 if (ret) 278 goto err_unlock; 279 280 /* Verify that we can read back at least one register */ 281 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); 282 if (!ret && (read_back & 0xff) != adc) 283 ret = -EIO; 284 285 err_unlock: 286 mutex_unlock(&st->lock); 287 return ret; 288 } 289 290 static int ad5592r_reset_channel_modes(struct ad5592r_state *st) 291 { 292 int i; 293 294 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++) 295 st->channel_modes[i] = CH_MODE_UNUSED; 296 297 return ad5592r_set_channel_modes(st); 298 } 299 300 static int ad5592r_write_raw(struct iio_dev *iio_dev, 301 struct iio_chan_spec const *chan, int val, int val2, long mask) 302 { 303 struct ad5592r_state *st = iio_priv(iio_dev); 304 int ret; 305 306 switch (mask) { 307 case IIO_CHAN_INFO_RAW: 308 309 if (val >= (1 << chan->scan_type.realbits) || val < 0) 310 return -EINVAL; 311 312 if (!chan->output) 313 return -EINVAL; 314 315 mutex_lock(&st->lock); 316 ret = st->ops->write_dac(st, chan->channel, val); 317 if (!ret) 318 st->cached_dac[chan->channel] = val; 319 mutex_unlock(&st->lock); 320 return ret; 321 case IIO_CHAN_INFO_SCALE: 322 if (chan->type == IIO_VOLTAGE) { 323 bool gain; 324 325 if (val == st->scale_avail[0][0] && 326 val2 == st->scale_avail[0][1]) 327 gain = false; 328 else if (val == st->scale_avail[1][0] && 329 val2 == st->scale_avail[1][1]) 330 gain = true; 331 else 332 return -EINVAL; 333 334 mutex_lock(&st->lock); 335 336 ret = st->ops->reg_read(st, AD5592R_REG_CTRL, 337 &st->cached_gp_ctrl); 338 if (ret < 0) { 339 mutex_unlock(&st->lock); 340 return ret; 341 } 342 343 if (chan->output) { 344 if (gain) 345 st->cached_gp_ctrl |= 346 AD5592R_REG_CTRL_DAC_RANGE; 347 else 348 st->cached_gp_ctrl &= 349 ~AD5592R_REG_CTRL_DAC_RANGE; 350 } else { 351 if (gain) 352 st->cached_gp_ctrl |= 353 AD5592R_REG_CTRL_ADC_RANGE; 354 else 355 st->cached_gp_ctrl &= 356 ~AD5592R_REG_CTRL_ADC_RANGE; 357 } 358 359 ret = st->ops->reg_write(st, AD5592R_REG_CTRL, 360 st->cached_gp_ctrl); 361 mutex_unlock(&st->lock); 362 363 return ret; 364 } 365 break; 366 default: 367 return -EINVAL; 368 } 369 370 return 0; 371 } 372 373 static int ad5592r_read_raw(struct iio_dev *iio_dev, 374 struct iio_chan_spec const *chan, 375 int *val, int *val2, long m) 376 { 377 struct ad5592r_state *st = iio_priv(iio_dev); 378 u16 read_val; 379 int ret; 380 381 switch (m) { 382 case IIO_CHAN_INFO_RAW: 383 mutex_lock(&st->lock); 384 385 if (!chan->output) { 386 ret = st->ops->read_adc(st, chan->channel, &read_val); 387 if (ret) 388 goto unlock; 389 390 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) { 391 dev_err(st->dev, "Error while reading channel %u\n", 392 chan->channel); 393 ret = -EIO; 394 goto unlock; 395 } 396 397 read_val &= GENMASK(11, 0); 398 399 } else { 400 read_val = st->cached_dac[chan->channel]; 401 } 402 403 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", 404 chan->channel, read_val); 405 406 *val = (int) read_val; 407 ret = IIO_VAL_INT; 408 break; 409 case IIO_CHAN_INFO_SCALE: 410 *val = ad5592r_get_vref(st); 411 412 if (chan->type == IIO_TEMP) { 413 s64 tmp = *val * (3767897513LL / 25LL); 414 *val = div_s64_rem(tmp, 1000000000LL, val2); 415 416 ret = IIO_VAL_INT_PLUS_MICRO; 417 } else { 418 int mult; 419 420 mutex_lock(&st->lock); 421 422 if (chan->output) 423 mult = !!(st->cached_gp_ctrl & 424 AD5592R_REG_CTRL_DAC_RANGE); 425 else 426 mult = !!(st->cached_gp_ctrl & 427 AD5592R_REG_CTRL_ADC_RANGE); 428 429 *val *= ++mult; 430 431 *val2 = chan->scan_type.realbits; 432 ret = IIO_VAL_FRACTIONAL_LOG2; 433 } 434 break; 435 case IIO_CHAN_INFO_OFFSET: 436 ret = ad5592r_get_vref(st); 437 438 mutex_lock(&st->lock); 439 440 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) 441 *val = (-34365 * 25) / ret; 442 else 443 *val = (-75365 * 25) / ret; 444 ret = IIO_VAL_INT; 445 break; 446 default: 447 ret = -EINVAL; 448 } 449 450 unlock: 451 mutex_unlock(&st->lock); 452 return ret; 453 } 454 455 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev, 456 struct iio_chan_spec const *chan, long mask) 457 { 458 switch (mask) { 459 case IIO_CHAN_INFO_SCALE: 460 return IIO_VAL_INT_PLUS_NANO; 461 462 default: 463 return IIO_VAL_INT_PLUS_MICRO; 464 } 465 466 return -EINVAL; 467 } 468 469 static const struct iio_info ad5592r_info = { 470 .read_raw = ad5592r_read_raw, 471 .write_raw = ad5592r_write_raw, 472 .write_raw_get_fmt = ad5592r_write_raw_get_fmt, 473 }; 474 475 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, 476 uintptr_t private, 477 const struct iio_chan_spec *chan, 478 char *buf) 479 { 480 struct ad5592r_state *st = iio_priv(iio_dev); 481 482 return sprintf(buf, "%d.%09u %d.%09u\n", 483 st->scale_avail[0][0], st->scale_avail[0][1], 484 st->scale_avail[1][0], st->scale_avail[1][1]); 485 } 486 487 static struct iio_chan_spec_ext_info ad5592r_ext_info[] = { 488 { 489 .name = "scale_available", 490 .read = ad5592r_show_scale_available, 491 .shared = true, 492 }, 493 {}, 494 }; 495 496 static void ad5592r_setup_channel(struct iio_dev *iio_dev, 497 struct iio_chan_spec *chan, bool output, unsigned id) 498 { 499 chan->type = IIO_VOLTAGE; 500 chan->indexed = 1; 501 chan->output = output; 502 chan->channel = id; 503 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 504 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 505 chan->scan_type.sign = 'u'; 506 chan->scan_type.realbits = 12; 507 chan->scan_type.storagebits = 16; 508 chan->ext_info = ad5592r_ext_info; 509 } 510 511 static int ad5592r_alloc_channels(struct ad5592r_state *st) 512 { 513 unsigned i, curr_channel = 0, 514 num_channels = st->num_channels; 515 struct iio_dev *iio_dev = iio_priv_to_dev(st); 516 struct iio_chan_spec *channels; 517 struct fwnode_handle *child; 518 u32 reg, tmp; 519 int ret; 520 521 device_for_each_child_node(st->dev, child) { 522 ret = fwnode_property_read_u32(child, "reg", ®); 523 if (ret || reg >= ARRAY_SIZE(st->channel_modes)) 524 continue; 525 526 ret = fwnode_property_read_u32(child, "adi,mode", &tmp); 527 if (!ret) 528 st->channel_modes[reg] = tmp; 529 530 fwnode_property_read_u32(child, "adi,off-state", &tmp); 531 if (!ret) 532 st->channel_offstate[reg] = tmp; 533 } 534 535 channels = devm_kcalloc(st->dev, 536 1 + 2 * num_channels, sizeof(*channels), 537 GFP_KERNEL); 538 if (!channels) 539 return -ENOMEM; 540 541 for (i = 0; i < num_channels; i++) { 542 switch (st->channel_modes[i]) { 543 case CH_MODE_DAC: 544 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 545 true, i); 546 curr_channel++; 547 break; 548 549 case CH_MODE_ADC: 550 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 551 false, i); 552 curr_channel++; 553 break; 554 555 case CH_MODE_DAC_AND_ADC: 556 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 557 true, i); 558 curr_channel++; 559 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 560 false, i); 561 curr_channel++; 562 break; 563 564 default: 565 continue; 566 } 567 } 568 569 channels[curr_channel].type = IIO_TEMP; 570 channels[curr_channel].channel = 8; 571 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 572 BIT(IIO_CHAN_INFO_SCALE) | 573 BIT(IIO_CHAN_INFO_OFFSET); 574 curr_channel++; 575 576 iio_dev->num_channels = curr_channel; 577 iio_dev->channels = channels; 578 579 return 0; 580 } 581 582 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV) 583 { 584 s64 tmp = (s64)vref_mV * 1000000000LL >> 12; 585 586 st->scale_avail[0][0] = 587 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]); 588 st->scale_avail[1][0] = 589 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]); 590 } 591 592 int ad5592r_probe(struct device *dev, const char *name, 593 const struct ad5592r_rw_ops *ops) 594 { 595 struct iio_dev *iio_dev; 596 struct ad5592r_state *st; 597 int ret; 598 599 iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 600 if (!iio_dev) 601 return -ENOMEM; 602 603 st = iio_priv(iio_dev); 604 st->dev = dev; 605 st->ops = ops; 606 st->num_channels = 8; 607 dev_set_drvdata(dev, iio_dev); 608 609 st->reg = devm_regulator_get_optional(dev, "vref"); 610 if (IS_ERR(st->reg)) { 611 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) 612 return PTR_ERR(st->reg); 613 614 st->reg = NULL; 615 } else { 616 ret = regulator_enable(st->reg); 617 if (ret) 618 return ret; 619 } 620 621 iio_dev->dev.parent = dev; 622 iio_dev->name = name; 623 iio_dev->info = &ad5592r_info; 624 iio_dev->modes = INDIO_DIRECT_MODE; 625 626 mutex_init(&st->lock); 627 628 ad5592r_init_scales(st, ad5592r_get_vref(st)); 629 630 ret = ad5592r_reset(st); 631 if (ret) 632 goto error_disable_reg; 633 634 ret = ops->reg_write(st, AD5592R_REG_PD, 635 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); 636 if (ret) 637 goto error_disable_reg; 638 639 ret = ad5592r_alloc_channels(st); 640 if (ret) 641 goto error_disable_reg; 642 643 ret = ad5592r_set_channel_modes(st); 644 if (ret) 645 goto error_reset_ch_modes; 646 647 ret = iio_device_register(iio_dev); 648 if (ret) 649 goto error_reset_ch_modes; 650 651 ret = ad5592r_gpio_init(st); 652 if (ret) 653 goto error_dev_unregister; 654 655 return 0; 656 657 error_dev_unregister: 658 iio_device_unregister(iio_dev); 659 660 error_reset_ch_modes: 661 ad5592r_reset_channel_modes(st); 662 663 error_disable_reg: 664 if (st->reg) 665 regulator_disable(st->reg); 666 667 return ret; 668 } 669 EXPORT_SYMBOL_GPL(ad5592r_probe); 670 671 int ad5592r_remove(struct device *dev) 672 { 673 struct iio_dev *iio_dev = dev_get_drvdata(dev); 674 struct ad5592r_state *st = iio_priv(iio_dev); 675 676 iio_device_unregister(iio_dev); 677 ad5592r_reset_channel_modes(st); 678 ad5592r_gpio_cleanup(st); 679 680 if (st->reg) 681 regulator_disable(st->reg); 682 683 return 0; 684 } 685 EXPORT_SYMBOL_GPL(ad5592r_remove); 686 687 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>"); 688 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); 689 MODULE_LICENSE("GPL v2"); 690