1 /* 2 * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, 3 * AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R, 4 * AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616, 5 * LTC2617, LTC2619, LTC2626, LTC2627, LTC2629, LTC2631, LTC2633, LTC2635 6 * Digital to analog converters driver 7 * 8 * Copyright 2011 Analog Devices Inc. 9 * 10 * Licensed under the GPL-2. 11 */ 12 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/spi/spi.h> 18 #include <linux/i2c.h> 19 #include <linux/slab.h> 20 #include <linux/sysfs.h> 21 #include <linux/regulator/consumer.h> 22 #include <asm/unaligned.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 27 #define AD5064_MAX_DAC_CHANNELS 8 28 #define AD5064_MAX_VREFS 4 29 30 #define AD5064_ADDR(x) ((x) << 20) 31 #define AD5064_CMD(x) ((x) << 24) 32 33 #define AD5064_ADDR_ALL_DAC 0xF 34 35 #define AD5064_CMD_WRITE_INPUT_N 0x0 36 #define AD5064_CMD_UPDATE_DAC_N 0x1 37 #define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 38 #define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3 39 #define AD5064_CMD_POWERDOWN_DAC 0x4 40 #define AD5064_CMD_CLEAR 0x5 41 #define AD5064_CMD_LDAC_MASK 0x6 42 #define AD5064_CMD_RESET 0x7 43 #define AD5064_CMD_CONFIG 0x8 44 45 #define AD5064_CMD_RESET_V2 0x5 46 #define AD5064_CMD_CONFIG_V2 0x7 47 48 #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1) 49 #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0) 50 51 #define AD5064_LDAC_PWRDN_NONE 0x0 52 #define AD5064_LDAC_PWRDN_1K 0x1 53 #define AD5064_LDAC_PWRDN_100K 0x2 54 #define AD5064_LDAC_PWRDN_3STATE 0x3 55 56 /** 57 * enum ad5064_regmap_type - Register layout variant 58 * @AD5064_REGMAP_ADI: Old Analog Devices register map layout 59 * @AD5064_REGMAP_ADI2: New Analog Devices register map layout 60 * @AD5064_REGMAP_LTC: LTC register map layout 61 */ 62 enum ad5064_regmap_type { 63 AD5064_REGMAP_ADI, 64 AD5064_REGMAP_ADI2, 65 AD5064_REGMAP_LTC, 66 }; 67 68 /** 69 * struct ad5064_chip_info - chip specific information 70 * @shared_vref: whether the vref supply is shared between channels 71 * @internal_vref: internal reference voltage. 0 if the chip has no 72 internal vref. 73 * @channel: channel specification 74 * @num_channels: number of channels 75 * @regmap_type: register map layout variant 76 */ 77 78 struct ad5064_chip_info { 79 bool shared_vref; 80 unsigned long internal_vref; 81 const struct iio_chan_spec *channels; 82 unsigned int num_channels; 83 enum ad5064_regmap_type regmap_type; 84 }; 85 86 struct ad5064_state; 87 88 typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd, 89 unsigned int addr, unsigned int val); 90 91 /** 92 * struct ad5064_state - driver instance specific data 93 * @dev: the device for this driver instance 94 * @chip_info: chip model specific constants, available modes etc 95 * @vref_reg: vref supply regulators 96 * @pwr_down: whether channel is powered down 97 * @pwr_down_mode: channel's current power down mode 98 * @dac_cache: current DAC raw value (chip does not support readback) 99 * @use_internal_vref: set to true if the internal reference voltage should be 100 * used. 101 * @write: register write callback 102 * @data: i2c/spi transfer buffers 103 */ 104 105 struct ad5064_state { 106 struct device *dev; 107 const struct ad5064_chip_info *chip_info; 108 struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS]; 109 bool pwr_down[AD5064_MAX_DAC_CHANNELS]; 110 u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS]; 111 unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS]; 112 bool use_internal_vref; 113 114 ad5064_write_func write; 115 /* Lock used to maintain consistency between cached and dev state */ 116 struct mutex lock; 117 118 /* 119 * DMA (thus cache coherency maintenance) requires the 120 * transfer buffers to live in their own cache lines. 121 */ 122 union { 123 u8 i2c[3]; 124 __be32 spi; 125 } data ____cacheline_aligned; 126 }; 127 128 enum ad5064_type { 129 ID_AD5024, 130 ID_AD5025, 131 ID_AD5044, 132 ID_AD5045, 133 ID_AD5064, 134 ID_AD5064_1, 135 ID_AD5065, 136 ID_AD5625, 137 ID_AD5625R_1V25, 138 ID_AD5625R_2V5, 139 ID_AD5627, 140 ID_AD5627R_1V25, 141 ID_AD5627R_2V5, 142 ID_AD5628_1, 143 ID_AD5628_2, 144 ID_AD5629_1, 145 ID_AD5629_2, 146 ID_AD5645R_1V25, 147 ID_AD5645R_2V5, 148 ID_AD5647R_1V25, 149 ID_AD5647R_2V5, 150 ID_AD5648_1, 151 ID_AD5648_2, 152 ID_AD5665, 153 ID_AD5665R_1V25, 154 ID_AD5665R_2V5, 155 ID_AD5666_1, 156 ID_AD5666_2, 157 ID_AD5667, 158 ID_AD5667R_1V25, 159 ID_AD5667R_2V5, 160 ID_AD5668_1, 161 ID_AD5668_2, 162 ID_AD5669_1, 163 ID_AD5669_2, 164 ID_LTC2606, 165 ID_LTC2607, 166 ID_LTC2609, 167 ID_LTC2616, 168 ID_LTC2617, 169 ID_LTC2619, 170 ID_LTC2626, 171 ID_LTC2627, 172 ID_LTC2629, 173 ID_LTC2631_L12, 174 ID_LTC2631_H12, 175 ID_LTC2631_L10, 176 ID_LTC2631_H10, 177 ID_LTC2631_L8, 178 ID_LTC2631_H8, 179 ID_LTC2633_L12, 180 ID_LTC2633_H12, 181 ID_LTC2633_L10, 182 ID_LTC2633_H10, 183 ID_LTC2633_L8, 184 ID_LTC2633_H8, 185 ID_LTC2635_L12, 186 ID_LTC2635_H12, 187 ID_LTC2635_L10, 188 ID_LTC2635_H10, 189 ID_LTC2635_L8, 190 ID_LTC2635_H8, 191 }; 192 193 static int ad5064_write(struct ad5064_state *st, unsigned int cmd, 194 unsigned int addr, unsigned int val, unsigned int shift) 195 { 196 val <<= shift; 197 198 return st->write(st, cmd, addr, val); 199 } 200 201 static int ad5064_sync_powerdown_mode(struct ad5064_state *st, 202 const struct iio_chan_spec *chan) 203 { 204 unsigned int val, address; 205 unsigned int shift; 206 int ret; 207 208 if (st->chip_info->regmap_type == AD5064_REGMAP_LTC) { 209 val = 0; 210 address = chan->address; 211 } else { 212 if (st->chip_info->regmap_type == AD5064_REGMAP_ADI2) 213 shift = 4; 214 else 215 shift = 8; 216 217 val = (0x1 << chan->address); 218 address = 0; 219 220 if (st->pwr_down[chan->channel]) 221 val |= st->pwr_down_mode[chan->channel] << shift; 222 } 223 224 ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0); 225 226 return ret; 227 } 228 229 static const char * const ad5064_powerdown_modes[] = { 230 "1kohm_to_gnd", 231 "100kohm_to_gnd", 232 "three_state", 233 }; 234 235 static const char * const ltc2617_powerdown_modes[] = { 236 "90kohm_to_gnd", 237 }; 238 239 static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev, 240 const struct iio_chan_spec *chan) 241 { 242 struct ad5064_state *st = iio_priv(indio_dev); 243 244 return st->pwr_down_mode[chan->channel] - 1; 245 } 246 247 static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev, 248 const struct iio_chan_spec *chan, unsigned int mode) 249 { 250 struct ad5064_state *st = iio_priv(indio_dev); 251 int ret; 252 253 mutex_lock(&st->lock); 254 st->pwr_down_mode[chan->channel] = mode + 1; 255 256 ret = ad5064_sync_powerdown_mode(st, chan); 257 mutex_unlock(&st->lock); 258 259 return ret; 260 } 261 262 static const struct iio_enum ad5064_powerdown_mode_enum = { 263 .items = ad5064_powerdown_modes, 264 .num_items = ARRAY_SIZE(ad5064_powerdown_modes), 265 .get = ad5064_get_powerdown_mode, 266 .set = ad5064_set_powerdown_mode, 267 }; 268 269 static const struct iio_enum ltc2617_powerdown_mode_enum = { 270 .items = ltc2617_powerdown_modes, 271 .num_items = ARRAY_SIZE(ltc2617_powerdown_modes), 272 .get = ad5064_get_powerdown_mode, 273 .set = ad5064_set_powerdown_mode, 274 }; 275 276 static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev, 277 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 278 { 279 struct ad5064_state *st = iio_priv(indio_dev); 280 281 return sprintf(buf, "%d\n", st->pwr_down[chan->channel]); 282 } 283 284 static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev, 285 uintptr_t private, const struct iio_chan_spec *chan, const char *buf, 286 size_t len) 287 { 288 struct ad5064_state *st = iio_priv(indio_dev); 289 bool pwr_down; 290 int ret; 291 292 ret = strtobool(buf, &pwr_down); 293 if (ret) 294 return ret; 295 296 mutex_lock(&st->lock); 297 st->pwr_down[chan->channel] = pwr_down; 298 299 ret = ad5064_sync_powerdown_mode(st, chan); 300 mutex_unlock(&st->lock); 301 return ret ? ret : len; 302 } 303 304 static int ad5064_get_vref(struct ad5064_state *st, 305 struct iio_chan_spec const *chan) 306 { 307 unsigned int i; 308 309 if (st->use_internal_vref) 310 return st->chip_info->internal_vref; 311 312 i = st->chip_info->shared_vref ? 0 : chan->channel; 313 return regulator_get_voltage(st->vref_reg[i].consumer); 314 } 315 316 static int ad5064_read_raw(struct iio_dev *indio_dev, 317 struct iio_chan_spec const *chan, 318 int *val, 319 int *val2, 320 long m) 321 { 322 struct ad5064_state *st = iio_priv(indio_dev); 323 int scale_uv; 324 325 switch (m) { 326 case IIO_CHAN_INFO_RAW: 327 *val = st->dac_cache[chan->channel]; 328 return IIO_VAL_INT; 329 case IIO_CHAN_INFO_SCALE: 330 scale_uv = ad5064_get_vref(st, chan); 331 if (scale_uv < 0) 332 return scale_uv; 333 334 *val = scale_uv / 1000; 335 *val2 = chan->scan_type.realbits; 336 return IIO_VAL_FRACTIONAL_LOG2; 337 default: 338 break; 339 } 340 return -EINVAL; 341 } 342 343 static int ad5064_write_raw(struct iio_dev *indio_dev, 344 struct iio_chan_spec const *chan, int val, int val2, long mask) 345 { 346 struct ad5064_state *st = iio_priv(indio_dev); 347 int ret; 348 349 switch (mask) { 350 case IIO_CHAN_INFO_RAW: 351 if (val >= (1 << chan->scan_type.realbits) || val < 0) 352 return -EINVAL; 353 354 mutex_lock(&st->lock); 355 ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N, 356 chan->address, val, chan->scan_type.shift); 357 if (ret == 0) 358 st->dac_cache[chan->channel] = val; 359 mutex_unlock(&st->lock); 360 break; 361 default: 362 ret = -EINVAL; 363 } 364 365 return ret; 366 } 367 368 static const struct iio_info ad5064_info = { 369 .read_raw = ad5064_read_raw, 370 .write_raw = ad5064_write_raw, 371 }; 372 373 static const struct iio_chan_spec_ext_info ad5064_ext_info[] = { 374 { 375 .name = "powerdown", 376 .read = ad5064_read_dac_powerdown, 377 .write = ad5064_write_dac_powerdown, 378 .shared = IIO_SEPARATE, 379 }, 380 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5064_powerdown_mode_enum), 381 IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum), 382 { }, 383 }; 384 385 static const struct iio_chan_spec_ext_info ltc2617_ext_info[] = { 386 { 387 .name = "powerdown", 388 .read = ad5064_read_dac_powerdown, 389 .write = ad5064_write_dac_powerdown, 390 .shared = IIO_SEPARATE, 391 }, 392 IIO_ENUM("powerdown_mode", IIO_SEPARATE, <c2617_powerdown_mode_enum), 393 IIO_ENUM_AVAILABLE("powerdown_mode", <c2617_powerdown_mode_enum), 394 { }, 395 }; 396 397 #define AD5064_CHANNEL(chan, addr, bits, _shift, _ext_info) { \ 398 .type = IIO_VOLTAGE, \ 399 .indexed = 1, \ 400 .output = 1, \ 401 .channel = (chan), \ 402 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 403 BIT(IIO_CHAN_INFO_SCALE), \ 404 .address = addr, \ 405 .scan_type = { \ 406 .sign = 'u', \ 407 .realbits = (bits), \ 408 .storagebits = 16, \ 409 .shift = (_shift), \ 410 }, \ 411 .ext_info = (_ext_info), \ 412 } 413 414 #define DECLARE_AD5064_CHANNELS(name, bits, shift, ext_info) \ 415 const struct iio_chan_spec name[] = { \ 416 AD5064_CHANNEL(0, 0, bits, shift, ext_info), \ 417 AD5064_CHANNEL(1, 1, bits, shift, ext_info), \ 418 AD5064_CHANNEL(2, 2, bits, shift, ext_info), \ 419 AD5064_CHANNEL(3, 3, bits, shift, ext_info), \ 420 AD5064_CHANNEL(4, 4, bits, shift, ext_info), \ 421 AD5064_CHANNEL(5, 5, bits, shift, ext_info), \ 422 AD5064_CHANNEL(6, 6, bits, shift, ext_info), \ 423 AD5064_CHANNEL(7, 7, bits, shift, ext_info), \ 424 } 425 426 #define DECLARE_AD5065_CHANNELS(name, bits, shift, ext_info) \ 427 const struct iio_chan_spec name[] = { \ 428 AD5064_CHANNEL(0, 0, bits, shift, ext_info), \ 429 AD5064_CHANNEL(1, 3, bits, shift, ext_info), \ 430 } 431 432 static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8, ad5064_ext_info); 433 static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6, ad5064_ext_info); 434 static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4, ad5064_ext_info); 435 436 static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8, ad5064_ext_info); 437 static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6, ad5064_ext_info); 438 static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4, ad5064_ext_info); 439 440 static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4, ad5064_ext_info); 441 static DECLARE_AD5064_CHANNELS(ad5645_channels, 14, 2, ad5064_ext_info); 442 static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info); 443 444 static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info); 445 static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info); 446 static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info); 447 #define ltc2631_12_channels ltc2627_channels 448 static DECLARE_AD5064_CHANNELS(ltc2631_10_channels, 10, 6, ltc2617_ext_info); 449 static DECLARE_AD5064_CHANNELS(ltc2631_8_channels, 8, 8, ltc2617_ext_info); 450 451 #define LTC2631_INFO(vref, pchannels, nchannels) \ 452 { \ 453 .shared_vref = true, \ 454 .internal_vref = vref, \ 455 .channels = pchannels, \ 456 .num_channels = nchannels, \ 457 .regmap_type = AD5064_REGMAP_LTC, \ 458 } 459 460 461 static const struct ad5064_chip_info ad5064_chip_info_tbl[] = { 462 [ID_AD5024] = { 463 .shared_vref = false, 464 .channels = ad5024_channels, 465 .num_channels = 4, 466 .regmap_type = AD5064_REGMAP_ADI, 467 }, 468 [ID_AD5025] = { 469 .shared_vref = false, 470 .channels = ad5025_channels, 471 .num_channels = 2, 472 .regmap_type = AD5064_REGMAP_ADI, 473 }, 474 [ID_AD5044] = { 475 .shared_vref = false, 476 .channels = ad5044_channels, 477 .num_channels = 4, 478 .regmap_type = AD5064_REGMAP_ADI, 479 }, 480 [ID_AD5045] = { 481 .shared_vref = false, 482 .channels = ad5045_channels, 483 .num_channels = 2, 484 .regmap_type = AD5064_REGMAP_ADI, 485 }, 486 [ID_AD5064] = { 487 .shared_vref = false, 488 .channels = ad5064_channels, 489 .num_channels = 4, 490 .regmap_type = AD5064_REGMAP_ADI, 491 }, 492 [ID_AD5064_1] = { 493 .shared_vref = true, 494 .channels = ad5064_channels, 495 .num_channels = 4, 496 .regmap_type = AD5064_REGMAP_ADI, 497 }, 498 [ID_AD5065] = { 499 .shared_vref = false, 500 .channels = ad5065_channels, 501 .num_channels = 2, 502 .regmap_type = AD5064_REGMAP_ADI, 503 }, 504 [ID_AD5625] = { 505 .shared_vref = true, 506 .channels = ad5629_channels, 507 .num_channels = 4, 508 .regmap_type = AD5064_REGMAP_ADI2 509 }, 510 [ID_AD5625R_1V25] = { 511 .shared_vref = true, 512 .internal_vref = 1250000, 513 .channels = ad5629_channels, 514 .num_channels = 4, 515 .regmap_type = AD5064_REGMAP_ADI2 516 }, 517 [ID_AD5625R_2V5] = { 518 .shared_vref = true, 519 .internal_vref = 2500000, 520 .channels = ad5629_channels, 521 .num_channels = 4, 522 .regmap_type = AD5064_REGMAP_ADI2 523 }, 524 [ID_AD5627] = { 525 .shared_vref = true, 526 .channels = ad5629_channels, 527 .num_channels = 2, 528 .regmap_type = AD5064_REGMAP_ADI2 529 }, 530 [ID_AD5627R_1V25] = { 531 .shared_vref = true, 532 .internal_vref = 1250000, 533 .channels = ad5629_channels, 534 .num_channels = 2, 535 .regmap_type = AD5064_REGMAP_ADI2 536 }, 537 [ID_AD5627R_2V5] = { 538 .shared_vref = true, 539 .internal_vref = 2500000, 540 .channels = ad5629_channels, 541 .num_channels = 2, 542 .regmap_type = AD5064_REGMAP_ADI2 543 }, 544 [ID_AD5628_1] = { 545 .shared_vref = true, 546 .internal_vref = 2500000, 547 .channels = ad5024_channels, 548 .num_channels = 8, 549 .regmap_type = AD5064_REGMAP_ADI, 550 }, 551 [ID_AD5628_2] = { 552 .shared_vref = true, 553 .internal_vref = 5000000, 554 .channels = ad5024_channels, 555 .num_channels = 8, 556 .regmap_type = AD5064_REGMAP_ADI, 557 }, 558 [ID_AD5629_1] = { 559 .shared_vref = true, 560 .internal_vref = 2500000, 561 .channels = ad5629_channels, 562 .num_channels = 8, 563 .regmap_type = AD5064_REGMAP_ADI, 564 }, 565 [ID_AD5629_2] = { 566 .shared_vref = true, 567 .internal_vref = 5000000, 568 .channels = ad5629_channels, 569 .num_channels = 8, 570 .regmap_type = AD5064_REGMAP_ADI, 571 }, 572 [ID_AD5645R_1V25] = { 573 .shared_vref = true, 574 .internal_vref = 1250000, 575 .channels = ad5645_channels, 576 .num_channels = 4, 577 .regmap_type = AD5064_REGMAP_ADI2 578 }, 579 [ID_AD5645R_2V5] = { 580 .shared_vref = true, 581 .internal_vref = 2500000, 582 .channels = ad5645_channels, 583 .num_channels = 4, 584 .regmap_type = AD5064_REGMAP_ADI2 585 }, 586 [ID_AD5647R_1V25] = { 587 .shared_vref = true, 588 .internal_vref = 1250000, 589 .channels = ad5645_channels, 590 .num_channels = 2, 591 .regmap_type = AD5064_REGMAP_ADI2 592 }, 593 [ID_AD5647R_2V5] = { 594 .shared_vref = true, 595 .internal_vref = 2500000, 596 .channels = ad5645_channels, 597 .num_channels = 2, 598 .regmap_type = AD5064_REGMAP_ADI2 599 }, 600 [ID_AD5648_1] = { 601 .shared_vref = true, 602 .internal_vref = 2500000, 603 .channels = ad5044_channels, 604 .num_channels = 8, 605 .regmap_type = AD5064_REGMAP_ADI, 606 }, 607 [ID_AD5648_2] = { 608 .shared_vref = true, 609 .internal_vref = 5000000, 610 .channels = ad5044_channels, 611 .num_channels = 8, 612 .regmap_type = AD5064_REGMAP_ADI, 613 }, 614 [ID_AD5665] = { 615 .shared_vref = true, 616 .channels = ad5669_channels, 617 .num_channels = 4, 618 .regmap_type = AD5064_REGMAP_ADI2 619 }, 620 [ID_AD5665R_1V25] = { 621 .shared_vref = true, 622 .internal_vref = 1250000, 623 .channels = ad5669_channels, 624 .num_channels = 4, 625 .regmap_type = AD5064_REGMAP_ADI2 626 }, 627 [ID_AD5665R_2V5] = { 628 .shared_vref = true, 629 .internal_vref = 2500000, 630 .channels = ad5669_channels, 631 .num_channels = 4, 632 .regmap_type = AD5064_REGMAP_ADI2 633 }, 634 [ID_AD5666_1] = { 635 .shared_vref = true, 636 .internal_vref = 2500000, 637 .channels = ad5064_channels, 638 .num_channels = 4, 639 .regmap_type = AD5064_REGMAP_ADI, 640 }, 641 [ID_AD5666_2] = { 642 .shared_vref = true, 643 .internal_vref = 5000000, 644 .channels = ad5064_channels, 645 .num_channels = 4, 646 .regmap_type = AD5064_REGMAP_ADI, 647 }, 648 [ID_AD5667] = { 649 .shared_vref = true, 650 .channels = ad5669_channels, 651 .num_channels = 2, 652 .regmap_type = AD5064_REGMAP_ADI2 653 }, 654 [ID_AD5667R_1V25] = { 655 .shared_vref = true, 656 .internal_vref = 1250000, 657 .channels = ad5669_channels, 658 .num_channels = 2, 659 .regmap_type = AD5064_REGMAP_ADI2 660 }, 661 [ID_AD5667R_2V5] = { 662 .shared_vref = true, 663 .internal_vref = 2500000, 664 .channels = ad5669_channels, 665 .num_channels = 2, 666 .regmap_type = AD5064_REGMAP_ADI2 667 }, 668 [ID_AD5668_1] = { 669 .shared_vref = true, 670 .internal_vref = 2500000, 671 .channels = ad5064_channels, 672 .num_channels = 8, 673 .regmap_type = AD5064_REGMAP_ADI, 674 }, 675 [ID_AD5668_2] = { 676 .shared_vref = true, 677 .internal_vref = 5000000, 678 .channels = ad5064_channels, 679 .num_channels = 8, 680 .regmap_type = AD5064_REGMAP_ADI, 681 }, 682 [ID_AD5669_1] = { 683 .shared_vref = true, 684 .internal_vref = 2500000, 685 .channels = ad5669_channels, 686 .num_channels = 8, 687 .regmap_type = AD5064_REGMAP_ADI, 688 }, 689 [ID_AD5669_2] = { 690 .shared_vref = true, 691 .internal_vref = 5000000, 692 .channels = ad5669_channels, 693 .num_channels = 8, 694 .regmap_type = AD5064_REGMAP_ADI, 695 }, 696 [ID_LTC2606] = { 697 .shared_vref = true, 698 .internal_vref = 0, 699 .channels = ltc2607_channels, 700 .num_channels = 1, 701 .regmap_type = AD5064_REGMAP_LTC, 702 }, 703 [ID_LTC2607] = { 704 .shared_vref = true, 705 .internal_vref = 0, 706 .channels = ltc2607_channels, 707 .num_channels = 2, 708 .regmap_type = AD5064_REGMAP_LTC, 709 }, 710 [ID_LTC2609] = { 711 .shared_vref = false, 712 .internal_vref = 0, 713 .channels = ltc2607_channels, 714 .num_channels = 4, 715 .regmap_type = AD5064_REGMAP_LTC, 716 }, 717 [ID_LTC2616] = { 718 .shared_vref = true, 719 .internal_vref = 0, 720 .channels = ltc2617_channels, 721 .num_channels = 1, 722 .regmap_type = AD5064_REGMAP_LTC, 723 }, 724 [ID_LTC2617] = { 725 .shared_vref = true, 726 .internal_vref = 0, 727 .channels = ltc2617_channels, 728 .num_channels = 2, 729 .regmap_type = AD5064_REGMAP_LTC, 730 }, 731 [ID_LTC2619] = { 732 .shared_vref = false, 733 .internal_vref = 0, 734 .channels = ltc2617_channels, 735 .num_channels = 4, 736 .regmap_type = AD5064_REGMAP_LTC, 737 }, 738 [ID_LTC2626] = { 739 .shared_vref = true, 740 .internal_vref = 0, 741 .channels = ltc2627_channels, 742 .num_channels = 1, 743 .regmap_type = AD5064_REGMAP_LTC, 744 }, 745 [ID_LTC2627] = { 746 .shared_vref = true, 747 .internal_vref = 0, 748 .channels = ltc2627_channels, 749 .num_channels = 2, 750 .regmap_type = AD5064_REGMAP_LTC, 751 }, 752 [ID_LTC2629] = { 753 .shared_vref = false, 754 .internal_vref = 0, 755 .channels = ltc2627_channels, 756 .num_channels = 4, 757 .regmap_type = AD5064_REGMAP_LTC, 758 }, 759 [ID_LTC2631_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 1), 760 [ID_LTC2631_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 1), 761 [ID_LTC2631_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 1), 762 [ID_LTC2631_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 1), 763 [ID_LTC2631_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 1), 764 [ID_LTC2631_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 1), 765 [ID_LTC2633_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 2), 766 [ID_LTC2633_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 2), 767 [ID_LTC2633_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 2), 768 [ID_LTC2633_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 2), 769 [ID_LTC2633_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 2), 770 [ID_LTC2633_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 2), 771 [ID_LTC2635_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 4), 772 [ID_LTC2635_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 4), 773 [ID_LTC2635_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 4), 774 [ID_LTC2635_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 4), 775 [ID_LTC2635_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 4), 776 [ID_LTC2635_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 4), 777 }; 778 779 static inline unsigned int ad5064_num_vref(struct ad5064_state *st) 780 { 781 return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels; 782 } 783 784 static const char * const ad5064_vref_names[] = { 785 "vrefA", 786 "vrefB", 787 "vrefC", 788 "vrefD", 789 }; 790 791 static const char * const ad5064_vref_name(struct ad5064_state *st, 792 unsigned int vref) 793 { 794 return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref]; 795 } 796 797 static int ad5064_set_config(struct ad5064_state *st, unsigned int val) 798 { 799 unsigned int cmd; 800 801 switch (st->chip_info->regmap_type) { 802 case AD5064_REGMAP_ADI2: 803 cmd = AD5064_CMD_CONFIG_V2; 804 break; 805 default: 806 cmd = AD5064_CMD_CONFIG; 807 break; 808 } 809 810 return ad5064_write(st, cmd, 0, val, 0); 811 } 812 813 static int ad5064_request_vref(struct ad5064_state *st, struct device *dev) 814 { 815 unsigned int i; 816 int ret; 817 818 for (i = 0; i < ad5064_num_vref(st); ++i) 819 st->vref_reg[i].supply = ad5064_vref_name(st, i); 820 821 if (!st->chip_info->internal_vref) 822 return devm_regulator_bulk_get(dev, ad5064_num_vref(st), 823 st->vref_reg); 824 825 /* 826 * This assumes that when the regulator has an internal VREF 827 * there is only one external VREF connection, which is 828 * currently the case for all supported devices. 829 */ 830 st->vref_reg[0].consumer = devm_regulator_get_optional(dev, "vref"); 831 if (!IS_ERR(st->vref_reg[0].consumer)) 832 return 0; 833 834 ret = PTR_ERR(st->vref_reg[0].consumer); 835 if (ret != -ENODEV) 836 return ret; 837 838 /* If no external regulator was supplied use the internal VREF */ 839 st->use_internal_vref = true; 840 ret = ad5064_set_config(st, AD5064_CONFIG_INT_VREF_ENABLE); 841 if (ret) 842 dev_err(dev, "Failed to enable internal vref: %d\n", ret); 843 844 return ret; 845 } 846 847 static int ad5064_probe(struct device *dev, enum ad5064_type type, 848 const char *name, ad5064_write_func write) 849 { 850 struct iio_dev *indio_dev; 851 struct ad5064_state *st; 852 unsigned int midscale; 853 unsigned int i; 854 int ret; 855 856 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 857 if (indio_dev == NULL) 858 return -ENOMEM; 859 860 st = iio_priv(indio_dev); 861 mutex_init(&st->lock); 862 dev_set_drvdata(dev, indio_dev); 863 864 st->chip_info = &ad5064_chip_info_tbl[type]; 865 st->dev = dev; 866 st->write = write; 867 868 ret = ad5064_request_vref(st, dev); 869 if (ret) 870 return ret; 871 872 if (!st->use_internal_vref) { 873 ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg); 874 if (ret) 875 return ret; 876 } 877 878 indio_dev->dev.parent = dev; 879 indio_dev->name = name; 880 indio_dev->info = &ad5064_info; 881 indio_dev->modes = INDIO_DIRECT_MODE; 882 indio_dev->channels = st->chip_info->channels; 883 indio_dev->num_channels = st->chip_info->num_channels; 884 885 midscale = (1 << indio_dev->channels[0].scan_type.realbits) / 2; 886 887 for (i = 0; i < st->chip_info->num_channels; ++i) { 888 st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K; 889 st->dac_cache[i] = midscale; 890 } 891 892 ret = iio_device_register(indio_dev); 893 if (ret) 894 goto error_disable_reg; 895 896 return 0; 897 898 error_disable_reg: 899 if (!st->use_internal_vref) 900 regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg); 901 902 return ret; 903 } 904 905 static int ad5064_remove(struct device *dev) 906 { 907 struct iio_dev *indio_dev = dev_get_drvdata(dev); 908 struct ad5064_state *st = iio_priv(indio_dev); 909 910 iio_device_unregister(indio_dev); 911 912 if (!st->use_internal_vref) 913 regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg); 914 915 return 0; 916 } 917 918 #if IS_ENABLED(CONFIG_SPI_MASTER) 919 920 static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd, 921 unsigned int addr, unsigned int val) 922 { 923 struct spi_device *spi = to_spi_device(st->dev); 924 925 st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val); 926 return spi_write(spi, &st->data.spi, sizeof(st->data.spi)); 927 } 928 929 static int ad5064_spi_probe(struct spi_device *spi) 930 { 931 const struct spi_device_id *id = spi_get_device_id(spi); 932 933 return ad5064_probe(&spi->dev, id->driver_data, id->name, 934 ad5064_spi_write); 935 } 936 937 static int ad5064_spi_remove(struct spi_device *spi) 938 { 939 return ad5064_remove(&spi->dev); 940 } 941 942 static const struct spi_device_id ad5064_spi_ids[] = { 943 {"ad5024", ID_AD5024}, 944 {"ad5025", ID_AD5025}, 945 {"ad5044", ID_AD5044}, 946 {"ad5045", ID_AD5045}, 947 {"ad5064", ID_AD5064}, 948 {"ad5064-1", ID_AD5064_1}, 949 {"ad5065", ID_AD5065}, 950 {"ad5628-1", ID_AD5628_1}, 951 {"ad5628-2", ID_AD5628_2}, 952 {"ad5648-1", ID_AD5648_1}, 953 {"ad5648-2", ID_AD5648_2}, 954 {"ad5666-1", ID_AD5666_1}, 955 {"ad5666-2", ID_AD5666_2}, 956 {"ad5668-1", ID_AD5668_1}, 957 {"ad5668-2", ID_AD5668_2}, 958 {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */ 959 {} 960 }; 961 MODULE_DEVICE_TABLE(spi, ad5064_spi_ids); 962 963 static struct spi_driver ad5064_spi_driver = { 964 .driver = { 965 .name = "ad5064", 966 }, 967 .probe = ad5064_spi_probe, 968 .remove = ad5064_spi_remove, 969 .id_table = ad5064_spi_ids, 970 }; 971 972 static int __init ad5064_spi_register_driver(void) 973 { 974 return spi_register_driver(&ad5064_spi_driver); 975 } 976 977 static void ad5064_spi_unregister_driver(void) 978 { 979 spi_unregister_driver(&ad5064_spi_driver); 980 } 981 982 #else 983 984 static inline int ad5064_spi_register_driver(void) { return 0; } 985 static inline void ad5064_spi_unregister_driver(void) { } 986 987 #endif 988 989 #if IS_ENABLED(CONFIG_I2C) 990 991 static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd, 992 unsigned int addr, unsigned int val) 993 { 994 struct i2c_client *i2c = to_i2c_client(st->dev); 995 unsigned int cmd_shift; 996 int ret; 997 998 switch (st->chip_info->regmap_type) { 999 case AD5064_REGMAP_ADI2: 1000 cmd_shift = 3; 1001 break; 1002 default: 1003 cmd_shift = 4; 1004 break; 1005 } 1006 1007 st->data.i2c[0] = (cmd << cmd_shift) | addr; 1008 put_unaligned_be16(val, &st->data.i2c[1]); 1009 1010 ret = i2c_master_send(i2c, st->data.i2c, 3); 1011 if (ret < 0) 1012 return ret; 1013 1014 return 0; 1015 } 1016 1017 static int ad5064_i2c_probe(struct i2c_client *i2c, 1018 const struct i2c_device_id *id) 1019 { 1020 return ad5064_probe(&i2c->dev, id->driver_data, id->name, 1021 ad5064_i2c_write); 1022 } 1023 1024 static int ad5064_i2c_remove(struct i2c_client *i2c) 1025 { 1026 return ad5064_remove(&i2c->dev); 1027 } 1028 1029 static const struct i2c_device_id ad5064_i2c_ids[] = { 1030 {"ad5625", ID_AD5625 }, 1031 {"ad5625r-1v25", ID_AD5625R_1V25 }, 1032 {"ad5625r-2v5", ID_AD5625R_2V5 }, 1033 {"ad5627", ID_AD5627 }, 1034 {"ad5627r-1v25", ID_AD5627R_1V25 }, 1035 {"ad5627r-2v5", ID_AD5627R_2V5 }, 1036 {"ad5629-1", ID_AD5629_1}, 1037 {"ad5629-2", ID_AD5629_2}, 1038 {"ad5629-3", ID_AD5629_2}, /* similar enough to ad5629-2 */ 1039 {"ad5645r-1v25", ID_AD5645R_1V25 }, 1040 {"ad5645r-2v5", ID_AD5645R_2V5 }, 1041 {"ad5665", ID_AD5665 }, 1042 {"ad5665r-1v25", ID_AD5665R_1V25 }, 1043 {"ad5665r-2v5", ID_AD5665R_2V5 }, 1044 {"ad5667", ID_AD5667 }, 1045 {"ad5667r-1v25", ID_AD5667R_1V25 }, 1046 {"ad5667r-2v5", ID_AD5667R_2V5 }, 1047 {"ad5669-1", ID_AD5669_1}, 1048 {"ad5669-2", ID_AD5669_2}, 1049 {"ad5669-3", ID_AD5669_2}, /* similar enough to ad5669-2 */ 1050 {"ltc2606", ID_LTC2606}, 1051 {"ltc2607", ID_LTC2607}, 1052 {"ltc2609", ID_LTC2609}, 1053 {"ltc2616", ID_LTC2616}, 1054 {"ltc2617", ID_LTC2617}, 1055 {"ltc2619", ID_LTC2619}, 1056 {"ltc2626", ID_LTC2626}, 1057 {"ltc2627", ID_LTC2627}, 1058 {"ltc2629", ID_LTC2629}, 1059 {"ltc2631-l12", ID_LTC2631_L12}, 1060 {"ltc2631-h12", ID_LTC2631_H12}, 1061 {"ltc2631-l10", ID_LTC2631_L10}, 1062 {"ltc2631-h10", ID_LTC2631_H10}, 1063 {"ltc2631-l8", ID_LTC2631_L8}, 1064 {"ltc2631-h8", ID_LTC2631_H8}, 1065 {"ltc2633-l12", ID_LTC2633_L12}, 1066 {"ltc2633-h12", ID_LTC2633_H12}, 1067 {"ltc2633-l10", ID_LTC2633_L10}, 1068 {"ltc2633-h10", ID_LTC2633_H10}, 1069 {"ltc2633-l8", ID_LTC2633_L8}, 1070 {"ltc2633-h8", ID_LTC2633_H8}, 1071 {"ltc2635-l12", ID_LTC2635_L12}, 1072 {"ltc2635-h12", ID_LTC2635_H12}, 1073 {"ltc2635-l10", ID_LTC2635_L10}, 1074 {"ltc2635-h10", ID_LTC2635_H10}, 1075 {"ltc2635-l8", ID_LTC2635_L8}, 1076 {"ltc2635-h8", ID_LTC2635_H8}, 1077 {} 1078 }; 1079 MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids); 1080 1081 static struct i2c_driver ad5064_i2c_driver = { 1082 .driver = { 1083 .name = "ad5064", 1084 }, 1085 .probe = ad5064_i2c_probe, 1086 .remove = ad5064_i2c_remove, 1087 .id_table = ad5064_i2c_ids, 1088 }; 1089 1090 static int __init ad5064_i2c_register_driver(void) 1091 { 1092 return i2c_add_driver(&ad5064_i2c_driver); 1093 } 1094 1095 static void __exit ad5064_i2c_unregister_driver(void) 1096 { 1097 i2c_del_driver(&ad5064_i2c_driver); 1098 } 1099 1100 #else 1101 1102 static inline int ad5064_i2c_register_driver(void) { return 0; } 1103 static inline void ad5064_i2c_unregister_driver(void) { } 1104 1105 #endif 1106 1107 static int __init ad5064_init(void) 1108 { 1109 int ret; 1110 1111 ret = ad5064_spi_register_driver(); 1112 if (ret) 1113 return ret; 1114 1115 ret = ad5064_i2c_register_driver(); 1116 if (ret) { 1117 ad5064_spi_unregister_driver(); 1118 return ret; 1119 } 1120 1121 return 0; 1122 } 1123 module_init(ad5064_init); 1124 1125 static void __exit ad5064_exit(void) 1126 { 1127 ad5064_i2c_unregister_driver(); 1128 ad5064_spi_unregister_driver(); 1129 } 1130 module_exit(ad5064_exit); 1131 1132 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1133 MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs"); 1134 MODULE_LICENSE("GPL v2"); 1135