1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7746 capacitive sensor driver supporting AD7745, AD7746 and AD7747 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/stat.h> 17 #include <linux/sysfs.h> 18 19 #include <asm/unaligned.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 24 /* AD7746 Register Definition */ 25 26 #define AD7746_REG_STATUS 0 27 #define AD7746_REG_CAP_DATA_HIGH 1 28 #define AD7746_REG_VT_DATA_HIGH 4 29 #define AD7746_REG_CAP_SETUP 7 30 #define AD7746_REG_VT_SETUP 8 31 #define AD7746_REG_EXC_SETUP 9 32 #define AD7746_REG_CFG 10 33 #define AD7746_REG_CAPDACA 11 34 #define AD7746_REG_CAPDACB 12 35 #define AD7746_REG_CAP_OFFH 13 36 #define AD7746_REG_CAP_GAINH 15 37 #define AD7746_REG_VOLT_GAINH 17 38 39 /* Status Register Bit Designations (AD7746_REG_STATUS) */ 40 #define AD7746_STATUS_EXCERR BIT(3) 41 #define AD7746_STATUS_RDY BIT(2) 42 #define AD7746_STATUS_RDYVT BIT(1) 43 #define AD7746_STATUS_RDYCAP BIT(0) 44 45 /* Capacitive Channel Setup Register Bit Designations (AD7746_REG_CAP_SETUP) */ 46 #define AD7746_CAPSETUP_CAPEN BIT(7) 47 #define AD7746_CAPSETUP_CIN2 BIT(6) /* AD7746 only */ 48 #define AD7746_CAPSETUP_CAPDIFF BIT(5) 49 #define AD7746_CAPSETUP_CACHOP BIT(0) 50 51 /* Voltage/Temperature Setup Register Bit Designations (AD7746_REG_VT_SETUP) */ 52 #define AD7746_VTSETUP_VTEN BIT(7) 53 #define AD7746_VTSETUP_VTMD_MASK GENMASK(6, 5) 54 #define AD7746_VTSETUP_VTMD_INT_TEMP 0 55 #define AD7746_VTSETUP_VTMD_EXT_TEMP 1 56 #define AD7746_VTSETUP_VTMD_VDD_MON 2 57 #define AD7746_VTSETUP_VTMD_EXT_VIN 3 58 #define AD7746_VTSETUP_EXTREF BIT(4) 59 #define AD7746_VTSETUP_VTSHORT BIT(1) 60 #define AD7746_VTSETUP_VTCHOP BIT(0) 61 62 /* Excitation Setup Register Bit Designations (AD7746_REG_EXC_SETUP) */ 63 #define AD7746_EXCSETUP_CLKCTRL BIT(7) 64 #define AD7746_EXCSETUP_EXCON BIT(6) 65 #define AD7746_EXCSETUP_EXCB BIT(5) 66 #define AD7746_EXCSETUP_NEXCB BIT(4) 67 #define AD7746_EXCSETUP_EXCA BIT(3) 68 #define AD7746_EXCSETUP_NEXCA BIT(2) 69 #define AD7746_EXCSETUP_EXCLVL_MASK GENMASK(1, 0) 70 71 /* Config Register Bit Designations (AD7746_REG_CFG) */ 72 #define AD7746_CONF_VTFS_MASK GENMASK(7, 6) 73 #define AD7746_CONF_CAPFS_MASK GENMASK(5, 3) 74 #define AD7746_CONF_MODE_MASK GENMASK(2, 0) 75 #define AD7746_CONF_MODE_IDLE 0 76 #define AD7746_CONF_MODE_CONT_CONV 1 77 #define AD7746_CONF_MODE_SINGLE_CONV 2 78 #define AD7746_CONF_MODE_PWRDN 3 79 #define AD7746_CONF_MODE_OFFS_CAL 5 80 #define AD7746_CONF_MODE_GAIN_CAL 6 81 82 /* CAPDAC Register Bit Designations (AD7746_REG_CAPDACx) */ 83 #define AD7746_CAPDAC_DACEN BIT(7) 84 #define AD7746_CAPDAC_DACP_MASK GENMASK(6, 0) 85 86 struct ad7746_chip_info { 87 struct i2c_client *client; 88 struct mutex lock; /* protect sensor state */ 89 /* 90 * Capacitive channel digital filter setup; 91 * conversion time/update rate setup per channel 92 */ 93 u8 config; 94 u8 cap_setup; 95 u8 vt_setup; 96 u8 capdac[2][2]; 97 s8 capdac_set; 98 }; 99 100 enum ad7746_chan { 101 VIN, 102 VIN_VDD, 103 TEMP_INT, 104 TEMP_EXT, 105 CIN1, 106 CIN1_DIFF, 107 CIN2, 108 CIN2_DIFF, 109 }; 110 111 struct ad7746_chan_info { 112 u8 addr; 113 union { 114 u8 vtmd; 115 struct { /* CAP SETUP fields */ 116 unsigned int cin2 : 1; 117 unsigned int capdiff : 1; 118 }; 119 }; 120 }; 121 122 static const struct ad7746_chan_info ad7746_chan_info[] = { 123 [VIN] = { 124 .addr = AD7746_REG_VT_DATA_HIGH, 125 .vtmd = AD7746_VTSETUP_VTMD_EXT_VIN, 126 }, 127 [VIN_VDD] = { 128 .addr = AD7746_REG_VT_DATA_HIGH, 129 .vtmd = AD7746_VTSETUP_VTMD_VDD_MON, 130 }, 131 [TEMP_INT] = { 132 .addr = AD7746_REG_VT_DATA_HIGH, 133 .vtmd = AD7746_VTSETUP_VTMD_INT_TEMP, 134 }, 135 [TEMP_EXT] = { 136 .addr = AD7746_REG_VT_DATA_HIGH, 137 .vtmd = AD7746_VTSETUP_VTMD_EXT_TEMP, 138 }, 139 [CIN1] = { 140 .addr = AD7746_REG_CAP_DATA_HIGH, 141 }, 142 [CIN1_DIFF] = { 143 .addr = AD7746_REG_CAP_DATA_HIGH, 144 .capdiff = 1, 145 }, 146 [CIN2] = { 147 .addr = AD7746_REG_CAP_DATA_HIGH, 148 .cin2 = 1, 149 }, 150 [CIN2_DIFF] = { 151 .addr = AD7746_REG_CAP_DATA_HIGH, 152 .cin2 = 1, 153 .capdiff = 1, 154 }, 155 }; 156 157 static const struct iio_chan_spec ad7746_channels[] = { 158 [VIN] = { 159 .type = IIO_VOLTAGE, 160 .indexed = 1, 161 .channel = 0, 162 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 163 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), 164 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 165 .address = VIN, 166 }, 167 [VIN_VDD] = { 168 .type = IIO_VOLTAGE, 169 .indexed = 1, 170 .channel = 1, 171 .extend_name = "supply", 172 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 173 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), 174 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 175 .address = VIN_VDD, 176 }, 177 [TEMP_INT] = { 178 .type = IIO_TEMP, 179 .indexed = 1, 180 .channel = 0, 181 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 182 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 183 .address = TEMP_INT, 184 }, 185 [TEMP_EXT] = { 186 .type = IIO_TEMP, 187 .indexed = 1, 188 .channel = 1, 189 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 190 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 191 .address = TEMP_EXT, 192 }, 193 [CIN1] = { 194 .type = IIO_CAPACITANCE, 195 .indexed = 1, 196 .channel = 0, 197 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 198 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), 199 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | 200 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 201 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 202 .address = CIN1, 203 }, 204 [CIN1_DIFF] = { 205 .type = IIO_CAPACITANCE, 206 .differential = 1, 207 .indexed = 1, 208 .channel = 0, 209 .channel2 = 2, 210 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 211 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_ZEROPOINT), 212 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | 213 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 214 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 215 .address = CIN1_DIFF, 216 }, 217 [CIN2] = { 218 .type = IIO_CAPACITANCE, 219 .indexed = 1, 220 .channel = 1, 221 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 222 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), 223 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | 224 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 225 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 226 .address = CIN2, 227 }, 228 [CIN2_DIFF] = { 229 .type = IIO_CAPACITANCE, 230 .differential = 1, 231 .indexed = 1, 232 .channel = 1, 233 .channel2 = 3, 234 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 235 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_ZEROPOINT), 236 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | 237 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 238 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 239 .address = CIN2_DIFF, 240 } 241 }; 242 243 /* Values are Update Rate (Hz), Conversion Time (ms) + 1*/ 244 static const unsigned char ad7746_vt_filter_rate_table[][2] = { 245 { 50, 20 + 1 }, { 31, 32 + 1 }, { 16, 62 + 1 }, { 8, 122 + 1 }, 246 }; 247 248 static const unsigned char ad7746_cap_filter_rate_table[][2] = { 249 { 91, 11 + 1 }, { 84, 12 + 1 }, { 50, 20 + 1 }, { 26, 38 + 1 }, 250 { 16, 62 + 1 }, { 13, 77 + 1 }, { 11, 92 + 1 }, { 9, 110 + 1 }, 251 }; 252 253 static int ad7746_set_capdac(struct ad7746_chip_info *chip, int channel) 254 { 255 int ret = i2c_smbus_write_byte_data(chip->client, 256 AD7746_REG_CAPDACA, 257 chip->capdac[channel][0]); 258 if (ret < 0) 259 return ret; 260 261 return i2c_smbus_write_byte_data(chip->client, 262 AD7746_REG_CAPDACB, 263 chip->capdac[channel][1]); 264 } 265 266 static int ad7746_select_channel(struct iio_dev *indio_dev, 267 struct iio_chan_spec const *chan) 268 { 269 struct ad7746_chip_info *chip = iio_priv(indio_dev); 270 u8 vt_setup, cap_setup; 271 int ret, delay, idx; 272 273 switch (chan->type) { 274 case IIO_CAPACITANCE: 275 cap_setup = FIELD_PREP(AD7746_CAPSETUP_CIN2, 276 ad7746_chan_info[chan->address].cin2) | 277 FIELD_PREP(AD7746_CAPSETUP_CAPDIFF, 278 ad7746_chan_info[chan->address].capdiff) | 279 FIELD_PREP(AD7746_CAPSETUP_CAPEN, 1); 280 vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN; 281 idx = FIELD_GET(AD7746_CONF_CAPFS_MASK, chip->config); 282 delay = ad7746_cap_filter_rate_table[idx][1]; 283 284 ret = ad7746_set_capdac(chip, chan->channel); 285 if (ret < 0) 286 return ret; 287 288 if (chip->capdac_set != chan->channel) 289 chip->capdac_set = chan->channel; 290 break; 291 case IIO_VOLTAGE: 292 case IIO_TEMP: 293 vt_setup = FIELD_PREP(AD7746_VTSETUP_VTMD_MASK, 294 ad7746_chan_info[chan->address].vtmd) | 295 FIELD_PREP(AD7746_VTSETUP_VTEN, 1); 296 cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN; 297 idx = FIELD_GET(AD7746_CONF_VTFS_MASK, chip->config); 298 delay = ad7746_cap_filter_rate_table[idx][1]; 299 break; 300 default: 301 return -EINVAL; 302 } 303 304 if (chip->cap_setup != cap_setup) { 305 ret = i2c_smbus_write_byte_data(chip->client, 306 AD7746_REG_CAP_SETUP, 307 cap_setup); 308 if (ret < 0) 309 return ret; 310 311 chip->cap_setup = cap_setup; 312 } 313 314 if (chip->vt_setup != vt_setup) { 315 ret = i2c_smbus_write_byte_data(chip->client, 316 AD7746_REG_VT_SETUP, 317 vt_setup); 318 if (ret < 0) 319 return ret; 320 321 chip->vt_setup = vt_setup; 322 } 323 324 return delay; 325 } 326 327 static inline ssize_t ad7746_start_calib(struct device *dev, 328 struct device_attribute *attr, 329 const char *buf, 330 size_t len, 331 u8 regval) 332 { 333 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 334 struct ad7746_chip_info *chip = iio_priv(indio_dev); 335 int ret, timeout = 10; 336 bool doit; 337 338 ret = kstrtobool(buf, &doit); 339 if (ret < 0) 340 return ret; 341 342 if (!doit) 343 return 0; 344 345 mutex_lock(&chip->lock); 346 regval |= chip->config; 347 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval); 348 if (ret < 0) 349 goto unlock; 350 351 do { 352 msleep(20); 353 ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG); 354 if (ret < 0) 355 goto unlock; 356 357 } while ((ret == regval) && timeout--); 358 359 mutex_unlock(&chip->lock); 360 361 return len; 362 363 unlock: 364 mutex_unlock(&chip->lock); 365 return ret; 366 } 367 368 static ssize_t ad7746_start_offset_calib(struct device *dev, 369 struct device_attribute *attr, 370 const char *buf, 371 size_t len) 372 { 373 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 374 int ret = ad7746_select_channel(indio_dev, 375 &ad7746_channels[to_iio_dev_attr(attr)->address]); 376 if (ret < 0) 377 return ret; 378 379 return ad7746_start_calib(dev, attr, buf, len, 380 FIELD_PREP(AD7746_CONF_MODE_MASK, 381 AD7746_CONF_MODE_OFFS_CAL)); 382 } 383 384 static ssize_t ad7746_start_gain_calib(struct device *dev, 385 struct device_attribute *attr, 386 const char *buf, 387 size_t len) 388 { 389 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 390 int ret = ad7746_select_channel(indio_dev, 391 &ad7746_channels[to_iio_dev_attr(attr)->address]); 392 if (ret < 0) 393 return ret; 394 395 return ad7746_start_calib(dev, attr, buf, len, 396 FIELD_PREP(AD7746_CONF_MODE_MASK, 397 AD7746_CONF_MODE_GAIN_CAL)); 398 } 399 400 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration, 401 0200, NULL, ad7746_start_offset_calib, CIN1); 402 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration, 403 0200, NULL, ad7746_start_offset_calib, CIN2); 404 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration, 405 0200, NULL, ad7746_start_gain_calib, CIN1); 406 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration, 407 0200, NULL, ad7746_start_gain_calib, CIN2); 408 static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration, 409 0200, NULL, ad7746_start_gain_calib, VIN); 410 411 static int ad7746_store_cap_filter_rate_setup(struct ad7746_chip_info *chip, 412 int val) 413 { 414 int i; 415 416 for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++) 417 if (val >= ad7746_cap_filter_rate_table[i][0]) 418 break; 419 420 if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table)) 421 i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1; 422 423 chip->config &= ~AD7746_CONF_CAPFS_MASK; 424 chip->config |= FIELD_PREP(AD7746_CONF_CAPFS_MASK, i); 425 426 return 0; 427 } 428 429 static int ad7746_store_vt_filter_rate_setup(struct ad7746_chip_info *chip, 430 int val) 431 { 432 int i; 433 434 for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++) 435 if (val >= ad7746_vt_filter_rate_table[i][0]) 436 break; 437 438 if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table)) 439 i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1; 440 441 chip->config &= ~AD7746_CONF_VTFS_MASK; 442 chip->config |= FIELD_PREP(AD7746_CONF_VTFS_MASK, i); 443 444 return 0; 445 } 446 447 static struct attribute *ad7746_attributes[] = { 448 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr, 449 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr, 450 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr, 451 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr, 452 &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr, 453 NULL, 454 }; 455 456 static const struct attribute_group ad7746_attribute_group = { 457 .attrs = ad7746_attributes, 458 }; 459 460 static int ad7746_write_raw(struct iio_dev *indio_dev, 461 struct iio_chan_spec const *chan, 462 int val, 463 int val2, 464 long mask) 465 { 466 struct ad7746_chip_info *chip = iio_priv(indio_dev); 467 int ret, reg; 468 469 switch (mask) { 470 case IIO_CHAN_INFO_CALIBSCALE: 471 if (val != 1) 472 return -EINVAL; 473 474 val = (val2 * 1024) / 15625; 475 476 switch (chan->type) { 477 case IIO_CAPACITANCE: 478 reg = AD7746_REG_CAP_GAINH; 479 break; 480 case IIO_VOLTAGE: 481 reg = AD7746_REG_VOLT_GAINH; 482 break; 483 default: 484 return -EINVAL; 485 } 486 487 mutex_lock(&chip->lock); 488 ret = i2c_smbus_write_word_swapped(chip->client, reg, val); 489 mutex_unlock(&chip->lock); 490 if (ret < 0) 491 return ret; 492 493 return 0; 494 case IIO_CHAN_INFO_CALIBBIAS: 495 if (val < 0 || val > 0xFFFF) 496 return -EINVAL; 497 498 mutex_lock(&chip->lock); 499 ret = i2c_smbus_write_word_swapped(chip->client, 500 AD7746_REG_CAP_OFFH, val); 501 mutex_unlock(&chip->lock); 502 if (ret < 0) 503 return ret; 504 505 return 0; 506 case IIO_CHAN_INFO_OFFSET: 507 case IIO_CHAN_INFO_ZEROPOINT: 508 if (val < 0 || val > 43008000) /* 21pF */ 509 return -EINVAL; 510 511 /* 512 * CAPDAC Scale = 21pF_typ / 127 513 * CIN Scale = 8.192pF / 2^24 514 * Offset Scale = CAPDAC Scale / CIN Scale = 338646 515 */ 516 517 val /= 338646; 518 mutex_lock(&chip->lock); 519 chip->capdac[chan->channel][chan->differential] = val > 0 ? 520 FIELD_PREP(AD7746_CAPDAC_DACP_MASK, val) | AD7746_CAPDAC_DACEN : 0; 521 522 ret = ad7746_set_capdac(chip, chan->channel); 523 if (ret < 0) { 524 mutex_unlock(&chip->lock); 525 return ret; 526 } 527 528 chip->capdac_set = chan->channel; 529 mutex_unlock(&chip->lock); 530 531 return 0; 532 case IIO_CHAN_INFO_SAMP_FREQ: 533 if (val2) 534 return -EINVAL; 535 536 switch (chan->type) { 537 case IIO_CAPACITANCE: 538 mutex_lock(&chip->lock); 539 ret = ad7746_store_cap_filter_rate_setup(chip, val); 540 mutex_unlock(&chip->lock); 541 return ret; 542 case IIO_VOLTAGE: 543 mutex_lock(&chip->lock); 544 ret = ad7746_store_vt_filter_rate_setup(chip, val); 545 mutex_unlock(&chip->lock); 546 return ret; 547 default: 548 return -EINVAL; 549 } 550 default: 551 return -EINVAL; 552 } 553 } 554 555 static const int ad7746_v_samp_freq[] = { 50, 31, 16, 8, }; 556 static const int ad7746_cap_samp_freq[] = { 91, 84, 50, 26, 16, 13, 11, 9, }; 557 558 static int ad7746_read_avail(struct iio_dev *indio_dev, 559 struct iio_chan_spec const *chan, const int **vals, 560 int *type, int *length, long mask) 561 { 562 if (mask != IIO_CHAN_INFO_SAMP_FREQ) 563 return -EINVAL; 564 565 switch (chan->type) { 566 case IIO_VOLTAGE: 567 *vals = ad7746_v_samp_freq; 568 *length = ARRAY_SIZE(ad7746_v_samp_freq); 569 break; 570 case IIO_CAPACITANCE: 571 *vals = ad7746_cap_samp_freq; 572 *length = ARRAY_SIZE(ad7746_cap_samp_freq); 573 break; 574 default: 575 return -EINVAL; 576 } 577 *type = IIO_VAL_INT; 578 return IIO_AVAIL_LIST; 579 } 580 581 static int ad7746_read_channel(struct iio_dev *indio_dev, 582 struct iio_chan_spec const *chan, 583 int *val) 584 { 585 struct ad7746_chip_info *chip = iio_priv(indio_dev); 586 int ret, delay; 587 u8 data[3]; 588 u8 regval; 589 590 ret = ad7746_select_channel(indio_dev, chan); 591 if (ret < 0) 592 return ret; 593 delay = ret; 594 595 regval = chip->config | FIELD_PREP(AD7746_CONF_MODE_MASK, 596 AD7746_CONF_MODE_SINGLE_CONV); 597 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval); 598 if (ret < 0) 599 return ret; 600 601 msleep(delay); 602 /* Now read the actual register */ 603 ret = i2c_smbus_read_i2c_block_data(chip->client, 604 ad7746_chan_info[chan->address].addr, 605 sizeof(data), data); 606 if (ret < 0) 607 return ret; 608 609 /* 610 * Offset applied internally becaue the _offset userspace interface is 611 * needed for the CAP DACs which apply a controllable offset. 612 */ 613 *val = get_unaligned_be24(data) - 0x800000; 614 615 return 0; 616 } 617 618 static int ad7746_read_raw(struct iio_dev *indio_dev, 619 struct iio_chan_spec const *chan, 620 int *val, int *val2, 621 long mask) 622 { 623 struct ad7746_chip_info *chip = iio_priv(indio_dev); 624 int ret, idx; 625 u8 reg; 626 627 switch (mask) { 628 case IIO_CHAN_INFO_RAW: 629 mutex_lock(&chip->lock); 630 ret = ad7746_read_channel(indio_dev, chan, val); 631 mutex_unlock(&chip->lock); 632 if (ret < 0) 633 return ret; 634 635 return IIO_VAL_INT; 636 case IIO_CHAN_INFO_CALIBSCALE: 637 switch (chan->type) { 638 case IIO_CAPACITANCE: 639 reg = AD7746_REG_CAP_GAINH; 640 break; 641 case IIO_VOLTAGE: 642 reg = AD7746_REG_VOLT_GAINH; 643 break; 644 default: 645 return -EINVAL; 646 } 647 648 mutex_lock(&chip->lock); 649 ret = i2c_smbus_read_word_swapped(chip->client, reg); 650 mutex_unlock(&chip->lock); 651 if (ret < 0) 652 return ret; 653 /* 1 + gain_val / 2^16 */ 654 *val = 1; 655 *val2 = (15625 * ret) / 1024; 656 657 return IIO_VAL_INT_PLUS_MICRO; 658 case IIO_CHAN_INFO_CALIBBIAS: 659 mutex_lock(&chip->lock); 660 ret = i2c_smbus_read_word_swapped(chip->client, 661 AD7746_REG_CAP_OFFH); 662 mutex_unlock(&chip->lock); 663 if (ret < 0) 664 return ret; 665 *val = ret; 666 667 return IIO_VAL_INT; 668 case IIO_CHAN_INFO_OFFSET: 669 case IIO_CHAN_INFO_ZEROPOINT: 670 *val = FIELD_GET(AD7746_CAPDAC_DACP_MASK, 671 chip->capdac[chan->channel][chan->differential]) * 338646; 672 673 return IIO_VAL_INT; 674 case IIO_CHAN_INFO_SCALE: 675 switch (chan->type) { 676 case IIO_CAPACITANCE: 677 /* 8.192pf / 2^24 */ 678 *val = 0; 679 *val2 = 488; 680 return IIO_VAL_INT_PLUS_NANO; 681 case IIO_VOLTAGE: 682 /* 1170mV / 2^23 */ 683 *val = 1170; 684 if (chan->channel == 1) 685 *val *= 6; 686 *val2 = 23; 687 return IIO_VAL_FRACTIONAL_LOG2; 688 case IIO_TEMP: 689 *val = 125; 690 *val2 = 8; 691 return IIO_VAL_FRACTIONAL_LOG2; 692 default: 693 return -EINVAL; 694 } 695 case IIO_CHAN_INFO_SAMP_FREQ: 696 switch (chan->type) { 697 case IIO_CAPACITANCE: 698 idx = FIELD_GET(AD7746_CONF_CAPFS_MASK, chip->config); 699 *val = ad7746_cap_filter_rate_table[idx][0]; 700 return IIO_VAL_INT; 701 case IIO_VOLTAGE: 702 idx = FIELD_GET(AD7746_CONF_VTFS_MASK, chip->config); 703 *val = ad7746_vt_filter_rate_table[idx][0]; 704 return IIO_VAL_INT; 705 default: 706 return -EINVAL; 707 } 708 default: 709 return -EINVAL; 710 } 711 } 712 713 static const struct iio_info ad7746_info = { 714 .attrs = &ad7746_attribute_group, 715 .read_raw = ad7746_read_raw, 716 .read_avail = ad7746_read_avail, 717 .write_raw = ad7746_write_raw, 718 }; 719 720 static int ad7746_probe(struct i2c_client *client) 721 { 722 const struct i2c_device_id *id = i2c_client_get_device_id(client); 723 struct device *dev = &client->dev; 724 struct ad7746_chip_info *chip; 725 struct iio_dev *indio_dev; 726 unsigned char regval = 0; 727 unsigned int vdd_permille; 728 int ret; 729 730 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); 731 if (!indio_dev) 732 return -ENOMEM; 733 734 chip = iio_priv(indio_dev); 735 mutex_init(&chip->lock); 736 737 chip->client = client; 738 chip->capdac_set = -1; 739 740 indio_dev->name = id->name; 741 indio_dev->info = &ad7746_info; 742 indio_dev->channels = ad7746_channels; 743 if (id->driver_data == 7746) 744 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels); 745 else 746 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels) - 2; 747 indio_dev->modes = INDIO_DIRECT_MODE; 748 749 if (device_property_read_bool(dev, "adi,exca-output-en")) { 750 if (device_property_read_bool(dev, "adi,exca-output-invert")) 751 regval |= AD7746_EXCSETUP_NEXCA; 752 else 753 regval |= AD7746_EXCSETUP_EXCA; 754 } 755 756 if (device_property_read_bool(dev, "adi,excb-output-en")) { 757 if (device_property_read_bool(dev, "adi,excb-output-invert")) 758 regval |= AD7746_EXCSETUP_NEXCB; 759 else 760 regval |= AD7746_EXCSETUP_EXCB; 761 } 762 763 ret = device_property_read_u32(dev, "adi,excitation-vdd-permille", 764 &vdd_permille); 765 if (!ret) { 766 switch (vdd_permille) { 767 case 125: 768 regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 0); 769 break; 770 case 250: 771 regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 1); 772 break; 773 case 375: 774 regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 2); 775 break; 776 case 500: 777 regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 3); 778 break; 779 default: 780 break; 781 } 782 } 783 784 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_EXC_SETUP, 785 regval); 786 if (ret < 0) 787 return ret; 788 789 return devm_iio_device_register(indio_dev->dev.parent, indio_dev); 790 } 791 792 static const struct i2c_device_id ad7746_id[] = { 793 { "ad7745", 7745 }, 794 { "ad7746", 7746 }, 795 { "ad7747", 7747 }, 796 {} 797 }; 798 MODULE_DEVICE_TABLE(i2c, ad7746_id); 799 800 static const struct of_device_id ad7746_of_match[] = { 801 { .compatible = "adi,ad7745" }, 802 { .compatible = "adi,ad7746" }, 803 { .compatible = "adi,ad7747" }, 804 { }, 805 }; 806 MODULE_DEVICE_TABLE(of, ad7746_of_match); 807 808 static struct i2c_driver ad7746_driver = { 809 .driver = { 810 .name = KBUILD_MODNAME, 811 .of_match_table = ad7746_of_match, 812 }, 813 .probe_new = ad7746_probe, 814 .id_table = ad7746_id, 815 }; 816 module_i2c_driver(ad7746_driver); 817 818 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 819 MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver"); 820 MODULE_LICENSE("GPL v2"); 821