1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <asm/unaligned.h> 8 #include <linux/bitfield.h> 9 #include <linux/crc8.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/trigger_consumer.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/interrupt.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/spi/spi.h> 25 26 #include <dt-bindings/iio/addac/adi,ad74413r.h> 27 28 #define AD74413R_CRC_POLYNOMIAL 0x7 29 DECLARE_CRC8_TABLE(ad74413r_crc8_table); 30 31 #define AD74413R_CHANNEL_MAX 4 32 33 #define AD74413R_FRAME_SIZE 4 34 35 struct ad74413r_chip_info { 36 const char *name; 37 bool hart_support; 38 }; 39 40 struct ad74413r_channel_config { 41 u32 func; 42 bool gpo_comparator; 43 bool initialized; 44 }; 45 46 struct ad74413r_channels { 47 struct iio_chan_spec *channels; 48 unsigned int num_channels; 49 }; 50 51 struct ad74413r_state { 52 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX]; 53 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX]; 54 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX]; 55 struct gpio_chip gpo_gpiochip; 56 struct gpio_chip comp_gpiochip; 57 struct completion adc_data_completion; 58 unsigned int num_gpo_gpios; 59 unsigned int num_comparator_gpios; 60 u32 sense_resistor_ohms; 61 62 /* 63 * Synchronize consecutive operations when doing a one-shot 64 * conversion and when updating the ADC samples SPI message. 65 */ 66 struct mutex lock; 67 68 const struct ad74413r_chip_info *chip_info; 69 struct spi_device *spi; 70 struct regulator *refin_reg; 71 struct regmap *regmap; 72 struct device *dev; 73 struct iio_trigger *trig; 74 struct gpio_desc *reset_gpio; 75 76 size_t adc_active_channels; 77 struct spi_message adc_samples_msg; 78 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; 79 80 /* 81 * DMA (thus cache coherency maintenance) may require the 82 * transfer buffers to live in their own cache lines. 83 */ 84 struct { 85 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 86 s64 timestamp; 87 } adc_samples_buf __aligned(IIO_DMA_MINALIGN); 88 89 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 90 u8 reg_tx_buf[AD74413R_FRAME_SIZE]; 91 u8 reg_rx_buf[AD74413R_FRAME_SIZE]; 92 }; 93 94 #define AD74413R_REG_NOP 0x00 95 96 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x)) 97 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0) 98 99 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x)) 100 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5) 101 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3) 102 #define AD74413R_ADC_RANGE_10V 0b000 103 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001 104 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010 105 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011 106 #define AD74413R_ADC_REJECTION_50_60 0b00 107 #define AD74413R_ADC_REJECTION_NONE 0b01 108 #define AD74413R_ADC_REJECTION_50_60_HART 0b10 109 #define AD74413R_ADC_REJECTION_HART 0b11 110 111 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x)) 112 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0) 113 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5) 114 115 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x)) 116 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0) 117 #define AD74413R_DAC_VOLTAGE_MAX 11000 118 119 #define AD74413R_REG_GPO_PAR_DATA 0x0d 120 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x)) 121 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3) 122 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0) 123 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000 124 #define AD74413R_GPO_CONFIG_LOGIC 0b001 125 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010 126 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011 127 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100 128 129 #define AD74413R_REG_ADC_CONV_CTRL 0x23 130 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8) 131 #define AD74413R_CONV_SEQ_ON 0b00 132 #define AD74413R_CONV_SEQ_SINGLE 0b01 133 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10 134 #define AD74413R_CONV_SEQ_OFF 0b11 135 #define AD74413R_CH_EN_MASK(x) BIT(x) 136 137 #define AD74413R_REG_DIN_COMP_OUT 0x25 138 139 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x)) 140 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0) 141 142 #define AD74413R_REG_READ_SELECT 0x41 143 144 #define AD74413R_REG_CMD_KEY 0x44 145 #define AD74413R_CMD_KEY_LDAC 0x953a 146 #define AD74413R_CMD_KEY_RESET1 0x15fa 147 #define AD74413R_CMD_KEY_RESET2 0xaf51 148 149 static const int ad74413r_adc_sampling_rates[] = { 150 20, 4800, 151 }; 152 153 static const int ad74413r_adc_sampling_rates_hart[] = { 154 10, 20, 1200, 4800, 155 }; 156 157 static int ad74413r_crc(u8 *buf) 158 { 159 return crc8(ad74413r_crc8_table, buf, 3, 0); 160 } 161 162 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf) 163 { 164 buf[0] = reg; 165 put_unaligned_be16(val, &buf[1]); 166 buf[3] = ad74413r_crc(buf); 167 } 168 169 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val) 170 { 171 struct ad74413r_state *st = context; 172 173 ad74413r_format_reg_write(reg, val, st->reg_tx_buf); 174 175 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); 176 } 177 178 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf) 179 { 180 u8 expected_crc = ad74413r_crc(buf); 181 182 if (buf[3] != expected_crc) { 183 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", 184 buf[3], buf[0], buf[1], buf[2]); 185 return -EINVAL; 186 } 187 188 return 0; 189 } 190 191 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val) 192 { 193 struct ad74413r_state *st = context; 194 struct spi_transfer reg_read_xfer[] = { 195 { 196 .tx_buf = st->reg_tx_buf, 197 .len = AD74413R_FRAME_SIZE, 198 .cs_change = 1, 199 }, 200 { 201 .rx_buf = st->reg_rx_buf, 202 .len = AD74413R_FRAME_SIZE, 203 }, 204 }; 205 int ret; 206 207 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg, 208 st->reg_tx_buf); 209 210 ret = spi_sync_transfer(st->spi, reg_read_xfer, 211 ARRAY_SIZE(reg_read_xfer)); 212 if (ret) 213 return ret; 214 215 ret = ad74413r_crc_check(st, st->reg_rx_buf); 216 if (ret) 217 return ret; 218 219 *val = get_unaligned_be16(&st->reg_rx_buf[1]); 220 221 return 0; 222 } 223 224 static const struct regmap_config ad74413r_regmap_config = { 225 .reg_bits = 8, 226 .val_bits = 16, 227 .reg_read = ad74413r_reg_read, 228 .reg_write = ad74413r_reg_write, 229 }; 230 231 static int ad74413r_set_gpo_config(struct ad74413r_state *st, 232 unsigned int offset, u8 mode) 233 { 234 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset), 235 AD74413R_GPO_CONFIG_SELECT_MASK, mode); 236 } 237 238 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = { 239 0, 13, 18, 24, 32, 42, 56, 75, 240 100, 130, 180, 240, 320, 420, 560, 750, 241 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500, 242 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000, 243 }; 244 245 static int ad74413r_set_comp_debounce(struct ad74413r_state *st, 246 unsigned int offset, 247 unsigned int debounce) 248 { 249 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1; 250 unsigned int i; 251 252 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++) 253 if (debounce <= ad74413r_debounce_map[i]) { 254 val = i; 255 break; 256 } 257 258 return regmap_update_bits(st->regmap, 259 AD74413R_REG_DIN_CONFIG_X(offset), 260 AD74413R_DIN_DEBOUNCE_MASK, 261 val); 262 } 263 264 static void ad74413r_gpio_set(struct gpio_chip *chip, 265 unsigned int offset, int val) 266 { 267 struct ad74413r_state *st = gpiochip_get_data(chip); 268 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 269 int ret; 270 271 ret = ad74413r_set_gpo_config(st, real_offset, 272 AD74413R_GPO_CONFIG_LOGIC); 273 if (ret) 274 return; 275 276 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset), 277 AD74413R_GPO_CONFIG_DATA_MASK, 278 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0); 279 } 280 281 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip, 282 unsigned long *mask, 283 unsigned long *bits) 284 { 285 struct ad74413r_state *st = gpiochip_get_data(chip); 286 unsigned long real_mask = 0; 287 unsigned long real_bits = 0; 288 unsigned int offset; 289 int ret; 290 291 for_each_set_bit(offset, mask, chip->ngpio) { 292 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 293 294 ret = ad74413r_set_gpo_config(st, real_offset, 295 AD74413R_GPO_CONFIG_LOGIC_PARALLEL); 296 if (ret) 297 return; 298 299 real_mask |= BIT(real_offset); 300 if (*bits & offset) 301 real_bits |= BIT(real_offset); 302 } 303 304 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA, 305 real_mask, real_bits); 306 } 307 308 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset) 309 { 310 struct ad74413r_state *st = gpiochip_get_data(chip); 311 unsigned int real_offset = st->comp_gpio_offsets[offset]; 312 unsigned int status; 313 int ret; 314 315 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status); 316 if (ret) 317 return ret; 318 319 status &= BIT(real_offset); 320 321 return status ? 1 : 0; 322 } 323 324 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, 325 unsigned long *mask, 326 unsigned long *bits) 327 { 328 struct ad74413r_state *st = gpiochip_get_data(chip); 329 unsigned int offset; 330 unsigned int val; 331 int ret; 332 333 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val); 334 if (ret) 335 return ret; 336 337 for_each_set_bit(offset, mask, chip->ngpio) { 338 unsigned int real_offset = st->comp_gpio_offsets[offset]; 339 340 __assign_bit(offset, bits, val & BIT(real_offset)); 341 } 342 343 return ret; 344 } 345 346 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip, 347 unsigned int offset) 348 { 349 return GPIO_LINE_DIRECTION_OUT; 350 } 351 352 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip, 353 unsigned int offset) 354 { 355 return GPIO_LINE_DIRECTION_IN; 356 } 357 358 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip, 359 unsigned int offset, 360 unsigned long config) 361 { 362 struct ad74413r_state *st = gpiochip_get_data(chip); 363 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 364 365 switch (pinconf_to_config_param(config)) { 366 case PIN_CONFIG_BIAS_PULL_DOWN: 367 return ad74413r_set_gpo_config(st, real_offset, 368 AD74413R_GPO_CONFIG_100K_PULL_DOWN); 369 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 370 return ad74413r_set_gpo_config(st, real_offset, 371 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE); 372 default: 373 return -ENOTSUPP; 374 } 375 } 376 377 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip, 378 unsigned int offset, 379 unsigned long config) 380 { 381 struct ad74413r_state *st = gpiochip_get_data(chip); 382 unsigned int real_offset = st->comp_gpio_offsets[offset]; 383 384 switch (pinconf_to_config_param(config)) { 385 case PIN_CONFIG_INPUT_DEBOUNCE: 386 return ad74413r_set_comp_debounce(st, real_offset, 387 pinconf_to_config_argument(config)); 388 default: 389 return -ENOTSUPP; 390 } 391 } 392 393 static int ad74413r_reset(struct ad74413r_state *st) 394 { 395 int ret; 396 397 if (st->reset_gpio) { 398 gpiod_set_value_cansleep(st->reset_gpio, 1); 399 fsleep(50); 400 gpiod_set_value_cansleep(st->reset_gpio, 0); 401 return 0; 402 } 403 404 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 405 AD74413R_CMD_KEY_RESET1); 406 if (ret) 407 return ret; 408 409 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 410 AD74413R_CMD_KEY_RESET2); 411 } 412 413 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st, 414 unsigned int channel, int dac_code) 415 { 416 struct reg_sequence reg_seq[2] = { 417 { AD74413R_REG_DAC_CODE_X(channel), dac_code }, 418 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC }, 419 }; 420 421 return regmap_multi_reg_write(st->regmap, reg_seq, 2); 422 } 423 424 static int ad74413r_set_channel_function(struct ad74413r_state *st, 425 unsigned int channel, u8 func) 426 { 427 return regmap_update_bits(st->regmap, 428 AD74413R_REG_CH_FUNC_SETUP_X(channel), 429 AD74413R_CH_FUNC_SETUP_MASK, func); 430 } 431 432 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st, 433 unsigned int status) 434 { 435 int ret; 436 437 /* 438 * These bits do not clear when a conversion completes. 439 * To enable a subsequent conversion, repeat the write. 440 */ 441 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 442 AD74413R_CONV_SEQ_MASK, 443 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status)); 444 if (ret) 445 return ret; 446 447 /* 448 * Wait 100us before starting conversions. 449 */ 450 usleep_range(100, 120); 451 452 return 0; 453 } 454 455 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st, 456 unsigned int channel, 457 bool status) 458 { 459 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 460 AD74413R_CH_EN_MASK(channel), 461 status ? AD74413R_CH_EN_MASK(channel) : 0); 462 } 463 464 static int ad74413r_get_adc_range(struct ad74413r_state *st, 465 unsigned int channel, 466 unsigned int *val) 467 { 468 int ret; 469 470 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 471 if (ret) 472 return ret; 473 474 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val); 475 476 return 0; 477 } 478 479 static int ad74413r_get_adc_rejection(struct ad74413r_state *st, 480 unsigned int channel, 481 unsigned int *val) 482 { 483 int ret; 484 485 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 486 if (ret) 487 return ret; 488 489 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val); 490 491 return 0; 492 } 493 494 static int ad74413r_set_adc_rejection(struct ad74413r_state *st, 495 unsigned int channel, 496 unsigned int val) 497 { 498 return regmap_update_bits(st->regmap, 499 AD74413R_REG_ADC_CONFIG_X(channel), 500 AD74413R_ADC_CONFIG_REJECTION_MASK, 501 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK, 502 val)); 503 } 504 505 static int ad74413r_rejection_to_rate(struct ad74413r_state *st, 506 unsigned int rej, int *val) 507 { 508 switch (rej) { 509 case AD74413R_ADC_REJECTION_50_60: 510 *val = 20; 511 return 0; 512 case AD74413R_ADC_REJECTION_NONE: 513 *val = 4800; 514 return 0; 515 case AD74413R_ADC_REJECTION_50_60_HART: 516 *val = 10; 517 return 0; 518 case AD74413R_ADC_REJECTION_HART: 519 *val = 1200; 520 return 0; 521 default: 522 dev_err(st->dev, "ADC rejection invalid\n"); 523 return -EINVAL; 524 } 525 } 526 527 static int ad74413r_rate_to_rejection(struct ad74413r_state *st, 528 int rate, unsigned int *val) 529 { 530 switch (rate) { 531 case 20: 532 *val = AD74413R_ADC_REJECTION_50_60; 533 return 0; 534 case 4800: 535 *val = AD74413R_ADC_REJECTION_NONE; 536 return 0; 537 case 10: 538 *val = AD74413R_ADC_REJECTION_50_60_HART; 539 return 0; 540 case 1200: 541 *val = AD74413R_ADC_REJECTION_HART; 542 return 0; 543 default: 544 dev_err(st->dev, "ADC rate invalid\n"); 545 return -EINVAL; 546 } 547 } 548 549 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st, 550 unsigned int range, int *val) 551 { 552 switch (range) { 553 case AD74413R_ADC_RANGE_10V: 554 *val = 10000; 555 return 0; 556 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 557 case AD74413R_ADC_RANGE_2P5V_INT_POW: 558 *val = 2500; 559 return 0; 560 case AD74413R_ADC_RANGE_5V_BI_DIR: 561 *val = 5000; 562 return 0; 563 default: 564 dev_err(st->dev, "ADC range invalid\n"); 565 return -EINVAL; 566 } 567 } 568 569 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st, 570 unsigned int range, int *val) 571 { 572 switch (range) { 573 case AD74413R_ADC_RANGE_10V: 574 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 575 *val = 0; 576 return 0; 577 case AD74413R_ADC_RANGE_2P5V_INT_POW: 578 case AD74413R_ADC_RANGE_5V_BI_DIR: 579 *val = -2500; 580 return 0; 581 default: 582 dev_err(st->dev, "ADC range invalid\n"); 583 return -EINVAL; 584 } 585 } 586 587 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st, 588 unsigned int range, int *val) 589 { 590 switch (range) { 591 case AD74413R_ADC_RANGE_10V: 592 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 593 *val = 0; 594 return 0; 595 case AD74413R_ADC_RANGE_2P5V_INT_POW: 596 *val = -((int)AD74413R_ADC_RESULT_MAX); 597 return 0; 598 case AD74413R_ADC_RANGE_5V_BI_DIR: 599 *val = -((int)AD74413R_ADC_RESULT_MAX / 2); 600 return 0; 601 default: 602 dev_err(st->dev, "ADC range invalid\n"); 603 return -EINVAL; 604 } 605 } 606 607 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st, 608 int *val, int *val2) 609 { 610 *val = AD74413R_DAC_VOLTAGE_MAX; 611 *val2 = AD74413R_DAC_CODE_MAX; 612 613 return IIO_VAL_FRACTIONAL; 614 } 615 616 static int ad74413r_get_output_current_scale(struct ad74413r_state *st, 617 int *val, int *val2) 618 { 619 *val = regulator_get_voltage(st->refin_reg); 620 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000; 621 622 return IIO_VAL_FRACTIONAL; 623 } 624 625 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st, 626 unsigned int channel, 627 int *val, int *val2) 628 { 629 unsigned int range; 630 int ret; 631 632 ret = ad74413r_get_adc_range(st, channel, &range); 633 if (ret) 634 return ret; 635 636 ret = ad74413r_range_to_voltage_range(st, range, val); 637 if (ret) 638 return ret; 639 640 *val2 = AD74413R_ADC_RESULT_MAX; 641 642 return IIO_VAL_FRACTIONAL; 643 } 644 645 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st, 646 unsigned int channel, int *val) 647 { 648 unsigned int range; 649 int ret; 650 651 ret = ad74413r_get_adc_range(st, channel, &range); 652 if (ret) 653 return ret; 654 655 ret = ad74413r_range_to_voltage_offset_raw(st, range, val); 656 if (ret) 657 return ret; 658 659 return IIO_VAL_INT; 660 } 661 662 static int ad74413r_get_input_current_scale(struct ad74413r_state *st, 663 unsigned int channel, int *val, 664 int *val2) 665 { 666 unsigned int range; 667 int ret; 668 669 ret = ad74413r_get_adc_range(st, channel, &range); 670 if (ret) 671 return ret; 672 673 ret = ad74413r_range_to_voltage_range(st, range, val); 674 if (ret) 675 return ret; 676 677 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms; 678 679 return IIO_VAL_FRACTIONAL; 680 } 681 682 static int ad74413_get_input_current_offset(struct ad74413r_state *st, 683 unsigned int channel, int *val) 684 { 685 unsigned int range; 686 int voltage_range; 687 int voltage_offset; 688 int ret; 689 690 ret = ad74413r_get_adc_range(st, channel, &range); 691 if (ret) 692 return ret; 693 694 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range); 695 if (ret) 696 return ret; 697 698 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset); 699 if (ret) 700 return ret; 701 702 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range; 703 704 return IIO_VAL_INT; 705 } 706 707 static int ad74413r_get_adc_rate(struct ad74413r_state *st, 708 unsigned int channel, int *val) 709 { 710 unsigned int rejection; 711 int ret; 712 713 ret = ad74413r_get_adc_rejection(st, channel, &rejection); 714 if (ret) 715 return ret; 716 717 ret = ad74413r_rejection_to_rate(st, rejection, val); 718 if (ret) 719 return ret; 720 721 return IIO_VAL_INT; 722 } 723 724 static int ad74413r_set_adc_rate(struct ad74413r_state *st, 725 unsigned int channel, int val) 726 { 727 unsigned int rejection; 728 int ret; 729 730 ret = ad74413r_rate_to_rejection(st, val, &rejection); 731 if (ret) 732 return ret; 733 734 return ad74413r_set_adc_rejection(st, channel, rejection); 735 } 736 737 static irqreturn_t ad74413r_trigger_handler(int irq, void *p) 738 { 739 struct iio_poll_func *pf = p; 740 struct iio_dev *indio_dev = pf->indio_dev; 741 struct ad74413r_state *st = iio_priv(indio_dev); 742 u8 *rx_buf = st->adc_samples_buf.rx_buf; 743 unsigned int i; 744 int ret; 745 746 ret = spi_sync(st->spi, &st->adc_samples_msg); 747 if (ret) 748 goto out; 749 750 for (i = 0; i < st->adc_active_channels; i++) 751 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]); 752 753 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf, 754 iio_get_time_ns(indio_dev)); 755 756 out: 757 iio_trigger_notify_done(indio_dev->trig); 758 759 return IRQ_HANDLED; 760 } 761 762 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data) 763 { 764 struct iio_dev *indio_dev = data; 765 struct ad74413r_state *st = iio_priv(indio_dev); 766 767 if (iio_buffer_enabled(indio_dev)) 768 iio_trigger_poll(st->trig); 769 else 770 complete(&st->adc_data_completion); 771 772 return IRQ_HANDLED; 773 } 774 775 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st, 776 unsigned int channel, int *val) 777 { 778 unsigned int uval; 779 int ret; 780 781 reinit_completion(&st->adc_data_completion); 782 783 ret = ad74413r_set_adc_channel_enable(st, channel, true); 784 if (ret) 785 return ret; 786 787 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE); 788 if (ret) 789 return ret; 790 791 ret = wait_for_completion_timeout(&st->adc_data_completion, 792 msecs_to_jiffies(1000)); 793 if (!ret) { 794 ret = -ETIMEDOUT; 795 return ret; 796 } 797 798 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel), 799 &uval); 800 if (ret) 801 return ret; 802 803 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 804 if (ret) 805 return ret; 806 807 ret = ad74413r_set_adc_channel_enable(st, channel, false); 808 if (ret) 809 return ret; 810 811 *val = uval; 812 813 return IIO_VAL_INT; 814 } 815 816 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev, 817 unsigned int channel, int *val) 818 { 819 struct ad74413r_state *st = iio_priv(indio_dev); 820 int ret; 821 822 ret = iio_device_claim_direct_mode(indio_dev); 823 if (ret) 824 return ret; 825 826 mutex_lock(&st->lock); 827 ret = _ad74413r_get_single_adc_result(st, channel, val); 828 mutex_unlock(&st->lock); 829 830 iio_device_release_direct_mode(indio_dev); 831 832 return ret; 833 } 834 835 static void ad74413r_adc_to_resistance_result(int adc_result, int *val) 836 { 837 if (adc_result == AD74413R_ADC_RESULT_MAX) 838 adc_result = AD74413R_ADC_RESULT_MAX - 1; 839 840 *val = DIV_ROUND_CLOSEST(adc_result * 2100, 841 AD74413R_ADC_RESULT_MAX - adc_result); 842 } 843 844 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev, 845 const unsigned long *active_scan_mask) 846 { 847 struct ad74413r_state *st = iio_priv(indio_dev); 848 struct spi_transfer *xfer = st->adc_samples_xfer; 849 u8 *rx_buf = st->adc_samples_buf.rx_buf; 850 u8 *tx_buf = st->adc_samples_tx_buf; 851 unsigned int channel; 852 int ret = -EINVAL; 853 854 mutex_lock(&st->lock); 855 856 spi_message_init(&st->adc_samples_msg); 857 st->adc_active_channels = 0; 858 859 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 860 ret = ad74413r_set_adc_channel_enable(st, channel, false); 861 if (ret) 862 goto out; 863 } 864 865 if (*active_scan_mask == 0) 866 goto out; 867 868 /* 869 * The read select register is used to select which register's value 870 * will be sent by the slave on the next SPI frame. 871 * 872 * Create an SPI message that, on each step, writes to the read select 873 * register to select the ADC result of the next enabled channel, and 874 * reads the ADC result of the previous enabled channel. 875 * 876 * Example: 877 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ] 878 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4] 879 */ 880 881 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 882 ret = ad74413r_set_adc_channel_enable(st, channel, true); 883 if (ret) 884 goto out; 885 886 st->adc_active_channels++; 887 888 if (xfer == st->adc_samples_xfer) 889 xfer->rx_buf = NULL; 890 else 891 xfer->rx_buf = rx_buf; 892 893 xfer->tx_buf = tx_buf; 894 xfer->len = AD74413R_FRAME_SIZE; 895 xfer->cs_change = 1; 896 897 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, 898 AD74413R_REG_ADC_RESULT_X(channel), 899 tx_buf); 900 901 spi_message_add_tail(xfer, &st->adc_samples_msg); 902 903 tx_buf += AD74413R_FRAME_SIZE; 904 if (xfer != st->adc_samples_xfer) 905 rx_buf += AD74413R_FRAME_SIZE; 906 xfer++; 907 } 908 909 xfer->rx_buf = rx_buf; 910 xfer->tx_buf = NULL; 911 xfer->len = AD74413R_FRAME_SIZE; 912 xfer->cs_change = 0; 913 914 spi_message_add_tail(xfer, &st->adc_samples_msg); 915 916 out: 917 mutex_unlock(&st->lock); 918 919 return ret; 920 } 921 922 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev) 923 { 924 struct ad74413r_state *st = iio_priv(indio_dev); 925 926 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS); 927 } 928 929 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev) 930 { 931 struct ad74413r_state *st = iio_priv(indio_dev); 932 933 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 934 } 935 936 static int ad74413r_read_raw(struct iio_dev *indio_dev, 937 struct iio_chan_spec const *chan, 938 int *val, int *val2, long info) 939 { 940 struct ad74413r_state *st = iio_priv(indio_dev); 941 942 switch (info) { 943 case IIO_CHAN_INFO_SCALE: 944 switch (chan->type) { 945 case IIO_VOLTAGE: 946 if (chan->output) 947 return ad74413r_get_output_voltage_scale(st, 948 val, val2); 949 else 950 return ad74413r_get_input_voltage_scale(st, 951 chan->channel, val, val2); 952 case IIO_CURRENT: 953 if (chan->output) 954 return ad74413r_get_output_current_scale(st, 955 val, val2); 956 else 957 return ad74413r_get_input_current_scale(st, 958 chan->channel, val, val2); 959 default: 960 return -EINVAL; 961 } 962 case IIO_CHAN_INFO_OFFSET: 963 switch (chan->type) { 964 case IIO_VOLTAGE: 965 return ad74413r_get_input_voltage_offset(st, 966 chan->channel, val); 967 case IIO_CURRENT: 968 return ad74413_get_input_current_offset(st, 969 chan->channel, val); 970 default: 971 return -EINVAL; 972 } 973 case IIO_CHAN_INFO_RAW: 974 if (chan->output) 975 return -EINVAL; 976 977 return ad74413r_get_single_adc_result(indio_dev, chan->channel, 978 val); 979 case IIO_CHAN_INFO_PROCESSED: { 980 int ret; 981 982 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel, 983 val); 984 if (ret) 985 return ret; 986 987 ad74413r_adc_to_resistance_result(*val, val); 988 989 return ret; 990 } 991 case IIO_CHAN_INFO_SAMP_FREQ: 992 return ad74413r_get_adc_rate(st, chan->channel, val); 993 default: 994 return -EINVAL; 995 } 996 } 997 998 static int ad74413r_write_raw(struct iio_dev *indio_dev, 999 struct iio_chan_spec const *chan, 1000 int val, int val2, long info) 1001 { 1002 struct ad74413r_state *st = iio_priv(indio_dev); 1003 1004 switch (info) { 1005 case IIO_CHAN_INFO_RAW: 1006 if (!chan->output) 1007 return -EINVAL; 1008 1009 if (val < 0 || val > AD74413R_DAC_CODE_MAX) { 1010 dev_err(st->dev, "Invalid DAC code\n"); 1011 return -EINVAL; 1012 } 1013 1014 return ad74413r_set_channel_dac_code(st, chan->channel, val); 1015 case IIO_CHAN_INFO_SAMP_FREQ: 1016 return ad74413r_set_adc_rate(st, chan->channel, val); 1017 default: 1018 return -EINVAL; 1019 } 1020 } 1021 1022 static int ad74413r_read_avail(struct iio_dev *indio_dev, 1023 struct iio_chan_spec const *chan, 1024 const int **vals, int *type, int *length, 1025 long info) 1026 { 1027 struct ad74413r_state *st = iio_priv(indio_dev); 1028 1029 switch (info) { 1030 case IIO_CHAN_INFO_SAMP_FREQ: 1031 if (st->chip_info->hart_support) { 1032 *vals = ad74413r_adc_sampling_rates_hart; 1033 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart); 1034 } else { 1035 *vals = ad74413r_adc_sampling_rates; 1036 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates); 1037 } 1038 *type = IIO_VAL_INT; 1039 return IIO_AVAIL_LIST; 1040 default: 1041 return -EINVAL; 1042 } 1043 } 1044 1045 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = { 1046 .postenable = &ad74413r_buffer_postenable, 1047 .predisable = &ad74413r_buffer_predisable, 1048 }; 1049 1050 static const struct iio_trigger_ops ad74413r_trigger_ops = { 1051 .validate_device = iio_trigger_validate_own_device, 1052 }; 1053 1054 static const struct iio_info ad74413r_info = { 1055 .read_raw = &ad74413r_read_raw, 1056 .write_raw = &ad74413r_write_raw, 1057 .read_avail = &ad74413r_read_avail, 1058 .update_scan_mode = &ad74413r_update_scan_mode, 1059 }; 1060 1061 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \ 1062 { \ 1063 .type = (_type), \ 1064 .indexed = 1, \ 1065 .output = 1, \ 1066 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1067 | (extra_mask_separate), \ 1068 } 1069 1070 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \ 1071 { \ 1072 .type = (_type), \ 1073 .indexed = 1, \ 1074 .output = 0, \ 1075 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1076 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 1077 | (extra_mask_separate), \ 1078 .info_mask_separate_available = \ 1079 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1080 .scan_type = { \ 1081 .sign = 'u', \ 1082 .realbits = 16, \ 1083 .storagebits = 32, \ 1084 .shift = 8, \ 1085 .endianness = IIO_BE, \ 1086 }, \ 1087 } 1088 1089 #define AD74413R_ADC_VOLTAGE_CHANNEL \ 1090 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \ 1091 | BIT(IIO_CHAN_INFO_OFFSET)) 1092 1093 #define AD74413R_ADC_CURRENT_CHANNEL \ 1094 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \ 1095 | BIT(IIO_CHAN_INFO_OFFSET)) 1096 1097 static struct iio_chan_spec ad74413r_voltage_output_channels[] = { 1098 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)), 1099 AD74413R_ADC_CURRENT_CHANNEL, 1100 }; 1101 1102 static struct iio_chan_spec ad74413r_current_output_channels[] = { 1103 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)), 1104 AD74413R_ADC_VOLTAGE_CHANNEL, 1105 }; 1106 1107 static struct iio_chan_spec ad74413r_voltage_input_channels[] = { 1108 AD74413R_ADC_VOLTAGE_CHANNEL, 1109 }; 1110 1111 static struct iio_chan_spec ad74413r_current_input_channels[] = { 1112 AD74413R_ADC_CURRENT_CHANNEL, 1113 }; 1114 1115 static struct iio_chan_spec ad74413r_resistance_input_channels[] = { 1116 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)), 1117 }; 1118 1119 static struct iio_chan_spec ad74413r_digital_input_channels[] = { 1120 AD74413R_ADC_VOLTAGE_CHANNEL, 1121 }; 1122 1123 #define _AD74413R_CHANNELS(_channels) \ 1124 { \ 1125 .channels = _channels, \ 1126 .num_channels = ARRAY_SIZE(_channels), \ 1127 } 1128 1129 #define AD74413R_CHANNELS(name) \ 1130 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels) 1131 1132 static const struct ad74413r_channels ad74413r_channels_map[] = { 1133 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input), 1134 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output), 1135 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output), 1136 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input), 1137 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input), 1138 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input), 1139 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input), 1140 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input), 1141 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input), 1142 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input), 1143 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input), 1144 }; 1145 1146 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev, 1147 struct fwnode_handle *channel_node) 1148 { 1149 struct ad74413r_state *st = iio_priv(indio_dev); 1150 struct ad74413r_channel_config *config; 1151 u32 index; 1152 int ret; 1153 1154 ret = fwnode_property_read_u32(channel_node, "reg", &index); 1155 if (ret) { 1156 dev_err(st->dev, "Failed to read channel reg: %d\n", ret); 1157 return ret; 1158 } 1159 1160 if (index >= AD74413R_CHANNEL_MAX) { 1161 dev_err(st->dev, "Channel index %u is too large\n", index); 1162 return -EINVAL; 1163 } 1164 1165 config = &st->channel_configs[index]; 1166 if (config->initialized) { 1167 dev_err(st->dev, "Channel %u already initialized\n", index); 1168 return -EINVAL; 1169 } 1170 1171 config->func = CH_FUNC_HIGH_IMPEDANCE; 1172 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func); 1173 1174 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) { 1175 dev_err(st->dev, "Invalid channel function %u\n", config->func); 1176 return -EINVAL; 1177 } 1178 1179 if (!st->chip_info->hart_support && 1180 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART || 1181 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) { 1182 dev_err(st->dev, "Unsupported HART function %u\n", config->func); 1183 return -EINVAL; 1184 } 1185 1186 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1187 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) 1188 st->num_comparator_gpios++; 1189 1190 config->gpo_comparator = fwnode_property_read_bool(channel_node, 1191 "adi,gpo-comparator"); 1192 1193 if (!config->gpo_comparator) 1194 st->num_gpo_gpios++; 1195 1196 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels; 1197 1198 config->initialized = true; 1199 1200 return 0; 1201 } 1202 1203 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev) 1204 { 1205 struct ad74413r_state *st = iio_priv(indio_dev); 1206 struct fwnode_handle *channel_node = NULL; 1207 int ret; 1208 1209 fwnode_for_each_available_child_node(dev_fwnode(st->dev), channel_node) { 1210 ret = ad74413r_parse_channel_config(indio_dev, channel_node); 1211 if (ret) 1212 goto put_channel_node; 1213 } 1214 1215 return 0; 1216 1217 put_channel_node: 1218 fwnode_handle_put(channel_node); 1219 1220 return ret; 1221 } 1222 1223 static int ad74413r_setup_channels(struct iio_dev *indio_dev) 1224 { 1225 struct ad74413r_state *st = iio_priv(indio_dev); 1226 struct ad74413r_channel_config *config; 1227 struct iio_chan_spec *channels, *chans; 1228 unsigned int i, num_chans, chan_i; 1229 int ret; 1230 1231 channels = devm_kcalloc(st->dev, sizeof(*channels), 1232 indio_dev->num_channels, GFP_KERNEL); 1233 if (!channels) 1234 return -ENOMEM; 1235 1236 indio_dev->channels = channels; 1237 1238 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1239 config = &st->channel_configs[i]; 1240 chans = ad74413r_channels_map[config->func].channels; 1241 num_chans = ad74413r_channels_map[config->func].num_channels; 1242 1243 memcpy(channels, chans, num_chans * sizeof(*chans)); 1244 1245 for (chan_i = 0; chan_i < num_chans; chan_i++) { 1246 struct iio_chan_spec *chan = &channels[chan_i]; 1247 1248 chan->channel = i; 1249 if (chan->output) 1250 chan->scan_index = -1; 1251 else 1252 chan->scan_index = i; 1253 } 1254 1255 ret = ad74413r_set_channel_function(st, i, config->func); 1256 if (ret) 1257 return ret; 1258 1259 channels += num_chans; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int ad74413r_setup_gpios(struct ad74413r_state *st) 1266 { 1267 struct ad74413r_channel_config *config; 1268 unsigned int comp_gpio_i = 0; 1269 unsigned int gpo_gpio_i = 0; 1270 unsigned int i; 1271 u8 gpo_config; 1272 int ret; 1273 1274 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1275 config = &st->channel_configs[i]; 1276 1277 if (config->gpo_comparator) { 1278 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR; 1279 } else { 1280 gpo_config = AD74413R_GPO_CONFIG_LOGIC; 1281 st->gpo_gpio_offsets[gpo_gpio_i++] = i; 1282 } 1283 1284 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1285 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) 1286 st->comp_gpio_offsets[comp_gpio_i++] = i; 1287 1288 ret = ad74413r_set_gpo_config(st, i, gpo_config); 1289 if (ret) 1290 return ret; 1291 } 1292 1293 return 0; 1294 } 1295 1296 static void ad74413r_regulator_disable(void *regulator) 1297 { 1298 regulator_disable(regulator); 1299 } 1300 1301 static int ad74413r_probe(struct spi_device *spi) 1302 { 1303 struct ad74413r_state *st; 1304 struct iio_dev *indio_dev; 1305 int ret; 1306 1307 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1308 if (!indio_dev) 1309 return -ENOMEM; 1310 1311 st = iio_priv(indio_dev); 1312 1313 st->spi = spi; 1314 st->dev = &spi->dev; 1315 st->chip_info = device_get_match_data(&spi->dev); 1316 if (!st->chip_info) { 1317 const struct spi_device_id *id = spi_get_device_id(spi); 1318 1319 if (id) 1320 st->chip_info = 1321 (struct ad74413r_chip_info *)id->driver_data; 1322 if (!st->chip_info) 1323 return -EINVAL; 1324 } 1325 1326 mutex_init(&st->lock); 1327 init_completion(&st->adc_data_completion); 1328 1329 st->regmap = devm_regmap_init(st->dev, NULL, st, 1330 &ad74413r_regmap_config); 1331 if (IS_ERR(st->regmap)) 1332 return PTR_ERR(st->regmap); 1333 1334 st->reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 1335 if (IS_ERR(st->reset_gpio)) 1336 return PTR_ERR(st->reset_gpio); 1337 1338 st->refin_reg = devm_regulator_get(st->dev, "refin"); 1339 if (IS_ERR(st->refin_reg)) 1340 return dev_err_probe(st->dev, PTR_ERR(st->refin_reg), 1341 "Failed to get refin regulator\n"); 1342 1343 ret = regulator_enable(st->refin_reg); 1344 if (ret) 1345 return ret; 1346 1347 ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable, 1348 st->refin_reg); 1349 if (ret) 1350 return ret; 1351 1352 st->sense_resistor_ohms = 100000000; 1353 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms", 1354 &st->sense_resistor_ohms); 1355 st->sense_resistor_ohms /= 1000000; 1356 1357 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d", 1358 st->chip_info->name, iio_device_id(indio_dev)); 1359 if (!st->trig) 1360 return -ENOMEM; 1361 1362 st->trig->ops = &ad74413r_trigger_ops; 1363 iio_trigger_set_drvdata(st->trig, st); 1364 1365 ret = devm_iio_trigger_register(st->dev, st->trig); 1366 if (ret) 1367 return ret; 1368 1369 indio_dev->name = st->chip_info->name; 1370 indio_dev->modes = INDIO_DIRECT_MODE; 1371 indio_dev->info = &ad74413r_info; 1372 indio_dev->trig = iio_trigger_get(st->trig); 1373 1374 ret = ad74413r_reset(st); 1375 if (ret) 1376 return ret; 1377 1378 ret = ad74413r_parse_channel_configs(indio_dev); 1379 if (ret) 1380 return ret; 1381 1382 ret = ad74413r_setup_channels(indio_dev); 1383 if (ret) 1384 return ret; 1385 1386 ret = ad74413r_setup_gpios(st); 1387 if (ret) 1388 return ret; 1389 1390 if (st->num_gpo_gpios) { 1391 st->gpo_gpiochip.owner = THIS_MODULE; 1392 st->gpo_gpiochip.label = st->chip_info->name; 1393 st->gpo_gpiochip.base = -1; 1394 st->gpo_gpiochip.ngpio = st->num_gpo_gpios; 1395 st->gpo_gpiochip.parent = st->dev; 1396 st->gpo_gpiochip.can_sleep = true; 1397 st->gpo_gpiochip.set = ad74413r_gpio_set; 1398 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple; 1399 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config; 1400 st->gpo_gpiochip.get_direction = 1401 ad74413r_gpio_get_gpo_direction; 1402 1403 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st); 1404 if (ret) 1405 return ret; 1406 } 1407 1408 if (st->num_comparator_gpios) { 1409 st->comp_gpiochip.owner = THIS_MODULE; 1410 st->comp_gpiochip.label = st->chip_info->name; 1411 st->comp_gpiochip.base = -1; 1412 st->comp_gpiochip.ngpio = st->num_comparator_gpios; 1413 st->comp_gpiochip.parent = st->dev; 1414 st->comp_gpiochip.can_sleep = true; 1415 st->comp_gpiochip.get = ad74413r_gpio_get; 1416 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple; 1417 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config; 1418 st->comp_gpiochip.get_direction = 1419 ad74413r_gpio_get_comp_direction; 1420 1421 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st); 1422 if (ret) 1423 return ret; 1424 } 1425 1426 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 1427 if (ret) 1428 return ret; 1429 1430 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt, 1431 0, st->chip_info->name, indio_dev); 1432 if (ret) 1433 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1434 1435 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev, 1436 &iio_pollfunc_store_time, 1437 &ad74413r_trigger_handler, 1438 &ad74413r_buffer_ops); 1439 if (ret) 1440 return ret; 1441 1442 return devm_iio_device_register(st->dev, indio_dev); 1443 } 1444 1445 static int ad74413r_unregister_driver(struct spi_driver *spi) 1446 { 1447 spi_unregister_driver(spi); 1448 1449 return 0; 1450 } 1451 1452 static int __init ad74413r_register_driver(struct spi_driver *spi) 1453 { 1454 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL); 1455 1456 return spi_register_driver(spi); 1457 } 1458 1459 static const struct ad74413r_chip_info ad74412r_chip_info_data = { 1460 .hart_support = false, 1461 .name = "ad74412r", 1462 }; 1463 1464 static const struct ad74413r_chip_info ad74413r_chip_info_data = { 1465 .hart_support = true, 1466 .name = "ad74413r", 1467 }; 1468 1469 static const struct of_device_id ad74413r_dt_id[] = { 1470 { 1471 .compatible = "adi,ad74412r", 1472 .data = &ad74412r_chip_info_data, 1473 }, 1474 { 1475 .compatible = "adi,ad74413r", 1476 .data = &ad74413r_chip_info_data, 1477 }, 1478 {}, 1479 }; 1480 MODULE_DEVICE_TABLE(of, ad74413r_dt_id); 1481 1482 static const struct spi_device_id ad74413r_spi_id[] = { 1483 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data }, 1484 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data }, 1485 {} 1486 }; 1487 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id); 1488 1489 static struct spi_driver ad74413r_driver = { 1490 .driver = { 1491 .name = "ad74413r", 1492 .of_match_table = ad74413r_dt_id, 1493 }, 1494 .probe = ad74413r_probe, 1495 .id_table = ad74413r_spi_id, 1496 }; 1497 1498 module_driver(ad74413r_driver, 1499 ad74413r_register_driver, 1500 ad74413r_unregister_driver); 1501 1502 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1503 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC"); 1504 MODULE_LICENSE("GPL v2"); 1505