1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <asm/unaligned.h> 8 #include <linux/bitfield.h> 9 #include <linux/crc8.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/trigger_consumer.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/interrupt.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/spi/spi.h> 25 26 #include <dt-bindings/iio/addac/adi,ad74413r.h> 27 28 #define AD74413R_CRC_POLYNOMIAL 0x7 29 DECLARE_CRC8_TABLE(ad74413r_crc8_table); 30 31 #define AD74413R_CHANNEL_MAX 4 32 33 #define AD74413R_FRAME_SIZE 4 34 35 struct ad74413r_chip_info { 36 const char *name; 37 bool hart_support; 38 }; 39 40 struct ad74413r_channel_config { 41 u32 func; 42 bool gpo_comparator; 43 bool initialized; 44 }; 45 46 struct ad74413r_channels { 47 struct iio_chan_spec *channels; 48 unsigned int num_channels; 49 }; 50 51 struct ad74413r_state { 52 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX]; 53 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX]; 54 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX]; 55 struct gpio_chip gpo_gpiochip; 56 struct gpio_chip comp_gpiochip; 57 struct completion adc_data_completion; 58 unsigned int num_gpo_gpios; 59 unsigned int num_comparator_gpios; 60 u32 sense_resistor_ohms; 61 62 /* 63 * Synchronize consecutive operations when doing a one-shot 64 * conversion and when updating the ADC samples SPI message. 65 */ 66 struct mutex lock; 67 68 const struct ad74413r_chip_info *chip_info; 69 struct spi_device *spi; 70 struct regulator *refin_reg; 71 struct regmap *regmap; 72 struct device *dev; 73 struct iio_trigger *trig; 74 75 size_t adc_active_channels; 76 struct spi_message adc_samples_msg; 77 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; 78 79 /* 80 * DMA (thus cache coherency maintenance) requires the 81 * transfer buffers to live in their own cache lines. 82 */ 83 struct { 84 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 85 s64 timestamp; 86 } adc_samples_buf ____cacheline_aligned; 87 88 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 89 u8 reg_tx_buf[AD74413R_FRAME_SIZE]; 90 u8 reg_rx_buf[AD74413R_FRAME_SIZE]; 91 }; 92 93 #define AD74413R_REG_NOP 0x00 94 95 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x)) 96 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0) 97 98 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x)) 99 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5) 100 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3) 101 #define AD74413R_ADC_RANGE_10V 0b000 102 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001 103 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010 104 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011 105 #define AD74413R_ADC_REJECTION_50_60 0b00 106 #define AD74413R_ADC_REJECTION_NONE 0b01 107 #define AD74413R_ADC_REJECTION_50_60_HART 0b10 108 #define AD74413R_ADC_REJECTION_HART 0b11 109 110 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x)) 111 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0) 112 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5) 113 114 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x)) 115 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0) 116 #define AD74413R_DAC_VOLTAGE_MAX 11000 117 118 #define AD74413R_REG_GPO_PAR_DATA 0x0d 119 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x)) 120 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3) 121 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0) 122 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000 123 #define AD74413R_GPO_CONFIG_LOGIC 0b001 124 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010 125 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011 126 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100 127 128 #define AD74413R_REG_ADC_CONV_CTRL 0x23 129 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8) 130 #define AD74413R_CONV_SEQ_ON 0b00 131 #define AD74413R_CONV_SEQ_SINGLE 0b01 132 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10 133 #define AD74413R_CONV_SEQ_OFF 0b11 134 #define AD74413R_CH_EN_MASK(x) BIT(x) 135 136 #define AD74413R_REG_DIN_COMP_OUT 0x25 137 138 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x)) 139 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0) 140 141 #define AD74413R_REG_READ_SELECT 0x41 142 143 #define AD74413R_REG_CMD_KEY 0x44 144 #define AD74413R_CMD_KEY_LDAC 0x953a 145 #define AD74413R_CMD_KEY_RESET1 0x15fa 146 #define AD74413R_CMD_KEY_RESET2 0xaf51 147 148 static const int ad74413r_adc_sampling_rates[] = { 149 20, 4800, 150 }; 151 152 static const int ad74413r_adc_sampling_rates_hart[] = { 153 10, 20, 1200, 4800, 154 }; 155 156 static int ad74413r_crc(u8 *buf) 157 { 158 return crc8(ad74413r_crc8_table, buf, 3, 0); 159 } 160 161 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf) 162 { 163 buf[0] = reg; 164 put_unaligned_be16(val, &buf[1]); 165 buf[3] = ad74413r_crc(buf); 166 } 167 168 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val) 169 { 170 struct ad74413r_state *st = context; 171 172 ad74413r_format_reg_write(reg, val, st->reg_tx_buf); 173 174 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); 175 } 176 177 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf) 178 { 179 u8 expected_crc = ad74413r_crc(buf); 180 181 if (buf[3] != expected_crc) { 182 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", 183 buf[3], buf[0], buf[1], buf[2]); 184 return -EINVAL; 185 } 186 187 return 0; 188 } 189 190 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val) 191 { 192 struct ad74413r_state *st = context; 193 struct spi_transfer reg_read_xfer[] = { 194 { 195 .tx_buf = st->reg_tx_buf, 196 .len = AD74413R_FRAME_SIZE, 197 .cs_change = 1, 198 }, 199 { 200 .rx_buf = st->reg_rx_buf, 201 .len = AD74413R_FRAME_SIZE, 202 }, 203 }; 204 int ret; 205 206 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg, 207 st->reg_tx_buf); 208 209 ret = spi_sync_transfer(st->spi, reg_read_xfer, 210 ARRAY_SIZE(reg_read_xfer)); 211 if (ret) 212 return ret; 213 214 ret = ad74413r_crc_check(st, st->reg_rx_buf); 215 if (ret) 216 return ret; 217 218 *val = get_unaligned_be16(&st->reg_rx_buf[1]); 219 220 return 0; 221 } 222 223 static const struct regmap_config ad74413r_regmap_config = { 224 .reg_bits = 8, 225 .val_bits = 16, 226 .reg_read = ad74413r_reg_read, 227 .reg_write = ad74413r_reg_write, 228 }; 229 230 static int ad74413r_set_gpo_config(struct ad74413r_state *st, 231 unsigned int offset, u8 mode) 232 { 233 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset), 234 AD74413R_GPO_CONFIG_SELECT_MASK, mode); 235 } 236 237 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = { 238 0, 13, 18, 24, 32, 42, 56, 75, 239 100, 130, 180, 240, 320, 420, 560, 750, 240 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500, 241 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000, 242 }; 243 244 static int ad74413r_set_comp_debounce(struct ad74413r_state *st, 245 unsigned int offset, 246 unsigned int debounce) 247 { 248 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1; 249 unsigned int i; 250 251 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++) 252 if (debounce <= ad74413r_debounce_map[i]) { 253 val = i; 254 break; 255 } 256 257 return regmap_update_bits(st->regmap, 258 AD74413R_REG_DIN_CONFIG_X(offset), 259 AD74413R_DIN_DEBOUNCE_MASK, 260 val); 261 } 262 263 static void ad74413r_gpio_set(struct gpio_chip *chip, 264 unsigned int offset, int val) 265 { 266 struct ad74413r_state *st = gpiochip_get_data(chip); 267 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 268 int ret; 269 270 ret = ad74413r_set_gpo_config(st, real_offset, 271 AD74413R_GPO_CONFIG_LOGIC); 272 if (ret) 273 return; 274 275 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset), 276 AD74413R_GPO_CONFIG_DATA_MASK, 277 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0); 278 } 279 280 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip, 281 unsigned long *mask, 282 unsigned long *bits) 283 { 284 struct ad74413r_state *st = gpiochip_get_data(chip); 285 unsigned long real_mask = 0; 286 unsigned long real_bits = 0; 287 unsigned int offset = 0; 288 int ret; 289 290 for_each_set_bit_from(offset, mask, chip->ngpio) { 291 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 292 293 ret = ad74413r_set_gpo_config(st, real_offset, 294 AD74413R_GPO_CONFIG_LOGIC_PARALLEL); 295 if (ret) 296 return; 297 298 real_mask |= BIT(real_offset); 299 if (*bits & offset) 300 real_bits |= BIT(real_offset); 301 } 302 303 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA, 304 real_mask, real_bits); 305 } 306 307 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset) 308 { 309 struct ad74413r_state *st = gpiochip_get_data(chip); 310 unsigned int real_offset = st->comp_gpio_offsets[offset]; 311 unsigned int status; 312 int ret; 313 314 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status); 315 if (ret) 316 return ret; 317 318 status &= BIT(real_offset); 319 320 return status ? 1 : 0; 321 } 322 323 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, 324 unsigned long *mask, 325 unsigned long *bits) 326 { 327 struct ad74413r_state *st = gpiochip_get_data(chip); 328 unsigned int offset = 0; 329 unsigned int val; 330 int ret; 331 332 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val); 333 if (ret) 334 return ret; 335 336 for_each_set_bit_from(offset, mask, chip->ngpio) { 337 unsigned int real_offset = st->comp_gpio_offsets[offset]; 338 339 __assign_bit(offset, bits, val & BIT(real_offset)); 340 } 341 342 return ret; 343 } 344 345 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip, 346 unsigned int offset) 347 { 348 return GPIO_LINE_DIRECTION_OUT; 349 } 350 351 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip, 352 unsigned int offset) 353 { 354 return GPIO_LINE_DIRECTION_IN; 355 } 356 357 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip, 358 unsigned int offset, 359 unsigned long config) 360 { 361 struct ad74413r_state *st = gpiochip_get_data(chip); 362 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 363 364 switch (pinconf_to_config_param(config)) { 365 case PIN_CONFIG_BIAS_PULL_DOWN: 366 return ad74413r_set_gpo_config(st, real_offset, 367 AD74413R_GPO_CONFIG_100K_PULL_DOWN); 368 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 369 return ad74413r_set_gpo_config(st, real_offset, 370 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE); 371 default: 372 return -ENOTSUPP; 373 } 374 } 375 376 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip, 377 unsigned int offset, 378 unsigned long config) 379 { 380 struct ad74413r_state *st = gpiochip_get_data(chip); 381 unsigned int real_offset = st->comp_gpio_offsets[offset]; 382 383 switch (pinconf_to_config_param(config)) { 384 case PIN_CONFIG_INPUT_DEBOUNCE: 385 return ad74413r_set_comp_debounce(st, real_offset, 386 pinconf_to_config_argument(config)); 387 default: 388 return -ENOTSUPP; 389 } 390 } 391 392 static int ad74413r_reset(struct ad74413r_state *st) 393 { 394 int ret; 395 396 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 397 AD74413R_CMD_KEY_RESET1); 398 if (ret) 399 return ret; 400 401 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 402 AD74413R_CMD_KEY_RESET2); 403 } 404 405 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st, 406 unsigned int channel, int dac_code) 407 { 408 struct reg_sequence reg_seq[2] = { 409 { AD74413R_REG_DAC_CODE_X(channel), dac_code }, 410 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC }, 411 }; 412 413 return regmap_multi_reg_write(st->regmap, reg_seq, 2); 414 } 415 416 static int ad74413r_set_channel_function(struct ad74413r_state *st, 417 unsigned int channel, u8 func) 418 { 419 return regmap_update_bits(st->regmap, 420 AD74413R_REG_CH_FUNC_SETUP_X(channel), 421 AD74413R_CH_FUNC_SETUP_MASK, func); 422 } 423 424 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st, 425 unsigned int status) 426 { 427 int ret; 428 429 /* 430 * These bits do not clear when a conversion completes. 431 * To enable a subsequent conversion, repeat the write. 432 */ 433 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 434 AD74413R_CONV_SEQ_MASK, 435 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status)); 436 if (ret) 437 return ret; 438 439 /* 440 * Wait 100us before starting conversions. 441 */ 442 usleep_range(100, 120); 443 444 return 0; 445 } 446 447 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st, 448 unsigned int channel, 449 bool status) 450 { 451 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 452 AD74413R_CH_EN_MASK(channel), 453 status ? AD74413R_CH_EN_MASK(channel) : 0); 454 } 455 456 static int ad74413r_get_adc_range(struct ad74413r_state *st, 457 unsigned int channel, 458 unsigned int *val) 459 { 460 int ret; 461 462 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 463 if (ret) 464 return ret; 465 466 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val); 467 468 return 0; 469 } 470 471 static int ad74413r_get_adc_rejection(struct ad74413r_state *st, 472 unsigned int channel, 473 unsigned int *val) 474 { 475 int ret; 476 477 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 478 if (ret) 479 return ret; 480 481 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val); 482 483 return 0; 484 } 485 486 static int ad74413r_set_adc_rejection(struct ad74413r_state *st, 487 unsigned int channel, 488 unsigned int val) 489 { 490 return regmap_update_bits(st->regmap, 491 AD74413R_REG_ADC_CONFIG_X(channel), 492 AD74413R_ADC_CONFIG_REJECTION_MASK, 493 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK, 494 val)); 495 } 496 497 static int ad74413r_rejection_to_rate(struct ad74413r_state *st, 498 unsigned int rej, int *val) 499 { 500 switch (rej) { 501 case AD74413R_ADC_REJECTION_50_60: 502 *val = 20; 503 return 0; 504 case AD74413R_ADC_REJECTION_NONE: 505 *val = 4800; 506 return 0; 507 case AD74413R_ADC_REJECTION_50_60_HART: 508 *val = 10; 509 return 0; 510 case AD74413R_ADC_REJECTION_HART: 511 *val = 1200; 512 return 0; 513 default: 514 dev_err(st->dev, "ADC rejection invalid\n"); 515 return -EINVAL; 516 } 517 } 518 519 static int ad74413r_rate_to_rejection(struct ad74413r_state *st, 520 int rate, unsigned int *val) 521 { 522 switch (rate) { 523 case 20: 524 *val = AD74413R_ADC_REJECTION_50_60; 525 return 0; 526 case 4800: 527 *val = AD74413R_ADC_REJECTION_NONE; 528 return 0; 529 case 10: 530 *val = AD74413R_ADC_REJECTION_50_60_HART; 531 return 0; 532 case 1200: 533 *val = AD74413R_ADC_REJECTION_HART; 534 return 0; 535 default: 536 dev_err(st->dev, "ADC rate invalid\n"); 537 return -EINVAL; 538 } 539 } 540 541 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st, 542 unsigned int range, int *val) 543 { 544 switch (range) { 545 case AD74413R_ADC_RANGE_10V: 546 *val = 10000; 547 return 0; 548 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 549 case AD74413R_ADC_RANGE_2P5V_INT_POW: 550 *val = 2500; 551 return 0; 552 case AD74413R_ADC_RANGE_5V_BI_DIR: 553 *val = 5000; 554 return 0; 555 default: 556 dev_err(st->dev, "ADC range invalid\n"); 557 return -EINVAL; 558 } 559 } 560 561 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st, 562 unsigned int range, int *val) 563 { 564 switch (range) { 565 case AD74413R_ADC_RANGE_10V: 566 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 567 *val = 0; 568 return 0; 569 case AD74413R_ADC_RANGE_2P5V_INT_POW: 570 case AD74413R_ADC_RANGE_5V_BI_DIR: 571 *val = -2500; 572 return 0; 573 default: 574 dev_err(st->dev, "ADC range invalid\n"); 575 return -EINVAL; 576 } 577 } 578 579 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st, 580 unsigned int range, int *val) 581 { 582 switch (range) { 583 case AD74413R_ADC_RANGE_10V: 584 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 585 *val = 0; 586 return 0; 587 case AD74413R_ADC_RANGE_2P5V_INT_POW: 588 *val = -((int)AD74413R_ADC_RESULT_MAX); 589 return 0; 590 case AD74413R_ADC_RANGE_5V_BI_DIR: 591 *val = -((int)AD74413R_ADC_RESULT_MAX / 2); 592 return 0; 593 default: 594 dev_err(st->dev, "ADC range invalid\n"); 595 return -EINVAL; 596 } 597 } 598 599 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st, 600 int *val, int *val2) 601 { 602 *val = AD74413R_DAC_VOLTAGE_MAX; 603 *val2 = AD74413R_DAC_CODE_MAX; 604 605 return IIO_VAL_FRACTIONAL; 606 } 607 608 static int ad74413r_get_output_current_scale(struct ad74413r_state *st, 609 int *val, int *val2) 610 { 611 *val = regulator_get_voltage(st->refin_reg); 612 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000; 613 614 return IIO_VAL_FRACTIONAL; 615 } 616 617 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st, 618 unsigned int channel, 619 int *val, int *val2) 620 { 621 unsigned int range; 622 int ret; 623 624 ret = ad74413r_get_adc_range(st, channel, &range); 625 if (ret) 626 return ret; 627 628 ret = ad74413r_range_to_voltage_range(st, range, val); 629 if (ret) 630 return ret; 631 632 *val2 = AD74413R_ADC_RESULT_MAX; 633 634 return IIO_VAL_FRACTIONAL; 635 } 636 637 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st, 638 unsigned int channel, int *val) 639 { 640 unsigned int range; 641 int ret; 642 643 ret = ad74413r_get_adc_range(st, channel, &range); 644 if (ret) 645 return ret; 646 647 ret = ad74413r_range_to_voltage_offset_raw(st, range, val); 648 if (ret) 649 return ret; 650 651 return IIO_VAL_INT; 652 } 653 654 static int ad74413r_get_input_current_scale(struct ad74413r_state *st, 655 unsigned int channel, int *val, 656 int *val2) 657 { 658 unsigned int range; 659 int ret; 660 661 ret = ad74413r_get_adc_range(st, channel, &range); 662 if (ret) 663 return ret; 664 665 ret = ad74413r_range_to_voltage_range(st, range, val); 666 if (ret) 667 return ret; 668 669 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms; 670 671 return IIO_VAL_FRACTIONAL; 672 } 673 674 static int ad74413_get_input_current_offset(struct ad74413r_state *st, 675 unsigned int channel, int *val) 676 { 677 unsigned int range; 678 int voltage_range; 679 int voltage_offset; 680 int ret; 681 682 ret = ad74413r_get_adc_range(st, channel, &range); 683 if (ret) 684 return ret; 685 686 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range); 687 if (ret) 688 return ret; 689 690 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset); 691 if (ret) 692 return ret; 693 694 *val = voltage_offset * AD74413R_ADC_RESULT_MAX / voltage_range; 695 696 return IIO_VAL_INT; 697 } 698 699 static int ad74413r_get_adc_rate(struct ad74413r_state *st, 700 unsigned int channel, int *val) 701 { 702 unsigned int rejection; 703 int ret; 704 705 ret = ad74413r_get_adc_rejection(st, channel, &rejection); 706 if (ret) 707 return ret; 708 709 ret = ad74413r_rejection_to_rate(st, rejection, val); 710 if (ret) 711 return ret; 712 713 return IIO_VAL_INT; 714 } 715 716 static int ad74413r_set_adc_rate(struct ad74413r_state *st, 717 unsigned int channel, int val) 718 { 719 unsigned int rejection; 720 int ret; 721 722 ret = ad74413r_rate_to_rejection(st, val, &rejection); 723 if (ret) 724 return ret; 725 726 return ad74413r_set_adc_rejection(st, channel, rejection); 727 } 728 729 static irqreturn_t ad74413r_trigger_handler(int irq, void *p) 730 { 731 struct iio_poll_func *pf = p; 732 struct iio_dev *indio_dev = pf->indio_dev; 733 struct ad74413r_state *st = iio_priv(indio_dev); 734 u8 *rx_buf = st->adc_samples_buf.rx_buf; 735 unsigned int i; 736 int ret; 737 738 ret = spi_sync(st->spi, &st->adc_samples_msg); 739 if (ret) 740 goto out; 741 742 for (i = 0; i < st->adc_active_channels; i++) 743 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]); 744 745 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf, 746 iio_get_time_ns(indio_dev)); 747 748 out: 749 iio_trigger_notify_done(indio_dev->trig); 750 751 return IRQ_HANDLED; 752 } 753 754 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data) 755 { 756 struct iio_dev *indio_dev = data; 757 struct ad74413r_state *st = iio_priv(indio_dev); 758 759 if (iio_buffer_enabled(indio_dev)) 760 iio_trigger_poll(st->trig); 761 else 762 complete(&st->adc_data_completion); 763 764 return IRQ_HANDLED; 765 } 766 767 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st, 768 unsigned int channel, int *val) 769 { 770 unsigned int uval; 771 int ret; 772 773 reinit_completion(&st->adc_data_completion); 774 775 ret = ad74413r_set_adc_channel_enable(st, channel, true); 776 if (ret) 777 return ret; 778 779 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE); 780 if (ret) 781 return ret; 782 783 ret = wait_for_completion_timeout(&st->adc_data_completion, 784 msecs_to_jiffies(1000)); 785 if (!ret) { 786 ret = -ETIMEDOUT; 787 return ret; 788 } 789 790 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel), 791 &uval); 792 if (ret) 793 return ret; 794 795 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 796 if (ret) 797 return ret; 798 799 ret = ad74413r_set_adc_channel_enable(st, channel, false); 800 if (ret) 801 return ret; 802 803 *val = uval; 804 805 return IIO_VAL_INT; 806 } 807 808 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev, 809 unsigned int channel, int *val) 810 { 811 struct ad74413r_state *st = iio_priv(indio_dev); 812 int ret; 813 814 ret = iio_device_claim_direct_mode(indio_dev); 815 if (ret) 816 return ret; 817 818 mutex_lock(&st->lock); 819 ret = _ad74413r_get_single_adc_result(st, channel, val); 820 mutex_unlock(&st->lock); 821 822 iio_device_release_direct_mode(indio_dev); 823 824 return ret; 825 } 826 827 static void ad74413r_adc_to_resistance_result(int adc_result, int *val) 828 { 829 if (adc_result == AD74413R_ADC_RESULT_MAX) 830 adc_result = AD74413R_ADC_RESULT_MAX - 1; 831 832 *val = DIV_ROUND_CLOSEST(adc_result * 2100, 833 AD74413R_ADC_RESULT_MAX - adc_result); 834 } 835 836 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev, 837 const unsigned long *active_scan_mask) 838 { 839 struct ad74413r_state *st = iio_priv(indio_dev); 840 struct spi_transfer *xfer = st->adc_samples_xfer; 841 u8 *rx_buf = st->adc_samples_buf.rx_buf; 842 u8 *tx_buf = st->adc_samples_tx_buf; 843 unsigned int channel; 844 int ret = -EINVAL; 845 846 mutex_lock(&st->lock); 847 848 spi_message_init(&st->adc_samples_msg); 849 st->adc_active_channels = 0; 850 851 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 852 ret = ad74413r_set_adc_channel_enable(st, channel, false); 853 if (ret) 854 goto out; 855 } 856 857 if (*active_scan_mask == 0) 858 goto out; 859 860 /* 861 * The read select register is used to select which register's value 862 * will be sent by the slave on the next SPI frame. 863 * 864 * Create an SPI message that, on each step, writes to the read select 865 * register to select the ADC result of the next enabled channel, and 866 * reads the ADC result of the previous enabled channel. 867 * 868 * Example: 869 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ] 870 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4] 871 */ 872 873 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 874 ret = ad74413r_set_adc_channel_enable(st, channel, true); 875 if (ret) 876 goto out; 877 878 st->adc_active_channels++; 879 880 if (xfer == st->adc_samples_xfer) 881 xfer->rx_buf = NULL; 882 else 883 xfer->rx_buf = rx_buf; 884 885 xfer->tx_buf = tx_buf; 886 xfer->len = AD74413R_FRAME_SIZE; 887 xfer->cs_change = 1; 888 889 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, 890 AD74413R_REG_ADC_RESULT_X(channel), 891 tx_buf); 892 893 spi_message_add_tail(xfer, &st->adc_samples_msg); 894 895 tx_buf += AD74413R_FRAME_SIZE; 896 if (xfer != st->adc_samples_xfer) 897 rx_buf += AD74413R_FRAME_SIZE; 898 xfer++; 899 } 900 901 xfer->rx_buf = rx_buf; 902 xfer->tx_buf = NULL; 903 xfer->len = AD74413R_FRAME_SIZE; 904 xfer->cs_change = 0; 905 906 spi_message_add_tail(xfer, &st->adc_samples_msg); 907 908 out: 909 mutex_unlock(&st->lock); 910 911 return ret; 912 } 913 914 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev) 915 { 916 struct ad74413r_state *st = iio_priv(indio_dev); 917 918 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS); 919 } 920 921 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev) 922 { 923 struct ad74413r_state *st = iio_priv(indio_dev); 924 925 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 926 } 927 928 static int ad74413r_read_raw(struct iio_dev *indio_dev, 929 struct iio_chan_spec const *chan, 930 int *val, int *val2, long info) 931 { 932 struct ad74413r_state *st = iio_priv(indio_dev); 933 934 switch (info) { 935 case IIO_CHAN_INFO_SCALE: 936 switch (chan->type) { 937 case IIO_VOLTAGE: 938 if (chan->output) 939 return ad74413r_get_output_voltage_scale(st, 940 val, val2); 941 else 942 return ad74413r_get_input_voltage_scale(st, 943 chan->channel, val, val2); 944 case IIO_CURRENT: 945 if (chan->output) 946 return ad74413r_get_output_current_scale(st, 947 val, val2); 948 else 949 return ad74413r_get_input_current_scale(st, 950 chan->channel, val, val2); 951 default: 952 return -EINVAL; 953 } 954 case IIO_CHAN_INFO_OFFSET: 955 switch (chan->type) { 956 case IIO_VOLTAGE: 957 return ad74413r_get_input_voltage_offset(st, 958 chan->channel, val); 959 case IIO_CURRENT: 960 return ad74413_get_input_current_offset(st, 961 chan->channel, val); 962 default: 963 return -EINVAL; 964 } 965 case IIO_CHAN_INFO_RAW: 966 if (chan->output) 967 return -EINVAL; 968 969 return ad74413r_get_single_adc_result(indio_dev, chan->channel, 970 val); 971 case IIO_CHAN_INFO_PROCESSED: { 972 int ret; 973 974 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel, 975 val); 976 if (ret) 977 return ret; 978 979 ad74413r_adc_to_resistance_result(*val, val); 980 981 return ret; 982 } 983 case IIO_CHAN_INFO_SAMP_FREQ: 984 return ad74413r_get_adc_rate(st, chan->channel, val); 985 default: 986 return -EINVAL; 987 } 988 } 989 990 static int ad74413r_write_raw(struct iio_dev *indio_dev, 991 struct iio_chan_spec const *chan, 992 int val, int val2, long info) 993 { 994 struct ad74413r_state *st = iio_priv(indio_dev); 995 996 switch (info) { 997 case IIO_CHAN_INFO_RAW: 998 if (!chan->output) 999 return -EINVAL; 1000 1001 if (val < 0 || val > AD74413R_DAC_CODE_MAX) { 1002 dev_err(st->dev, "Invalid DAC code\n"); 1003 return -EINVAL; 1004 } 1005 1006 return ad74413r_set_channel_dac_code(st, chan->channel, val); 1007 case IIO_CHAN_INFO_SAMP_FREQ: 1008 return ad74413r_set_adc_rate(st, chan->channel, val); 1009 default: 1010 return -EINVAL; 1011 } 1012 } 1013 1014 static int ad74413r_read_avail(struct iio_dev *indio_dev, 1015 struct iio_chan_spec const *chan, 1016 const int **vals, int *type, int *length, 1017 long info) 1018 { 1019 struct ad74413r_state *st = iio_priv(indio_dev); 1020 1021 switch (info) { 1022 case IIO_CHAN_INFO_SAMP_FREQ: 1023 if (st->chip_info->hart_support) { 1024 *vals = ad74413r_adc_sampling_rates_hart; 1025 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart); 1026 } else { 1027 *vals = ad74413r_adc_sampling_rates; 1028 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates); 1029 } 1030 *type = IIO_VAL_INT; 1031 return IIO_AVAIL_LIST; 1032 default: 1033 return -EINVAL; 1034 } 1035 } 1036 1037 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = { 1038 .postenable = &ad74413r_buffer_postenable, 1039 .predisable = &ad74413r_buffer_predisable, 1040 }; 1041 1042 static const struct iio_trigger_ops ad74413r_trigger_ops = { 1043 .validate_device = iio_trigger_validate_own_device, 1044 }; 1045 1046 static const struct iio_info ad74413r_info = { 1047 .read_raw = &ad74413r_read_raw, 1048 .write_raw = &ad74413r_write_raw, 1049 .read_avail = &ad74413r_read_avail, 1050 .update_scan_mode = &ad74413r_update_scan_mode, 1051 }; 1052 1053 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \ 1054 { \ 1055 .type = (_type), \ 1056 .indexed = 1, \ 1057 .output = 1, \ 1058 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1059 | (extra_mask_separate), \ 1060 } 1061 1062 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \ 1063 { \ 1064 .type = (_type), \ 1065 .indexed = 1, \ 1066 .output = 0, \ 1067 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1068 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 1069 | (extra_mask_separate), \ 1070 .info_mask_separate_available = \ 1071 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1072 .scan_type = { \ 1073 .sign = 'u', \ 1074 .realbits = 16, \ 1075 .storagebits = 32, \ 1076 .shift = 8, \ 1077 .endianness = IIO_BE, \ 1078 }, \ 1079 } 1080 1081 #define AD74413R_ADC_VOLTAGE_CHANNEL \ 1082 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \ 1083 | BIT(IIO_CHAN_INFO_OFFSET)) 1084 1085 #define AD74413R_ADC_CURRENT_CHANNEL \ 1086 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \ 1087 | BIT(IIO_CHAN_INFO_OFFSET)) 1088 1089 static struct iio_chan_spec ad74413r_voltage_output_channels[] = { 1090 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)), 1091 AD74413R_ADC_CURRENT_CHANNEL, 1092 }; 1093 1094 static struct iio_chan_spec ad74413r_current_output_channels[] = { 1095 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)), 1096 AD74413R_ADC_VOLTAGE_CHANNEL, 1097 }; 1098 1099 static struct iio_chan_spec ad74413r_voltage_input_channels[] = { 1100 AD74413R_ADC_VOLTAGE_CHANNEL, 1101 }; 1102 1103 static struct iio_chan_spec ad74413r_current_input_channels[] = { 1104 AD74413R_ADC_CURRENT_CHANNEL, 1105 }; 1106 1107 static struct iio_chan_spec ad74413r_resistance_input_channels[] = { 1108 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)), 1109 }; 1110 1111 static struct iio_chan_spec ad74413r_digital_input_channels[] = { 1112 AD74413R_ADC_VOLTAGE_CHANNEL, 1113 }; 1114 1115 #define _AD74413R_CHANNELS(_channels) \ 1116 { \ 1117 .channels = _channels, \ 1118 .num_channels = ARRAY_SIZE(_channels), \ 1119 } 1120 1121 #define AD74413R_CHANNELS(name) \ 1122 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels) 1123 1124 static const struct ad74413r_channels ad74413r_channels_map[] = { 1125 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input), 1126 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output), 1127 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output), 1128 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input), 1129 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input), 1130 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input), 1131 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input), 1132 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input), 1133 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input), 1134 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input), 1135 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input), 1136 }; 1137 1138 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev, 1139 struct fwnode_handle *channel_node) 1140 { 1141 struct ad74413r_state *st = iio_priv(indio_dev); 1142 struct ad74413r_channel_config *config; 1143 u32 index; 1144 int ret; 1145 1146 ret = fwnode_property_read_u32(channel_node, "reg", &index); 1147 if (ret) { 1148 dev_err(st->dev, "Failed to read channel reg: %d\n", ret); 1149 return ret; 1150 } 1151 1152 if (index >= AD74413R_CHANNEL_MAX) { 1153 dev_err(st->dev, "Channel index %u is too large\n", index); 1154 return -EINVAL; 1155 } 1156 1157 config = &st->channel_configs[index]; 1158 if (config->initialized) { 1159 dev_err(st->dev, "Channel %u already initialized\n", index); 1160 return -EINVAL; 1161 } 1162 1163 config->func = CH_FUNC_HIGH_IMPEDANCE; 1164 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func); 1165 1166 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) { 1167 dev_err(st->dev, "Invalid channel function %u\n", config->func); 1168 return -EINVAL; 1169 } 1170 1171 if (!st->chip_info->hart_support && 1172 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART || 1173 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) { 1174 dev_err(st->dev, "Unsupported HART function %u\n", config->func); 1175 return -EINVAL; 1176 } 1177 1178 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1179 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) 1180 st->num_comparator_gpios++; 1181 1182 config->gpo_comparator = fwnode_property_read_bool(channel_node, 1183 "adi,gpo-comparator"); 1184 1185 if (!config->gpo_comparator) 1186 st->num_gpo_gpios++; 1187 1188 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels; 1189 1190 config->initialized = true; 1191 1192 return 0; 1193 } 1194 1195 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev) 1196 { 1197 struct ad74413r_state *st = iio_priv(indio_dev); 1198 struct fwnode_handle *channel_node = NULL; 1199 int ret; 1200 1201 fwnode_for_each_available_child_node(dev_fwnode(st->dev), channel_node) { 1202 ret = ad74413r_parse_channel_config(indio_dev, channel_node); 1203 if (ret) 1204 goto put_channel_node; 1205 } 1206 1207 return 0; 1208 1209 put_channel_node: 1210 fwnode_handle_put(channel_node); 1211 1212 return ret; 1213 } 1214 1215 static int ad74413r_setup_channels(struct iio_dev *indio_dev) 1216 { 1217 struct ad74413r_state *st = iio_priv(indio_dev); 1218 struct ad74413r_channel_config *config; 1219 struct iio_chan_spec *channels, *chans; 1220 unsigned int i, num_chans, chan_i; 1221 int ret; 1222 1223 channels = devm_kcalloc(st->dev, sizeof(*channels), 1224 indio_dev->num_channels, GFP_KERNEL); 1225 if (!channels) 1226 return -ENOMEM; 1227 1228 indio_dev->channels = channels; 1229 1230 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1231 config = &st->channel_configs[i]; 1232 chans = ad74413r_channels_map[config->func].channels; 1233 num_chans = ad74413r_channels_map[config->func].num_channels; 1234 1235 memcpy(channels, chans, num_chans * sizeof(*chans)); 1236 1237 for (chan_i = 0; chan_i < num_chans; chan_i++) { 1238 struct iio_chan_spec *chan = &channels[chan_i]; 1239 1240 chan->channel = i; 1241 if (chan->output) 1242 chan->scan_index = -1; 1243 else 1244 chan->scan_index = i; 1245 } 1246 1247 ret = ad74413r_set_channel_function(st, i, config->func); 1248 if (ret) 1249 return ret; 1250 1251 channels += num_chans; 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int ad74413r_setup_gpios(struct ad74413r_state *st) 1258 { 1259 struct ad74413r_channel_config *config; 1260 unsigned int comp_gpio_i = 0; 1261 unsigned int gpo_gpio_i = 0; 1262 unsigned int i; 1263 u8 gpo_config; 1264 int ret; 1265 1266 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1267 config = &st->channel_configs[i]; 1268 1269 if (config->gpo_comparator) { 1270 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR; 1271 } else { 1272 gpo_config = AD74413R_GPO_CONFIG_LOGIC; 1273 st->gpo_gpio_offsets[gpo_gpio_i++] = i; 1274 } 1275 1276 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1277 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) 1278 st->comp_gpio_offsets[comp_gpio_i++] = i; 1279 1280 ret = ad74413r_set_gpo_config(st, i, gpo_config); 1281 if (ret) 1282 return ret; 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void ad74413r_regulator_disable(void *regulator) 1289 { 1290 regulator_disable(regulator); 1291 } 1292 1293 static int ad74413r_probe(struct spi_device *spi) 1294 { 1295 struct ad74413r_state *st; 1296 struct iio_dev *indio_dev; 1297 int ret; 1298 1299 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1300 if (!indio_dev) 1301 return -ENOMEM; 1302 1303 st = iio_priv(indio_dev); 1304 1305 st->spi = spi; 1306 st->dev = &spi->dev; 1307 st->chip_info = device_get_match_data(&spi->dev); 1308 mutex_init(&st->lock); 1309 init_completion(&st->adc_data_completion); 1310 1311 st->regmap = devm_regmap_init(st->dev, NULL, st, 1312 &ad74413r_regmap_config); 1313 if (IS_ERR(st->regmap)) 1314 return PTR_ERR(st->regmap); 1315 1316 st->refin_reg = devm_regulator_get(st->dev, "refin"); 1317 if (IS_ERR(st->refin_reg)) 1318 return dev_err_probe(st->dev, PTR_ERR(st->refin_reg), 1319 "Failed to get refin regulator\n"); 1320 1321 ret = regulator_enable(st->refin_reg); 1322 if (ret) 1323 return ret; 1324 1325 ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable, 1326 st->refin_reg); 1327 if (ret) 1328 return ret; 1329 1330 st->sense_resistor_ohms = 100000000; 1331 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms", 1332 &st->sense_resistor_ohms); 1333 st->sense_resistor_ohms /= 1000000; 1334 1335 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d", 1336 st->chip_info->name, iio_device_id(indio_dev)); 1337 if (!st->trig) 1338 return -ENOMEM; 1339 1340 st->trig->ops = &ad74413r_trigger_ops; 1341 iio_trigger_set_drvdata(st->trig, st); 1342 1343 ret = devm_iio_trigger_register(st->dev, st->trig); 1344 if (ret) 1345 return ret; 1346 1347 indio_dev->name = st->chip_info->name; 1348 indio_dev->modes = INDIO_DIRECT_MODE; 1349 indio_dev->info = &ad74413r_info; 1350 indio_dev->trig = iio_trigger_get(st->trig); 1351 1352 ret = ad74413r_reset(st); 1353 if (ret) 1354 return ret; 1355 1356 ret = ad74413r_parse_channel_configs(indio_dev); 1357 if (ret) 1358 return ret; 1359 1360 ret = ad74413r_setup_channels(indio_dev); 1361 if (ret) 1362 return ret; 1363 1364 ret = ad74413r_setup_gpios(st); 1365 if (ret) 1366 return ret; 1367 1368 if (st->num_gpo_gpios) { 1369 st->gpo_gpiochip.owner = THIS_MODULE; 1370 st->gpo_gpiochip.label = st->chip_info->name; 1371 st->gpo_gpiochip.base = -1; 1372 st->gpo_gpiochip.ngpio = st->num_gpo_gpios; 1373 st->gpo_gpiochip.parent = st->dev; 1374 st->gpo_gpiochip.can_sleep = true; 1375 st->gpo_gpiochip.set = ad74413r_gpio_set; 1376 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple; 1377 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config; 1378 st->gpo_gpiochip.get_direction = 1379 ad74413r_gpio_get_gpo_direction; 1380 1381 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st); 1382 if (ret) 1383 return ret; 1384 } 1385 1386 if (st->num_comparator_gpios) { 1387 st->comp_gpiochip.owner = THIS_MODULE; 1388 st->comp_gpiochip.label = st->chip_info->name; 1389 st->comp_gpiochip.base = -1; 1390 st->comp_gpiochip.ngpio = st->num_comparator_gpios; 1391 st->comp_gpiochip.parent = st->dev; 1392 st->comp_gpiochip.can_sleep = true; 1393 st->comp_gpiochip.get = ad74413r_gpio_get; 1394 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple; 1395 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config; 1396 st->comp_gpiochip.get_direction = 1397 ad74413r_gpio_get_comp_direction; 1398 1399 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st); 1400 if (ret) 1401 return ret; 1402 } 1403 1404 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 1405 if (ret) 1406 return ret; 1407 1408 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt, 1409 0, st->chip_info->name, indio_dev); 1410 if (ret) 1411 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1412 1413 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev, 1414 &iio_pollfunc_store_time, 1415 &ad74413r_trigger_handler, 1416 &ad74413r_buffer_ops); 1417 if (ret) 1418 return ret; 1419 1420 return devm_iio_device_register(st->dev, indio_dev); 1421 } 1422 1423 static int ad74413r_unregister_driver(struct spi_driver *spi) 1424 { 1425 spi_unregister_driver(spi); 1426 1427 return 0; 1428 } 1429 1430 static int __init ad74413r_register_driver(struct spi_driver *spi) 1431 { 1432 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL); 1433 1434 return spi_register_driver(spi); 1435 } 1436 1437 static const struct ad74413r_chip_info ad74412r_chip_info_data = { 1438 .hart_support = false, 1439 .name = "ad74412r", 1440 }; 1441 1442 static const struct ad74413r_chip_info ad74413r_chip_info_data = { 1443 .hart_support = true, 1444 .name = "ad74413r", 1445 }; 1446 1447 static const struct of_device_id ad74413r_dt_id[] = { 1448 { 1449 .compatible = "adi,ad74412r", 1450 .data = &ad74412r_chip_info_data, 1451 }, 1452 { 1453 .compatible = "adi,ad74413r", 1454 .data = &ad74413r_chip_info_data, 1455 }, 1456 {}, 1457 }; 1458 MODULE_DEVICE_TABLE(of, ad74413r_dt_id); 1459 1460 static struct spi_driver ad74413r_driver = { 1461 .driver = { 1462 .name = "ad74413r", 1463 .of_match_table = ad74413r_dt_id, 1464 }, 1465 .probe = ad74413r_probe, 1466 }; 1467 1468 module_driver(ad74413r_driver, 1469 ad74413r_register_driver, 1470 ad74413r_unregister_driver); 1471 1472 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1473 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC"); 1474 MODULE_LICENSE("GPL v2"); 1475