1 /* 2 * Xilinx XADC driver 3 * 4 * Copyright 2013 Analog Devices Inc. 5 * Author: Lars-Peter Clauen <lars@metafoo.de> 6 * 7 * Licensed under the GPL-2. 8 */ 9 10 #ifndef __IIO_XILINX_XADC__ 11 #define __IIO_XILINX_XADC__ 12 13 #include <linux/interrupt.h> 14 #include <linux/mutex.h> 15 #include <linux/spinlock.h> 16 17 struct iio_dev; 18 struct clk; 19 struct xadc_ops; 20 struct platform_device; 21 22 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events); 23 24 int xadc_read_event_config(struct iio_dev *indio_dev, 25 const struct iio_chan_spec *chan, enum iio_event_type type, 26 enum iio_event_direction dir); 27 int xadc_write_event_config(struct iio_dev *indio_dev, 28 const struct iio_chan_spec *chan, enum iio_event_type type, 29 enum iio_event_direction dir, int state); 30 int xadc_read_event_value(struct iio_dev *indio_dev, 31 const struct iio_chan_spec *chan, enum iio_event_type type, 32 enum iio_event_direction dir, enum iio_event_info info, 33 int *val, int *val2); 34 int xadc_write_event_value(struct iio_dev *indio_dev, 35 const struct iio_chan_spec *chan, enum iio_event_type type, 36 enum iio_event_direction dir, enum iio_event_info info, 37 int val, int val2); 38 39 enum xadc_external_mux_mode { 40 XADC_EXTERNAL_MUX_NONE, 41 XADC_EXTERNAL_MUX_SINGLE, 42 XADC_EXTERNAL_MUX_DUAL, 43 }; 44 45 struct xadc { 46 void __iomem *base; 47 struct clk *clk; 48 49 const struct xadc_ops *ops; 50 51 uint16_t threshold[16]; 52 uint16_t temp_hysteresis; 53 unsigned int alarm_mask; 54 55 uint16_t *data; 56 57 struct iio_trigger *trigger; 58 struct iio_trigger *convst_trigger; 59 struct iio_trigger *samplerate_trigger; 60 61 enum xadc_external_mux_mode external_mux_mode; 62 63 unsigned int zynq_masked_alarm; 64 unsigned int zynq_intmask; 65 struct delayed_work zynq_unmask_work; 66 67 struct mutex mutex; 68 spinlock_t lock; 69 70 struct completion completion; 71 int irq; 72 }; 73 74 struct xadc_ops { 75 int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val); 76 int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val); 77 int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev, 78 int irq); 79 void (*update_alarm)(struct xadc *xadc, unsigned int alarm); 80 unsigned long (*get_dclk_rate)(struct xadc *xadc); 81 irqreturn_t (*interrupt_handler)(int irq, void *devid); 82 83 unsigned int flags; 84 }; 85 86 static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, 87 uint16_t *val) 88 { 89 lockdep_assert_held(&xadc->mutex); 90 return xadc->ops->read(xadc, reg, val); 91 } 92 93 static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, 94 uint16_t val) 95 { 96 lockdep_assert_held(&xadc->mutex); 97 return xadc->ops->write(xadc, reg, val); 98 } 99 100 static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, 101 uint16_t *val) 102 { 103 int ret; 104 105 mutex_lock(&xadc->mutex); 106 ret = _xadc_read_adc_reg(xadc, reg, val); 107 mutex_unlock(&xadc->mutex); 108 return ret; 109 } 110 111 static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, 112 uint16_t val) 113 { 114 int ret; 115 116 mutex_lock(&xadc->mutex); 117 ret = _xadc_write_adc_reg(xadc, reg, val); 118 mutex_unlock(&xadc->mutex); 119 return ret; 120 } 121 122 /* XADC hardmacro register definitions */ 123 #define XADC_REG_TEMP 0x00 124 #define XADC_REG_VCCINT 0x01 125 #define XADC_REG_VCCAUX 0x02 126 #define XADC_REG_VPVN 0x03 127 #define XADC_REG_VREFP 0x04 128 #define XADC_REG_VREFN 0x05 129 #define XADC_REG_VCCBRAM 0x06 130 131 #define XADC_REG_VCCPINT 0x0d 132 #define XADC_REG_VCCPAUX 0x0e 133 #define XADC_REG_VCCO_DDR 0x0f 134 #define XADC_REG_VAUX(x) (0x10 + (x)) 135 136 #define XADC_REG_MAX_TEMP 0x20 137 #define XADC_REG_MAX_VCCINT 0x21 138 #define XADC_REG_MAX_VCCAUX 0x22 139 #define XADC_REG_MAX_VCCBRAM 0x23 140 #define XADC_REG_MIN_TEMP 0x24 141 #define XADC_REG_MIN_VCCINT 0x25 142 #define XADC_REG_MIN_VCCAUX 0x26 143 #define XADC_REG_MIN_VCCBRAM 0x27 144 #define XADC_REG_MAX_VCCPINT 0x28 145 #define XADC_REG_MAX_VCCPAUX 0x29 146 #define XADC_REG_MAX_VCCO_DDR 0x2a 147 #define XADC_REG_MIN_VCCPINT 0x2c 148 #define XADC_REG_MIN_VCCPAUX 0x2d 149 #define XADC_REG_MIN_VCCO_DDR 0x2e 150 151 #define XADC_REG_CONF0 0x40 152 #define XADC_REG_CONF1 0x41 153 #define XADC_REG_CONF2 0x42 154 #define XADC_REG_SEQ(x) (0x48 + (x)) 155 #define XADC_REG_INPUT_MODE(x) (0x4c + (x)) 156 #define XADC_REG_THRESHOLD(x) (0x50 + (x)) 157 158 #define XADC_REG_FLAG 0x3f 159 160 #define XADC_CONF0_EC BIT(9) 161 #define XADC_CONF0_ACQ BIT(8) 162 #define XADC_CONF0_MUX BIT(11) 163 #define XADC_CONF0_CHAN(x) (x) 164 165 #define XADC_CONF1_SEQ_MASK (0xf << 12) 166 #define XADC_CONF1_SEQ_DEFAULT (0 << 12) 167 #define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12) 168 #define XADC_CONF1_SEQ_CONTINUOUS (2 << 12) 169 #define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12) 170 #define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12) 171 #define XADC_CONF1_SEQ_INDEPENDENT (8 << 12) 172 #define XADC_CONF1_ALARM_MASK 0x0f0f 173 174 #define XADC_CONF2_DIV_MASK 0xff00 175 #define XADC_CONF2_DIV_OFFSET 8 176 177 #define XADC_CONF2_PD_MASK (0x3 << 4) 178 #define XADC_CONF2_PD_NONE (0x0 << 4) 179 #define XADC_CONF2_PD_ADC_B (0x2 << 4) 180 #define XADC_CONF2_PD_BOTH (0x3 << 4) 181 182 #define XADC_ALARM_TEMP_MASK BIT(0) 183 #define XADC_ALARM_VCCINT_MASK BIT(1) 184 #define XADC_ALARM_VCCAUX_MASK BIT(2) 185 #define XADC_ALARM_OT_MASK BIT(3) 186 #define XADC_ALARM_VCCBRAM_MASK BIT(4) 187 #define XADC_ALARM_VCCPINT_MASK BIT(5) 188 #define XADC_ALARM_VCCPAUX_MASK BIT(6) 189 #define XADC_ALARM_VCCODDR_MASK BIT(7) 190 191 #define XADC_THRESHOLD_TEMP_MAX 0x0 192 #define XADC_THRESHOLD_VCCINT_MAX 0x1 193 #define XADC_THRESHOLD_VCCAUX_MAX 0x2 194 #define XADC_THRESHOLD_OT_MAX 0x3 195 #define XADC_THRESHOLD_TEMP_MIN 0x4 196 #define XADC_THRESHOLD_VCCINT_MIN 0x5 197 #define XADC_THRESHOLD_VCCAUX_MIN 0x6 198 #define XADC_THRESHOLD_OT_MIN 0x7 199 #define XADC_THRESHOLD_VCCBRAM_MAX 0x8 200 #define XADC_THRESHOLD_VCCPINT_MAX 0x9 201 #define XADC_THRESHOLD_VCCPAUX_MAX 0xa 202 #define XADC_THRESHOLD_VCCODDR_MAX 0xb 203 #define XADC_THRESHOLD_VCCBRAM_MIN 0xc 204 #define XADC_THRESHOLD_VCCPINT_MIN 0xd 205 #define XADC_THRESHOLD_VCCPAUX_MIN 0xe 206 #define XADC_THRESHOLD_VCCODDR_MIN 0xf 207 208 #endif 209