1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Xilinx XADC driver 4 * 5 * Copyright 2013 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 */ 8 9 #ifndef __IIO_XILINX_XADC__ 10 #define __IIO_XILINX_XADC__ 11 12 #include <linux/interrupt.h> 13 #include <linux/mutex.h> 14 #include <linux/spinlock.h> 15 16 struct iio_dev; 17 struct clk; 18 struct xadc_ops; 19 struct platform_device; 20 21 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events); 22 23 int xadc_read_event_config(struct iio_dev *indio_dev, 24 const struct iio_chan_spec *chan, enum iio_event_type type, 25 enum iio_event_direction dir); 26 int xadc_write_event_config(struct iio_dev *indio_dev, 27 const struct iio_chan_spec *chan, enum iio_event_type type, 28 enum iio_event_direction dir, int state); 29 int xadc_read_event_value(struct iio_dev *indio_dev, 30 const struct iio_chan_spec *chan, enum iio_event_type type, 31 enum iio_event_direction dir, enum iio_event_info info, 32 int *val, int *val2); 33 int xadc_write_event_value(struct iio_dev *indio_dev, 34 const struct iio_chan_spec *chan, enum iio_event_type type, 35 enum iio_event_direction dir, enum iio_event_info info, 36 int val, int val2); 37 38 enum xadc_external_mux_mode { 39 XADC_EXTERNAL_MUX_NONE, 40 XADC_EXTERNAL_MUX_SINGLE, 41 XADC_EXTERNAL_MUX_DUAL, 42 }; 43 44 struct xadc { 45 void __iomem *base; 46 struct clk *clk; 47 48 const struct xadc_ops *ops; 49 50 uint16_t threshold[16]; 51 uint16_t temp_hysteresis; 52 unsigned int alarm_mask; 53 54 uint16_t *data; 55 56 struct iio_trigger *trigger; 57 struct iio_trigger *convst_trigger; 58 struct iio_trigger *samplerate_trigger; 59 60 enum xadc_external_mux_mode external_mux_mode; 61 62 unsigned int zynq_masked_alarm; 63 unsigned int zynq_intmask; 64 struct delayed_work zynq_unmask_work; 65 66 struct mutex mutex; 67 spinlock_t lock; 68 69 struct completion completion; 70 }; 71 72 enum xadc_type { 73 XADC_TYPE_S7, /* Series 7 */ 74 XADC_TYPE_US, /* UltraScale and UltraScale+ */ 75 }; 76 77 struct xadc_ops { 78 int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val); 79 int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val); 80 int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev, 81 int irq); 82 void (*update_alarm)(struct xadc *xadc, unsigned int alarm); 83 unsigned long (*get_dclk_rate)(struct xadc *xadc); 84 irqreturn_t (*interrupt_handler)(int irq, void *devid); 85 86 unsigned int flags; 87 enum xadc_type type; 88 }; 89 90 static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, 91 uint16_t *val) 92 { 93 lockdep_assert_held(&xadc->mutex); 94 return xadc->ops->read(xadc, reg, val); 95 } 96 97 static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, 98 uint16_t val) 99 { 100 lockdep_assert_held(&xadc->mutex); 101 return xadc->ops->write(xadc, reg, val); 102 } 103 104 static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, 105 uint16_t *val) 106 { 107 int ret; 108 109 mutex_lock(&xadc->mutex); 110 ret = _xadc_read_adc_reg(xadc, reg, val); 111 mutex_unlock(&xadc->mutex); 112 return ret; 113 } 114 115 static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, 116 uint16_t val) 117 { 118 int ret; 119 120 mutex_lock(&xadc->mutex); 121 ret = _xadc_write_adc_reg(xadc, reg, val); 122 mutex_unlock(&xadc->mutex); 123 return ret; 124 } 125 126 /* XADC hardmacro register definitions */ 127 #define XADC_REG_TEMP 0x00 128 #define XADC_REG_VCCINT 0x01 129 #define XADC_REG_VCCAUX 0x02 130 #define XADC_REG_VPVN 0x03 131 #define XADC_REG_VREFP 0x04 132 #define XADC_REG_VREFN 0x05 133 #define XADC_REG_VCCBRAM 0x06 134 135 #define XADC_REG_VCCPINT 0x0d 136 #define XADC_REG_VCCPAUX 0x0e 137 #define XADC_REG_VCCO_DDR 0x0f 138 #define XADC_REG_VAUX(x) (0x10 + (x)) 139 140 #define XADC_REG_MAX_TEMP 0x20 141 #define XADC_REG_MAX_VCCINT 0x21 142 #define XADC_REG_MAX_VCCAUX 0x22 143 #define XADC_REG_MAX_VCCBRAM 0x23 144 #define XADC_REG_MIN_TEMP 0x24 145 #define XADC_REG_MIN_VCCINT 0x25 146 #define XADC_REG_MIN_VCCAUX 0x26 147 #define XADC_REG_MIN_VCCBRAM 0x27 148 #define XADC_REG_MAX_VCCPINT 0x28 149 #define XADC_REG_MAX_VCCPAUX 0x29 150 #define XADC_REG_MAX_VCCO_DDR 0x2a 151 #define XADC_REG_MIN_VCCPINT 0x2c 152 #define XADC_REG_MIN_VCCPAUX 0x2d 153 #define XADC_REG_MIN_VCCO_DDR 0x2e 154 155 #define XADC_REG_CONF0 0x40 156 #define XADC_REG_CONF1 0x41 157 #define XADC_REG_CONF2 0x42 158 #define XADC_REG_SEQ(x) (0x48 + (x)) 159 #define XADC_REG_INPUT_MODE(x) (0x4c + (x)) 160 #define XADC_REG_THRESHOLD(x) (0x50 + (x)) 161 162 #define XADC_REG_FLAG 0x3f 163 164 #define XADC_CONF0_EC BIT(9) 165 #define XADC_CONF0_ACQ BIT(8) 166 #define XADC_CONF0_MUX BIT(11) 167 #define XADC_CONF0_CHAN(x) (x) 168 169 #define XADC_CONF1_SEQ_MASK (0xf << 12) 170 #define XADC_CONF1_SEQ_DEFAULT (0 << 12) 171 #define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12) 172 #define XADC_CONF1_SEQ_CONTINUOUS (2 << 12) 173 #define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12) 174 #define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12) 175 #define XADC_CONF1_SEQ_INDEPENDENT (8 << 12) 176 #define XADC_CONF1_ALARM_MASK 0x0f0f 177 178 #define XADC_CONF2_DIV_MASK 0xff00 179 #define XADC_CONF2_DIV_OFFSET 8 180 181 #define XADC_CONF2_PD_MASK (0x3 << 4) 182 #define XADC_CONF2_PD_NONE (0x0 << 4) 183 #define XADC_CONF2_PD_ADC_B (0x2 << 4) 184 #define XADC_CONF2_PD_BOTH (0x3 << 4) 185 186 #define XADC_ALARM_TEMP_MASK BIT(0) 187 #define XADC_ALARM_VCCINT_MASK BIT(1) 188 #define XADC_ALARM_VCCAUX_MASK BIT(2) 189 #define XADC_ALARM_OT_MASK BIT(3) 190 #define XADC_ALARM_VCCBRAM_MASK BIT(4) 191 #define XADC_ALARM_VCCPINT_MASK BIT(5) 192 #define XADC_ALARM_VCCPAUX_MASK BIT(6) 193 #define XADC_ALARM_VCCODDR_MASK BIT(7) 194 195 #define XADC_THRESHOLD_TEMP_MAX 0x0 196 #define XADC_THRESHOLD_VCCINT_MAX 0x1 197 #define XADC_THRESHOLD_VCCAUX_MAX 0x2 198 #define XADC_THRESHOLD_OT_MAX 0x3 199 #define XADC_THRESHOLD_TEMP_MIN 0x4 200 #define XADC_THRESHOLD_VCCINT_MIN 0x5 201 #define XADC_THRESHOLD_VCCAUX_MIN 0x6 202 #define XADC_THRESHOLD_OT_MIN 0x7 203 #define XADC_THRESHOLD_VCCBRAM_MAX 0x8 204 #define XADC_THRESHOLD_VCCPINT_MAX 0x9 205 #define XADC_THRESHOLD_VCCPAUX_MAX 0xa 206 #define XADC_THRESHOLD_VCCODDR_MAX 0xb 207 #define XADC_THRESHOLD_VCCBRAM_MIN 0xc 208 #define XADC_THRESHOLD_VCCPINT_MIN 0xd 209 #define XADC_THRESHOLD_VCCPAUX_MIN 0xe 210 #define XADC_THRESHOLD_VCCODDR_MIN 0xf 211 212 #endif 213