1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx AMS driver 4 * 5 * Copyright (C) 2021 Xilinx, Inc. 6 * 7 * Manish Narani <mnarani@xilinx.com> 8 * Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/devm-helpers.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/overflow.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/slab.h> 26 27 #include <linux/iio/events.h> 28 #include <linux/iio/iio.h> 29 30 /* AMS registers definitions */ 31 #define AMS_ISR_0 0x010 32 #define AMS_ISR_1 0x014 33 #define AMS_IER_0 0x020 34 #define AMS_IER_1 0x024 35 #define AMS_IDR_0 0x028 36 #define AMS_IDR_1 0x02C 37 #define AMS_PS_CSTS 0x040 38 #define AMS_PL_CSTS 0x044 39 40 #define AMS_VCC_PSPLL0 0x060 41 #define AMS_VCC_PSPLL3 0x06C 42 #define AMS_VCCINT 0x078 43 #define AMS_VCCBRAM 0x07C 44 #define AMS_VCCAUX 0x080 45 #define AMS_PSDDRPLL 0x084 46 #define AMS_PSINTFPDDR 0x09C 47 48 #define AMS_VCC_PSPLL0_CH 48 49 #define AMS_VCC_PSPLL3_CH 51 50 #define AMS_VCCINT_CH 54 51 #define AMS_VCCBRAM_CH 55 52 #define AMS_VCCAUX_CH 56 53 #define AMS_PSDDRPLL_CH 57 54 #define AMS_PSINTFPDDR_CH 63 55 56 #define AMS_REG_CONFIG0 0x100 57 #define AMS_REG_CONFIG1 0x104 58 #define AMS_REG_CONFIG3 0x10C 59 #define AMS_REG_CONFIG4 0x110 60 #define AMS_REG_SEQ_CH0 0x120 61 #define AMS_REG_SEQ_CH1 0x124 62 #define AMS_REG_SEQ_CH2 0x118 63 64 #define AMS_VUSER0_MASK BIT(0) 65 #define AMS_VUSER1_MASK BIT(1) 66 #define AMS_VUSER2_MASK BIT(2) 67 #define AMS_VUSER3_MASK BIT(3) 68 69 #define AMS_TEMP 0x000 70 #define AMS_SUPPLY1 0x004 71 #define AMS_SUPPLY2 0x008 72 #define AMS_VP_VN 0x00C 73 #define AMS_VREFP 0x010 74 #define AMS_VREFN 0x014 75 #define AMS_SUPPLY3 0x018 76 #define AMS_SUPPLY4 0x034 77 #define AMS_SUPPLY5 0x038 78 #define AMS_SUPPLY6 0x03C 79 #define AMS_SUPPLY7 0x200 80 #define AMS_SUPPLY8 0x204 81 #define AMS_SUPPLY9 0x208 82 #define AMS_SUPPLY10 0x20C 83 #define AMS_VCCAMS 0x210 84 #define AMS_TEMP_REMOTE 0x214 85 86 #define AMS_REG_VAUX(x) (0x40 + 4 * (x)) 87 88 #define AMS_PS_RESET_VALUE 0xFFFF 89 #define AMS_PL_RESET_VALUE 0xFFFF 90 91 #define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0) 92 93 #define AMS_CONF1_SEQ_MASK GENMASK(15, 12) 94 #define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0) 95 #define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2) 96 #define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3) 97 98 #define AMS_REG_SEQ0_MASK GENMASK(15, 0) 99 #define AMS_REG_SEQ2_MASK GENMASK(21, 16) 100 #define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22) 101 102 #define AMS_PS_SEQ_MASK GENMASK(21, 0) 103 #define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22) 104 105 #define AMS_ALARM_TEMP 0x140 106 #define AMS_ALARM_SUPPLY1 0x144 107 #define AMS_ALARM_SUPPLY2 0x148 108 #define AMS_ALARM_SUPPLY3 0x160 109 #define AMS_ALARM_SUPPLY4 0x164 110 #define AMS_ALARM_SUPPLY5 0x168 111 #define AMS_ALARM_SUPPLY6 0x16C 112 #define AMS_ALARM_SUPPLY7 0x180 113 #define AMS_ALARM_SUPPLY8 0x184 114 #define AMS_ALARM_SUPPLY9 0x188 115 #define AMS_ALARM_SUPPLY10 0x18C 116 #define AMS_ALARM_VCCAMS 0x190 117 #define AMS_ALARM_TEMP_REMOTE 0x194 118 #define AMS_ALARM_THRESHOLD_OFF_10 0x10 119 #define AMS_ALARM_THRESHOLD_OFF_20 0x20 120 121 #define AMS_ALARM_THR_DIRECT_MASK BIT(1) 122 #define AMS_ALARM_THR_MIN 0x0000 123 #define AMS_ALARM_THR_MAX (BIT(16) - 1) 124 125 #define AMS_ALARM_MASK GENMASK_ULL(63, 0) 126 #define AMS_NO_OF_ALARMS 32 127 #define AMS_PL_ALARM_START 16 128 #define AMS_PL_ALARM_MASK GENMASK(31, 16) 129 #define AMS_ISR0_ALARM_MASK GENMASK(31, 0) 130 #define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0)) 131 #define AMS_ISR1_EOC_MASK BIT(3) 132 #define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32) 133 #define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0) 134 #define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3) 135 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8) 136 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1) 137 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8) 138 #define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0) 139 #define AMS_REGCFG1_ALARM_MASK \ 140 (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0)) 141 #define AMS_REGCFG3_ALARM_MASK AMS_CONF1_ALARM_12_TO_7_MASK 142 143 #define AMS_PS_CSTS_PS_READY (BIT(27) | BIT(16)) 144 #define AMS_PL_CSTS_ACCESS_MASK BIT(1) 145 146 #define AMS_PL_MAX_FIXED_CHANNEL 10 147 #define AMS_PL_MAX_EXT_CHANNEL 20 148 149 #define AMS_INIT_POLL_TIME_US 200 150 #define AMS_INIT_TIMEOUT_US 10000 151 #define AMS_UNMASK_TIMEOUT_MS 500 152 153 /* 154 * Following scale and offset value is derived from 155 * UG580 (v1.7) December 20, 2016 156 */ 157 #define AMS_SUPPLY_SCALE_1VOLT_mV 1000 158 #define AMS_SUPPLY_SCALE_3VOLT_mV 3000 159 #define AMS_SUPPLY_SCALE_6VOLT_mV 6000 160 #define AMS_SUPPLY_SCALE_DIV_BIT 16 161 162 #define AMS_TEMP_SCALE 509314 163 #define AMS_TEMP_SCALE_DIV_BIT 16 164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314) 165 166 enum ams_alarm_bit { 167 AMS_ALARM_BIT_TEMP = 0, 168 AMS_ALARM_BIT_SUPPLY1 = 1, 169 AMS_ALARM_BIT_SUPPLY2 = 2, 170 AMS_ALARM_BIT_SUPPLY3 = 3, 171 AMS_ALARM_BIT_SUPPLY4 = 4, 172 AMS_ALARM_BIT_SUPPLY5 = 5, 173 AMS_ALARM_BIT_SUPPLY6 = 6, 174 AMS_ALARM_BIT_RESERVED = 7, 175 AMS_ALARM_BIT_SUPPLY7 = 8, 176 AMS_ALARM_BIT_SUPPLY8 = 9, 177 AMS_ALARM_BIT_SUPPLY9 = 10, 178 AMS_ALARM_BIT_SUPPLY10 = 11, 179 AMS_ALARM_BIT_VCCAMS = 12, 180 AMS_ALARM_BIT_TEMP_REMOTE = 13, 181 }; 182 183 enum ams_seq { 184 AMS_SEQ_VCC_PSPLL = 0, 185 AMS_SEQ_VCC_PSBATT = 1, 186 AMS_SEQ_VCCINT = 2, 187 AMS_SEQ_VCCBRAM = 3, 188 AMS_SEQ_VCCAUX = 4, 189 AMS_SEQ_PSDDRPLL = 5, 190 AMS_SEQ_INTDDR = 6, 191 }; 192 193 enum ams_ps_pl_seq { 194 AMS_SEQ_CALIB = 0, 195 AMS_SEQ_RSVD_1 = 1, 196 AMS_SEQ_RSVD_2 = 2, 197 AMS_SEQ_TEST = 3, 198 AMS_SEQ_RSVD_4 = 4, 199 AMS_SEQ_SUPPLY4 = 5, 200 AMS_SEQ_SUPPLY5 = 6, 201 AMS_SEQ_SUPPLY6 = 7, 202 AMS_SEQ_TEMP = 8, 203 AMS_SEQ_SUPPLY2 = 9, 204 AMS_SEQ_SUPPLY1 = 10, 205 AMS_SEQ_VP_VN = 11, 206 AMS_SEQ_VREFP = 12, 207 AMS_SEQ_VREFN = 13, 208 AMS_SEQ_SUPPLY3 = 14, 209 AMS_SEQ_CURRENT_MON = 15, 210 AMS_SEQ_SUPPLY7 = 16, 211 AMS_SEQ_SUPPLY8 = 17, 212 AMS_SEQ_SUPPLY9 = 18, 213 AMS_SEQ_SUPPLY10 = 19, 214 AMS_SEQ_VCCAMS = 20, 215 AMS_SEQ_TEMP_REMOTE = 21, 216 AMS_SEQ_MAX = 22 217 }; 218 219 #define AMS_PS_SEQ_MAX AMS_SEQ_MAX 220 #define AMS_SEQ(x) (AMS_SEQ_MAX + (x)) 221 #define PS_SEQ(x) (x) 222 #define PL_SEQ(x) (AMS_PS_SEQ_MAX + (x)) 223 #define AMS_CTRL_SEQ_BASE (AMS_PS_SEQ_MAX * 3) 224 225 #define AMS_CHAN_TEMP(_scan_index, _addr) { \ 226 .type = IIO_TEMP, \ 227 .indexed = 1, \ 228 .address = (_addr), \ 229 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 230 BIT(IIO_CHAN_INFO_SCALE) | \ 231 BIT(IIO_CHAN_INFO_OFFSET), \ 232 .event_spec = ams_temp_events, \ 233 .scan_index = _scan_index, \ 234 .num_event_specs = ARRAY_SIZE(ams_temp_events), \ 235 } 236 237 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm) { \ 238 .type = IIO_VOLTAGE, \ 239 .indexed = 1, \ 240 .address = (_addr), \ 241 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 242 BIT(IIO_CHAN_INFO_SCALE), \ 243 .event_spec = (_alarm) ? ams_voltage_events : NULL, \ 244 .scan_index = _scan_index, \ 245 .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \ 246 } 247 248 #define AMS_PS_CHAN_TEMP(_scan_index, _addr) \ 249 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr) 250 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr) \ 251 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true) 252 253 #define AMS_PL_CHAN_TEMP(_scan_index, _addr) \ 254 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr) 255 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm) \ 256 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm) 257 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \ 258 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false) 259 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr) \ 260 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false) 261 262 /** 263 * struct ams - This structure contains necessary state for xilinx-ams to operate 264 * @base: physical base address of device 265 * @ps_base: physical base address of PS device 266 * @pl_base: physical base address of PL device 267 * @clk: clocks associated with the device 268 * @dev: pointer to device struct 269 * @lock: to handle multiple user interaction 270 * @intr_lock: to protect interrupt mask values 271 * @alarm_mask: alarm configuration 272 * @current_masked_alarm: currently masked due to alarm 273 * @intr_mask: interrupt configuration 274 * @ams_unmask_work: re-enables event once the event condition disappears 275 * 276 */ 277 struct ams { 278 void __iomem *base; 279 void __iomem *ps_base; 280 void __iomem *pl_base; 281 struct clk *clk; 282 struct device *dev; 283 struct mutex lock; 284 spinlock_t intr_lock; 285 unsigned int alarm_mask; 286 unsigned int current_masked_alarm; 287 u64 intr_mask; 288 struct delayed_work ams_unmask_work; 289 }; 290 291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset, 292 u32 mask, u32 data) 293 { 294 u32 val, regval; 295 296 val = readl(ams->ps_base + offset); 297 regval = (val & ~mask) | (data & mask); 298 writel(regval, ams->ps_base + offset); 299 } 300 301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset, 302 u32 mask, u32 data) 303 { 304 u32 val, regval; 305 306 val = readl(ams->pl_base + offset); 307 regval = (val & ~mask) | (data & mask); 308 writel(regval, ams->pl_base + offset); 309 } 310 311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val) 312 { 313 u32 regval; 314 315 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask); 316 317 regval = ~(ams->intr_mask | ams->current_masked_alarm); 318 writel(regval, ams->base + AMS_IER_0); 319 320 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask)); 321 writel(regval, ams->base + AMS_IER_1); 322 323 regval = ams->intr_mask | ams->current_masked_alarm; 324 writel(regval, ams->base + AMS_IDR_0); 325 326 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask); 327 writel(regval, ams->base + AMS_IDR_1); 328 } 329 330 static void ams_disable_all_alarms(struct ams *ams) 331 { 332 /* disable PS module alarm */ 333 if (ams->ps_base) { 334 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 335 AMS_REGCFG1_ALARM_MASK); 336 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 337 AMS_REGCFG3_ALARM_MASK); 338 } 339 340 /* disable PL module alarm */ 341 if (ams->pl_base) { 342 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 343 AMS_REGCFG1_ALARM_MASK); 344 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 345 AMS_REGCFG3_ALARM_MASK); 346 } 347 } 348 349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask) 350 { 351 u32 cfg; 352 u32 val; 353 354 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask); 355 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 356 357 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask); 358 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 359 360 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 361 362 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask); 363 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 364 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 365 } 366 367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask) 368 { 369 unsigned long pl_alarm_mask; 370 u32 cfg; 371 u32 val; 372 373 pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask); 374 375 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask); 376 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 377 378 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask); 379 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 380 381 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 382 383 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask); 384 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 385 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 386 } 387 388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask) 389 { 390 unsigned long flags; 391 392 if (ams->ps_base) 393 ams_update_ps_alarm(ams, alarm_mask); 394 395 if (ams->pl_base) 396 ams_update_pl_alarm(ams, alarm_mask); 397 398 spin_lock_irqsave(&ams->intr_lock, flags); 399 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask); 400 spin_unlock_irqrestore(&ams->intr_lock, flags); 401 } 402 403 static void ams_enable_channel_sequence(struct iio_dev *indio_dev) 404 { 405 struct ams *ams = iio_priv(indio_dev); 406 unsigned long long scan_mask; 407 int i; 408 u32 regval; 409 410 /* 411 * Enable channel sequence. First 22 bits of scan_mask represent 412 * PS channels, and next remaining bits represent PL channels. 413 */ 414 415 /* Run calibration of PS & PL as part of the sequence */ 416 scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX); 417 for (i = 0; i < indio_dev->num_channels; i++) { 418 const struct iio_chan_spec *chan = &indio_dev->channels[i]; 419 420 if (chan->scan_index < AMS_CTRL_SEQ_BASE) 421 scan_mask |= BIT_ULL(chan->scan_index); 422 } 423 424 if (ams->ps_base) { 425 /* put sysmon in a soft reset to change the sequence */ 426 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 427 AMS_CONF1_SEQ_DEFAULT); 428 429 /* configure basic channels */ 430 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 431 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0); 432 433 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 434 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2); 435 436 /* set continuous sequence mode */ 437 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 438 AMS_CONF1_SEQ_CONTINUOUS); 439 } 440 441 if (ams->pl_base) { 442 /* put sysmon in a soft reset to change the sequence */ 443 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 444 AMS_CONF1_SEQ_DEFAULT); 445 446 /* configure basic channels */ 447 scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask); 448 449 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 450 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0); 451 452 regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask); 453 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1); 454 455 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 456 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2); 457 458 /* set continuous sequence mode */ 459 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 460 AMS_CONF1_SEQ_CONTINUOUS); 461 } 462 } 463 464 static int ams_init_device(struct ams *ams) 465 { 466 u32 expect = AMS_PS_CSTS_PS_READY; 467 u32 reg, value; 468 int ret; 469 470 /* reset AMS */ 471 if (ams->ps_base) { 472 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN); 473 474 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect), 475 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 476 if (ret) 477 return ret; 478 479 /* put sysmon in a default state */ 480 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 481 AMS_CONF1_SEQ_DEFAULT); 482 } 483 484 if (ams->pl_base) { 485 value = readl(ams->base + AMS_PL_CSTS); 486 if (value == 0) 487 return 0; 488 489 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN); 490 491 /* put sysmon in a default state */ 492 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 493 AMS_CONF1_SEQ_DEFAULT); 494 } 495 496 ams_disable_all_alarms(ams); 497 498 /* Disable interrupt */ 499 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK); 500 501 /* Clear any pending interrupt */ 502 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0); 503 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1); 504 505 return 0; 506 } 507 508 static int ams_enable_single_channel(struct ams *ams, unsigned int offset) 509 { 510 u8 channel_num; 511 512 switch (offset) { 513 case AMS_VCC_PSPLL0: 514 channel_num = AMS_VCC_PSPLL0_CH; 515 break; 516 case AMS_VCC_PSPLL3: 517 channel_num = AMS_VCC_PSPLL3_CH; 518 break; 519 case AMS_VCCINT: 520 channel_num = AMS_VCCINT_CH; 521 break; 522 case AMS_VCCBRAM: 523 channel_num = AMS_VCCBRAM_CH; 524 break; 525 case AMS_VCCAUX: 526 channel_num = AMS_VCCAUX_CH; 527 break; 528 case AMS_PSDDRPLL: 529 channel_num = AMS_PSDDRPLL_CH; 530 break; 531 case AMS_PSINTFPDDR: 532 channel_num = AMS_PSINTFPDDR_CH; 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 /* put sysmon in a soft reset to change the sequence */ 539 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 540 AMS_CONF1_SEQ_DEFAULT); 541 542 /* write the channel number */ 543 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK, 544 channel_num); 545 546 /* set single channel, sequencer off mode */ 547 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 548 AMS_CONF1_SEQ_SINGLE_CHANNEL); 549 550 return 0; 551 } 552 553 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data) 554 { 555 u32 expect = AMS_ISR1_EOC_MASK; 556 u32 reg; 557 int ret; 558 559 ret = ams_enable_single_channel(ams, offset); 560 if (ret) 561 return ret; 562 563 /* clear end-of-conversion flag, wait for next conversion to complete */ 564 writel(expect, ams->base + AMS_ISR_1); 565 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect), 566 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 567 if (ret) 568 return ret; 569 570 *data = readl(ams->base + offset); 571 572 return 0; 573 } 574 575 static int ams_get_ps_scale(int address) 576 { 577 int val; 578 579 switch (address) { 580 case AMS_SUPPLY1: 581 case AMS_SUPPLY2: 582 case AMS_SUPPLY3: 583 case AMS_SUPPLY4: 584 case AMS_SUPPLY9: 585 case AMS_SUPPLY10: 586 case AMS_VCCAMS: 587 val = AMS_SUPPLY_SCALE_3VOLT_mV; 588 break; 589 case AMS_SUPPLY5: 590 case AMS_SUPPLY6: 591 case AMS_SUPPLY7: 592 case AMS_SUPPLY8: 593 val = AMS_SUPPLY_SCALE_6VOLT_mV; 594 break; 595 default: 596 val = AMS_SUPPLY_SCALE_1VOLT_mV; 597 break; 598 } 599 600 return val; 601 } 602 603 static int ams_get_pl_scale(struct ams *ams, int address) 604 { 605 int val, regval; 606 607 switch (address) { 608 case AMS_SUPPLY1: 609 case AMS_SUPPLY2: 610 case AMS_SUPPLY3: 611 case AMS_SUPPLY4: 612 case AMS_SUPPLY5: 613 case AMS_SUPPLY6: 614 case AMS_VCCAMS: 615 case AMS_VREFP: 616 case AMS_VREFN: 617 val = AMS_SUPPLY_SCALE_3VOLT_mV; 618 break; 619 case AMS_SUPPLY7: 620 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 621 if (FIELD_GET(AMS_VUSER0_MASK, regval)) 622 val = AMS_SUPPLY_SCALE_6VOLT_mV; 623 else 624 val = AMS_SUPPLY_SCALE_3VOLT_mV; 625 break; 626 case AMS_SUPPLY8: 627 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 628 if (FIELD_GET(AMS_VUSER1_MASK, regval)) 629 val = AMS_SUPPLY_SCALE_6VOLT_mV; 630 else 631 val = AMS_SUPPLY_SCALE_3VOLT_mV; 632 break; 633 case AMS_SUPPLY9: 634 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 635 if (FIELD_GET(AMS_VUSER2_MASK, regval)) 636 val = AMS_SUPPLY_SCALE_6VOLT_mV; 637 else 638 val = AMS_SUPPLY_SCALE_3VOLT_mV; 639 break; 640 case AMS_SUPPLY10: 641 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 642 if (FIELD_GET(AMS_VUSER3_MASK, regval)) 643 val = AMS_SUPPLY_SCALE_6VOLT_mV; 644 else 645 val = AMS_SUPPLY_SCALE_3VOLT_mV; 646 break; 647 case AMS_VP_VN: 648 case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15): 649 val = AMS_SUPPLY_SCALE_1VOLT_mV; 650 break; 651 default: 652 val = AMS_SUPPLY_SCALE_1VOLT_mV; 653 break; 654 } 655 656 return val; 657 } 658 659 static int ams_get_ctrl_scale(int address) 660 { 661 int val; 662 663 switch (address) { 664 case AMS_VCC_PSPLL0: 665 case AMS_VCC_PSPLL3: 666 case AMS_VCCINT: 667 case AMS_VCCBRAM: 668 case AMS_VCCAUX: 669 case AMS_PSDDRPLL: 670 case AMS_PSINTFPDDR: 671 val = AMS_SUPPLY_SCALE_3VOLT_mV; 672 break; 673 default: 674 val = AMS_SUPPLY_SCALE_1VOLT_mV; 675 break; 676 } 677 678 return val; 679 } 680 681 static int ams_read_raw(struct iio_dev *indio_dev, 682 struct iio_chan_spec const *chan, 683 int *val, int *val2, long mask) 684 { 685 struct ams *ams = iio_priv(indio_dev); 686 int ret; 687 688 switch (mask) { 689 case IIO_CHAN_INFO_RAW: 690 mutex_lock(&ams->lock); 691 if (chan->scan_index >= AMS_CTRL_SEQ_BASE) { 692 ret = ams_read_vcc_reg(ams, chan->address, val); 693 if (ret) 694 goto unlock_mutex; 695 ams_enable_channel_sequence(indio_dev); 696 } else if (chan->scan_index >= AMS_PS_SEQ_MAX) 697 *val = readl(ams->pl_base + chan->address); 698 else 699 *val = readl(ams->ps_base + chan->address); 700 701 ret = IIO_VAL_INT; 702 unlock_mutex: 703 mutex_unlock(&ams->lock); 704 return ret; 705 case IIO_CHAN_INFO_SCALE: 706 switch (chan->type) { 707 case IIO_VOLTAGE: 708 if (chan->scan_index < AMS_PS_SEQ_MAX) 709 *val = ams_get_ps_scale(chan->address); 710 else if (chan->scan_index >= AMS_PS_SEQ_MAX && 711 chan->scan_index < AMS_CTRL_SEQ_BASE) 712 *val = ams_get_pl_scale(ams, chan->address); 713 else 714 *val = ams_get_ctrl_scale(chan->address); 715 716 *val2 = AMS_SUPPLY_SCALE_DIV_BIT; 717 return IIO_VAL_FRACTIONAL_LOG2; 718 case IIO_TEMP: 719 *val = AMS_TEMP_SCALE; 720 *val2 = AMS_TEMP_SCALE_DIV_BIT; 721 return IIO_VAL_FRACTIONAL_LOG2; 722 default: 723 return -EINVAL; 724 } 725 case IIO_CHAN_INFO_OFFSET: 726 /* Only the temperature channel has an offset */ 727 *val = AMS_TEMP_OFFSET; 728 return IIO_VAL_INT; 729 default: 730 return -EINVAL; 731 } 732 } 733 734 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir) 735 { 736 int offset; 737 738 if (scan_index >= AMS_PS_SEQ_MAX) 739 scan_index -= AMS_PS_SEQ_MAX; 740 741 if (dir == IIO_EV_DIR_FALLING) { 742 if (scan_index < AMS_SEQ_SUPPLY7) 743 offset = AMS_ALARM_THRESHOLD_OFF_10; 744 else 745 offset = AMS_ALARM_THRESHOLD_OFF_20; 746 } else { 747 offset = 0; 748 } 749 750 switch (scan_index) { 751 case AMS_SEQ_TEMP: 752 return AMS_ALARM_TEMP + offset; 753 case AMS_SEQ_SUPPLY1: 754 return AMS_ALARM_SUPPLY1 + offset; 755 case AMS_SEQ_SUPPLY2: 756 return AMS_ALARM_SUPPLY2 + offset; 757 case AMS_SEQ_SUPPLY3: 758 return AMS_ALARM_SUPPLY3 + offset; 759 case AMS_SEQ_SUPPLY4: 760 return AMS_ALARM_SUPPLY4 + offset; 761 case AMS_SEQ_SUPPLY5: 762 return AMS_ALARM_SUPPLY5 + offset; 763 case AMS_SEQ_SUPPLY6: 764 return AMS_ALARM_SUPPLY6 + offset; 765 case AMS_SEQ_SUPPLY7: 766 return AMS_ALARM_SUPPLY7 + offset; 767 case AMS_SEQ_SUPPLY8: 768 return AMS_ALARM_SUPPLY8 + offset; 769 case AMS_SEQ_SUPPLY9: 770 return AMS_ALARM_SUPPLY9 + offset; 771 case AMS_SEQ_SUPPLY10: 772 return AMS_ALARM_SUPPLY10 + offset; 773 case AMS_SEQ_VCCAMS: 774 return AMS_ALARM_VCCAMS + offset; 775 case AMS_SEQ_TEMP_REMOTE: 776 return AMS_ALARM_TEMP_REMOTE + offset; 777 default: 778 return 0; 779 } 780 } 781 782 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev, 783 u32 event) 784 { 785 int scan_index = 0, i; 786 787 if (event >= AMS_PL_ALARM_START) { 788 event -= AMS_PL_ALARM_START; 789 scan_index = AMS_PS_SEQ_MAX; 790 } 791 792 switch (event) { 793 case AMS_ALARM_BIT_TEMP: 794 scan_index += AMS_SEQ_TEMP; 795 break; 796 case AMS_ALARM_BIT_SUPPLY1: 797 scan_index += AMS_SEQ_SUPPLY1; 798 break; 799 case AMS_ALARM_BIT_SUPPLY2: 800 scan_index += AMS_SEQ_SUPPLY2; 801 break; 802 case AMS_ALARM_BIT_SUPPLY3: 803 scan_index += AMS_SEQ_SUPPLY3; 804 break; 805 case AMS_ALARM_BIT_SUPPLY4: 806 scan_index += AMS_SEQ_SUPPLY4; 807 break; 808 case AMS_ALARM_BIT_SUPPLY5: 809 scan_index += AMS_SEQ_SUPPLY5; 810 break; 811 case AMS_ALARM_BIT_SUPPLY6: 812 scan_index += AMS_SEQ_SUPPLY6; 813 break; 814 case AMS_ALARM_BIT_SUPPLY7: 815 scan_index += AMS_SEQ_SUPPLY7; 816 break; 817 case AMS_ALARM_BIT_SUPPLY8: 818 scan_index += AMS_SEQ_SUPPLY8; 819 break; 820 case AMS_ALARM_BIT_SUPPLY9: 821 scan_index += AMS_SEQ_SUPPLY9; 822 break; 823 case AMS_ALARM_BIT_SUPPLY10: 824 scan_index += AMS_SEQ_SUPPLY10; 825 break; 826 case AMS_ALARM_BIT_VCCAMS: 827 scan_index += AMS_SEQ_VCCAMS; 828 break; 829 case AMS_ALARM_BIT_TEMP_REMOTE: 830 scan_index += AMS_SEQ_TEMP_REMOTE; 831 break; 832 default: 833 break; 834 } 835 836 for (i = 0; i < dev->num_channels; i++) 837 if (dev->channels[i].scan_index == scan_index) 838 break; 839 840 return &dev->channels[i]; 841 } 842 843 static int ams_get_alarm_mask(int scan_index) 844 { 845 int bit = 0; 846 847 if (scan_index >= AMS_PS_SEQ_MAX) { 848 bit = AMS_PL_ALARM_START; 849 scan_index -= AMS_PS_SEQ_MAX; 850 } 851 852 switch (scan_index) { 853 case AMS_SEQ_TEMP: 854 return BIT(AMS_ALARM_BIT_TEMP + bit); 855 case AMS_SEQ_SUPPLY1: 856 return BIT(AMS_ALARM_BIT_SUPPLY1 + bit); 857 case AMS_SEQ_SUPPLY2: 858 return BIT(AMS_ALARM_BIT_SUPPLY2 + bit); 859 case AMS_SEQ_SUPPLY3: 860 return BIT(AMS_ALARM_BIT_SUPPLY3 + bit); 861 case AMS_SEQ_SUPPLY4: 862 return BIT(AMS_ALARM_BIT_SUPPLY4 + bit); 863 case AMS_SEQ_SUPPLY5: 864 return BIT(AMS_ALARM_BIT_SUPPLY5 + bit); 865 case AMS_SEQ_SUPPLY6: 866 return BIT(AMS_ALARM_BIT_SUPPLY6 + bit); 867 case AMS_SEQ_SUPPLY7: 868 return BIT(AMS_ALARM_BIT_SUPPLY7 + bit); 869 case AMS_SEQ_SUPPLY8: 870 return BIT(AMS_ALARM_BIT_SUPPLY8 + bit); 871 case AMS_SEQ_SUPPLY9: 872 return BIT(AMS_ALARM_BIT_SUPPLY9 + bit); 873 case AMS_SEQ_SUPPLY10: 874 return BIT(AMS_ALARM_BIT_SUPPLY10 + bit); 875 case AMS_SEQ_VCCAMS: 876 return BIT(AMS_ALARM_BIT_VCCAMS + bit); 877 case AMS_SEQ_TEMP_REMOTE: 878 return BIT(AMS_ALARM_BIT_TEMP_REMOTE + bit); 879 default: 880 return 0; 881 } 882 } 883 884 static int ams_read_event_config(struct iio_dev *indio_dev, 885 const struct iio_chan_spec *chan, 886 enum iio_event_type type, 887 enum iio_event_direction dir) 888 { 889 struct ams *ams = iio_priv(indio_dev); 890 891 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index)); 892 } 893 894 static int ams_write_event_config(struct iio_dev *indio_dev, 895 const struct iio_chan_spec *chan, 896 enum iio_event_type type, 897 enum iio_event_direction dir, 898 int state) 899 { 900 struct ams *ams = iio_priv(indio_dev); 901 unsigned int alarm; 902 903 alarm = ams_get_alarm_mask(chan->scan_index); 904 905 mutex_lock(&ams->lock); 906 907 if (state) 908 ams->alarm_mask |= alarm; 909 else 910 ams->alarm_mask &= ~alarm; 911 912 ams_update_alarm(ams, ams->alarm_mask); 913 914 mutex_unlock(&ams->lock); 915 916 return 0; 917 } 918 919 static int ams_read_event_value(struct iio_dev *indio_dev, 920 const struct iio_chan_spec *chan, 921 enum iio_event_type type, 922 enum iio_event_direction dir, 923 enum iio_event_info info, int *val, int *val2) 924 { 925 struct ams *ams = iio_priv(indio_dev); 926 unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir); 927 928 mutex_lock(&ams->lock); 929 930 if (chan->scan_index >= AMS_PS_SEQ_MAX) 931 *val = readl(ams->pl_base + offset); 932 else 933 *val = readl(ams->ps_base + offset); 934 935 mutex_unlock(&ams->lock); 936 937 return IIO_VAL_INT; 938 } 939 940 static int ams_write_event_value(struct iio_dev *indio_dev, 941 const struct iio_chan_spec *chan, 942 enum iio_event_type type, 943 enum iio_event_direction dir, 944 enum iio_event_info info, int val, int val2) 945 { 946 struct ams *ams = iio_priv(indio_dev); 947 unsigned int offset; 948 949 mutex_lock(&ams->lock); 950 951 /* Set temperature channel threshold to direct threshold */ 952 if (chan->type == IIO_TEMP) { 953 offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING); 954 955 if (chan->scan_index >= AMS_PS_SEQ_MAX) 956 ams_pl_update_reg(ams, offset, 957 AMS_ALARM_THR_DIRECT_MASK, 958 AMS_ALARM_THR_DIRECT_MASK); 959 else 960 ams_ps_update_reg(ams, offset, 961 AMS_ALARM_THR_DIRECT_MASK, 962 AMS_ALARM_THR_DIRECT_MASK); 963 } 964 965 offset = ams_get_alarm_offset(chan->scan_index, dir); 966 if (chan->scan_index >= AMS_PS_SEQ_MAX) 967 writel(val, ams->pl_base + offset); 968 else 969 writel(val, ams->ps_base + offset); 970 971 mutex_unlock(&ams->lock); 972 973 return 0; 974 } 975 976 static void ams_handle_event(struct iio_dev *indio_dev, u32 event) 977 { 978 const struct iio_chan_spec *chan; 979 980 chan = ams_event_to_channel(indio_dev, event); 981 982 if (chan->type == IIO_TEMP) { 983 /* 984 * The temperature channel only supports over-temperature 985 * events. 986 */ 987 iio_push_event(indio_dev, 988 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 989 IIO_EV_TYPE_THRESH, 990 IIO_EV_DIR_RISING), 991 iio_get_time_ns(indio_dev)); 992 } else { 993 /* 994 * For other channels we don't know whether it is a upper or 995 * lower threshold event. Userspace will have to check the 996 * channel value if it wants to know. 997 */ 998 iio_push_event(indio_dev, 999 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 1000 IIO_EV_TYPE_THRESH, 1001 IIO_EV_DIR_EITHER), 1002 iio_get_time_ns(indio_dev)); 1003 } 1004 } 1005 1006 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events) 1007 { 1008 unsigned int bit; 1009 1010 for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS) 1011 ams_handle_event(indio_dev, bit); 1012 } 1013 1014 /** 1015 * ams_unmask_worker - ams alarm interrupt unmask worker 1016 * @work: work to be done 1017 * 1018 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the 1019 * threshold condition go way from within the interrupt handler, this means as 1020 * soon as a threshold condition is present we would enter the interrupt handler 1021 * again and again. To work around this we mask all active threshold interrupts 1022 * in the interrupt handler and start a timer. In this timer we poll the 1023 * interrupt status and only if the interrupt is inactive we unmask it again. 1024 */ 1025 static void ams_unmask_worker(struct work_struct *work) 1026 { 1027 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work); 1028 unsigned int status, unmask; 1029 1030 spin_lock_irq(&ams->intr_lock); 1031 1032 status = readl(ams->base + AMS_ISR_0); 1033 1034 /* Clear those bits which are not active anymore */ 1035 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm; 1036 1037 /* Clear status of disabled alarm */ 1038 unmask |= ams->intr_mask; 1039 1040 ams->current_masked_alarm &= status; 1041 1042 /* Also clear those which are masked out anyway */ 1043 ams->current_masked_alarm &= ~ams->intr_mask; 1044 1045 /* Clear the interrupts before we unmask them */ 1046 writel(unmask, ams->base + AMS_ISR_0); 1047 1048 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 1049 1050 spin_unlock_irq(&ams->intr_lock); 1051 1052 /* If still pending some alarm re-trigger the timer */ 1053 if (ams->current_masked_alarm) 1054 schedule_delayed_work(&ams->ams_unmask_work, 1055 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1056 } 1057 1058 static irqreturn_t ams_irq(int irq, void *data) 1059 { 1060 struct iio_dev *indio_dev = data; 1061 struct ams *ams = iio_priv(indio_dev); 1062 u32 isr0; 1063 1064 spin_lock(&ams->intr_lock); 1065 1066 isr0 = readl(ams->base + AMS_ISR_0); 1067 1068 /* Only process alarms that are not masked */ 1069 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm); 1070 if (!isr0) { 1071 spin_unlock(&ams->intr_lock); 1072 return IRQ_NONE; 1073 } 1074 1075 /* Clear interrupt */ 1076 writel(isr0, ams->base + AMS_ISR_0); 1077 1078 /* Mask the alarm interrupts until cleared */ 1079 ams->current_masked_alarm |= isr0; 1080 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 1081 1082 ams_handle_events(indio_dev, isr0); 1083 1084 schedule_delayed_work(&ams->ams_unmask_work, 1085 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1086 1087 spin_unlock(&ams->intr_lock); 1088 1089 return IRQ_HANDLED; 1090 } 1091 1092 static const struct iio_event_spec ams_temp_events[] = { 1093 { 1094 .type = IIO_EV_TYPE_THRESH, 1095 .dir = IIO_EV_DIR_RISING, 1096 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), 1097 }, 1098 }; 1099 1100 static const struct iio_event_spec ams_voltage_events[] = { 1101 { 1102 .type = IIO_EV_TYPE_THRESH, 1103 .dir = IIO_EV_DIR_RISING, 1104 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1105 }, 1106 { 1107 .type = IIO_EV_TYPE_THRESH, 1108 .dir = IIO_EV_DIR_FALLING, 1109 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1110 }, 1111 { 1112 .type = IIO_EV_TYPE_THRESH, 1113 .dir = IIO_EV_DIR_EITHER, 1114 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1115 }, 1116 }; 1117 1118 static const struct iio_chan_spec ams_ps_channels[] = { 1119 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP), 1120 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE), 1121 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1), 1122 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2), 1123 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3), 1124 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4), 1125 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5), 1126 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6), 1127 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7), 1128 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8), 1129 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9), 1130 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10), 1131 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS), 1132 }; 1133 1134 static const struct iio_chan_spec ams_pl_channels[] = { 1135 AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP), 1136 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true), 1137 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true), 1138 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false), 1139 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false), 1140 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true), 1141 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true), 1142 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true), 1143 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true), 1144 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true), 1145 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false), 1146 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true), 1147 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true), 1148 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true), 1149 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true), 1150 AMS_PL_AUX_CHAN_VOLTAGE(0), 1151 AMS_PL_AUX_CHAN_VOLTAGE(1), 1152 AMS_PL_AUX_CHAN_VOLTAGE(2), 1153 AMS_PL_AUX_CHAN_VOLTAGE(3), 1154 AMS_PL_AUX_CHAN_VOLTAGE(4), 1155 AMS_PL_AUX_CHAN_VOLTAGE(5), 1156 AMS_PL_AUX_CHAN_VOLTAGE(6), 1157 AMS_PL_AUX_CHAN_VOLTAGE(7), 1158 AMS_PL_AUX_CHAN_VOLTAGE(8), 1159 AMS_PL_AUX_CHAN_VOLTAGE(9), 1160 AMS_PL_AUX_CHAN_VOLTAGE(10), 1161 AMS_PL_AUX_CHAN_VOLTAGE(11), 1162 AMS_PL_AUX_CHAN_VOLTAGE(12), 1163 AMS_PL_AUX_CHAN_VOLTAGE(13), 1164 AMS_PL_AUX_CHAN_VOLTAGE(14), 1165 AMS_PL_AUX_CHAN_VOLTAGE(15), 1166 }; 1167 1168 static const struct iio_chan_spec ams_ctrl_channels[] = { 1169 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0), 1170 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3), 1171 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT), 1172 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM), 1173 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX), 1174 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL), 1175 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR), 1176 }; 1177 1178 static int ams_get_ext_chan(struct fwnode_handle *chan_node, 1179 struct iio_chan_spec *channels, int num_channels) 1180 { 1181 struct iio_chan_spec *chan; 1182 struct fwnode_handle *child; 1183 unsigned int reg, ext_chan; 1184 int ret; 1185 1186 fwnode_for_each_child_node(chan_node, child) { 1187 ret = fwnode_property_read_u32(child, "reg", ®); 1188 if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30) 1189 continue; 1190 1191 chan = &channels[num_channels]; 1192 ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30; 1193 memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels)); 1194 1195 if (fwnode_property_read_bool(child, "xlnx,bipolar")) 1196 chan->scan_type.sign = 's'; 1197 1198 num_channels++; 1199 } 1200 1201 return num_channels; 1202 } 1203 1204 static void ams_iounmap_ps(void *data) 1205 { 1206 struct ams *ams = data; 1207 1208 iounmap(ams->ps_base); 1209 } 1210 1211 static void ams_iounmap_pl(void *data) 1212 { 1213 struct ams *ams = data; 1214 1215 iounmap(ams->pl_base); 1216 } 1217 1218 static int ams_init_module(struct iio_dev *indio_dev, 1219 struct fwnode_handle *fwnode, 1220 struct iio_chan_spec *channels) 1221 { 1222 struct device *dev = indio_dev->dev.parent; 1223 struct ams *ams = iio_priv(indio_dev); 1224 int num_channels = 0; 1225 int ret; 1226 1227 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) { 1228 ams->ps_base = fwnode_iomap(fwnode, 0); 1229 if (!ams->ps_base) 1230 return -ENXIO; 1231 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams); 1232 if (ret < 0) 1233 return ret; 1234 1235 /* add PS channels to iio device channels */ 1236 memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels)); 1237 num_channels = ARRAY_SIZE(ams_ps_channels); 1238 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) { 1239 ams->pl_base = fwnode_iomap(fwnode, 0); 1240 if (!ams->pl_base) 1241 return -ENXIO; 1242 1243 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams); 1244 if (ret < 0) 1245 return ret; 1246 1247 /* Copy only first 10 fix channels */ 1248 memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels)); 1249 num_channels += AMS_PL_MAX_FIXED_CHANNEL; 1250 num_channels = ams_get_ext_chan(fwnode, channels, 1251 num_channels); 1252 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) { 1253 /* add AMS channels to iio device channels */ 1254 memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels)); 1255 num_channels += ARRAY_SIZE(ams_ctrl_channels); 1256 } else { 1257 return -EINVAL; 1258 } 1259 1260 return num_channels; 1261 } 1262 1263 static int ams_parse_firmware(struct iio_dev *indio_dev) 1264 { 1265 struct ams *ams = iio_priv(indio_dev); 1266 struct iio_chan_spec *ams_channels, *dev_channels; 1267 struct device *dev = indio_dev->dev.parent; 1268 struct fwnode_handle *child = NULL; 1269 struct fwnode_handle *fwnode = dev_fwnode(dev); 1270 size_t ams_size; 1271 int ret, ch_cnt = 0, i, rising_off, falling_off; 1272 unsigned int num_channels = 0; 1273 1274 ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) + 1275 ARRAY_SIZE(ams_ctrl_channels); 1276 1277 /* Initialize buffer for channel specification */ 1278 ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL); 1279 if (!ams_channels) 1280 return -ENOMEM; 1281 1282 if (fwnode_device_is_available(fwnode)) { 1283 ret = ams_init_module(indio_dev, fwnode, ams_channels); 1284 if (ret < 0) 1285 return ret; 1286 1287 num_channels += ret; 1288 } 1289 1290 fwnode_for_each_child_node(fwnode, child) { 1291 if (fwnode_device_is_available(child)) { 1292 ret = ams_init_module(indio_dev, child, ams_channels + num_channels); 1293 if (ret < 0) { 1294 fwnode_handle_put(child); 1295 return ret; 1296 } 1297 1298 num_channels += ret; 1299 } 1300 } 1301 1302 for (i = 0; i < num_channels; i++) { 1303 ams_channels[i].channel = ch_cnt++; 1304 1305 if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) { 1306 /* set threshold to max and min for each channel */ 1307 falling_off = 1308 ams_get_alarm_offset(ams_channels[i].scan_index, 1309 IIO_EV_DIR_FALLING); 1310 rising_off = 1311 ams_get_alarm_offset(ams_channels[i].scan_index, 1312 IIO_EV_DIR_RISING); 1313 if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) { 1314 writel(AMS_ALARM_THR_MIN, 1315 ams->pl_base + falling_off); 1316 writel(AMS_ALARM_THR_MAX, 1317 ams->pl_base + rising_off); 1318 } else { 1319 writel(AMS_ALARM_THR_MIN, 1320 ams->ps_base + falling_off); 1321 writel(AMS_ALARM_THR_MAX, 1322 ams->ps_base + rising_off); 1323 } 1324 } 1325 } 1326 1327 dev_channels = devm_krealloc_array(dev, ams_channels, num_channels, 1328 sizeof(*dev_channels), GFP_KERNEL); 1329 if (!dev_channels) 1330 return -ENOMEM; 1331 1332 indio_dev->channels = dev_channels; 1333 indio_dev->num_channels = num_channels; 1334 1335 return 0; 1336 } 1337 1338 static const struct iio_info iio_ams_info = { 1339 .read_raw = &ams_read_raw, 1340 .read_event_config = &ams_read_event_config, 1341 .write_event_config = &ams_write_event_config, 1342 .read_event_value = &ams_read_event_value, 1343 .write_event_value = &ams_write_event_value, 1344 }; 1345 1346 static const struct of_device_id ams_of_match_table[] = { 1347 { .compatible = "xlnx,zynqmp-ams" }, 1348 { } 1349 }; 1350 MODULE_DEVICE_TABLE(of, ams_of_match_table); 1351 1352 static int ams_probe(struct platform_device *pdev) 1353 { 1354 struct iio_dev *indio_dev; 1355 struct ams *ams; 1356 int ret; 1357 int irq; 1358 1359 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams)); 1360 if (!indio_dev) 1361 return -ENOMEM; 1362 1363 ams = iio_priv(indio_dev); 1364 mutex_init(&ams->lock); 1365 spin_lock_init(&ams->intr_lock); 1366 1367 indio_dev->name = "xilinx-ams"; 1368 1369 indio_dev->info = &iio_ams_info; 1370 indio_dev->modes = INDIO_DIRECT_MODE; 1371 1372 ams->base = devm_platform_ioremap_resource(pdev, 0); 1373 if (IS_ERR(ams->base)) 1374 return PTR_ERR(ams->base); 1375 1376 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1377 if (IS_ERR(ams->clk)) 1378 return PTR_ERR(ams->clk); 1379 1380 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work, 1381 ams_unmask_worker); 1382 if (ret < 0) 1383 return ret; 1384 1385 ret = ams_parse_firmware(indio_dev); 1386 if (ret) 1387 return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n"); 1388 1389 ret = ams_init_device(ams); 1390 if (ret) 1391 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n"); 1392 1393 ams_enable_channel_sequence(indio_dev); 1394 1395 irq = platform_get_irq(pdev, 0); 1396 if (irq < 0) 1397 return irq; 1398 1399 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq", 1400 indio_dev); 1401 if (ret < 0) 1402 return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n"); 1403 1404 platform_set_drvdata(pdev, indio_dev); 1405 1406 return devm_iio_device_register(&pdev->dev, indio_dev); 1407 } 1408 1409 static int ams_suspend(struct device *dev) 1410 { 1411 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1412 1413 clk_disable_unprepare(ams->clk); 1414 1415 return 0; 1416 } 1417 1418 static int ams_resume(struct device *dev) 1419 { 1420 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1421 1422 return clk_prepare_enable(ams->clk); 1423 } 1424 1425 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume); 1426 1427 static struct platform_driver ams_driver = { 1428 .probe = ams_probe, 1429 .driver = { 1430 .name = "xilinx-ams", 1431 .pm = pm_sleep_ptr(&ams_pm_ops), 1432 .of_match_table = ams_of_match_table, 1433 }, 1434 }; 1435 module_platform_driver(ams_driver); 1436 1437 MODULE_LICENSE("GPL v2"); 1438 MODULE_AUTHOR("Xilinx, Inc."); 1439