1 /* 2 * Freescale Vybrid vf610 ADC driver 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/io.h> 28 #include <linux/clk.h> 29 #include <linux/completion.h> 30 #include <linux/of.h> 31 #include <linux/of_irq.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/of_platform.h> 34 #include <linux/err.h> 35 36 #include <linux/iio/iio.h> 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/sysfs.h> 39 #include <linux/iio/trigger.h> 40 #include <linux/iio/trigger_consumer.h> 41 #include <linux/iio/triggered_buffer.h> 42 43 /* This will be the driver name the kernel reports */ 44 #define DRIVER_NAME "vf610-adc" 45 46 /* Vybrid/IMX ADC registers */ 47 #define VF610_REG_ADC_HC0 0x00 48 #define VF610_REG_ADC_HC1 0x04 49 #define VF610_REG_ADC_HS 0x08 50 #define VF610_REG_ADC_R0 0x0c 51 #define VF610_REG_ADC_R1 0x10 52 #define VF610_REG_ADC_CFG 0x14 53 #define VF610_REG_ADC_GC 0x18 54 #define VF610_REG_ADC_GS 0x1c 55 #define VF610_REG_ADC_CV 0x20 56 #define VF610_REG_ADC_OFS 0x24 57 #define VF610_REG_ADC_CAL 0x28 58 #define VF610_REG_ADC_PCTL 0x30 59 60 /* Configuration register field define */ 61 #define VF610_ADC_MODE_BIT8 0x00 62 #define VF610_ADC_MODE_BIT10 0x04 63 #define VF610_ADC_MODE_BIT12 0x08 64 #define VF610_ADC_MODE_MASK 0x0c 65 #define VF610_ADC_BUSCLK2_SEL 0x01 66 #define VF610_ADC_ALTCLK_SEL 0x02 67 #define VF610_ADC_ADACK_SEL 0x03 68 #define VF610_ADC_ADCCLK_MASK 0x03 69 #define VF610_ADC_CLK_DIV2 0x20 70 #define VF610_ADC_CLK_DIV4 0x40 71 #define VF610_ADC_CLK_DIV8 0x60 72 #define VF610_ADC_CLK_MASK 0x60 73 #define VF610_ADC_ADLSMP_LONG 0x10 74 #define VF610_ADC_ADSTS_SHORT 0x100 75 #define VF610_ADC_ADSTS_NORMAL 0x200 76 #define VF610_ADC_ADSTS_LONG 0x300 77 #define VF610_ADC_ADSTS_MASK 0x300 78 #define VF610_ADC_ADLPC_EN 0x80 79 #define VF610_ADC_ADHSC_EN 0x400 80 #define VF610_ADC_REFSEL_VALT 0x100 81 #define VF610_ADC_REFSEL_VBG 0x1000 82 #define VF610_ADC_ADTRG_HARD 0x2000 83 #define VF610_ADC_AVGS_8 0x4000 84 #define VF610_ADC_AVGS_16 0x8000 85 #define VF610_ADC_AVGS_32 0xC000 86 #define VF610_ADC_AVGS_MASK 0xC000 87 #define VF610_ADC_OVWREN 0x10000 88 89 /* General control register field define */ 90 #define VF610_ADC_ADACKEN 0x1 91 #define VF610_ADC_DMAEN 0x2 92 #define VF610_ADC_ACREN 0x4 93 #define VF610_ADC_ACFGT 0x8 94 #define VF610_ADC_ACFE 0x10 95 #define VF610_ADC_AVGEN 0x20 96 #define VF610_ADC_ADCON 0x40 97 #define VF610_ADC_CAL 0x80 98 99 /* Other field define */ 100 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 101 #define VF610_ADC_AIEN (0x1 << 7) 102 #define VF610_ADC_CONV_DISABLE 0x1F 103 #define VF610_ADC_HS_COCO0 0x1 104 #define VF610_ADC_CALF 0x2 105 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 106 107 #define DEFAULT_SAMPLE_TIME 1000 108 109 enum clk_sel { 110 VF610_ADCIOC_BUSCLK_SET, 111 VF610_ADCIOC_ALTCLK_SET, 112 VF610_ADCIOC_ADACK_SET, 113 }; 114 115 enum vol_ref { 116 VF610_ADCIOC_VR_VREF_SET, 117 VF610_ADCIOC_VR_VALT_SET, 118 VF610_ADCIOC_VR_VBG_SET, 119 }; 120 121 enum average_sel { 122 VF610_ADC_SAMPLE_1, 123 VF610_ADC_SAMPLE_4, 124 VF610_ADC_SAMPLE_8, 125 VF610_ADC_SAMPLE_16, 126 VF610_ADC_SAMPLE_32, 127 }; 128 129 enum conversion_mode_sel { 130 VF610_ADC_CONV_NORMAL, 131 VF610_ADC_CONV_HIGH_SPEED, 132 VF610_ADC_CONV_LOW_POWER, 133 }; 134 135 enum lst_adder_sel { 136 VF610_ADCK_CYCLES_3, 137 VF610_ADCK_CYCLES_5, 138 VF610_ADCK_CYCLES_7, 139 VF610_ADCK_CYCLES_9, 140 VF610_ADCK_CYCLES_13, 141 VF610_ADCK_CYCLES_17, 142 VF610_ADCK_CYCLES_21, 143 VF610_ADCK_CYCLES_25, 144 }; 145 146 struct vf610_adc_feature { 147 enum clk_sel clk_sel; 148 enum vol_ref vol_ref; 149 enum conversion_mode_sel conv_mode; 150 151 int clk_div; 152 int sample_rate; 153 int res_mode; 154 u32 lst_adder_index; 155 u32 default_sample_time; 156 157 bool calibration; 158 bool ovwren; 159 }; 160 161 struct vf610_adc { 162 struct device *dev; 163 void __iomem *regs; 164 struct clk *clk; 165 166 u32 vref_uv; 167 u32 value; 168 struct regulator *vref; 169 170 u32 max_adck_rate[3]; 171 struct vf610_adc_feature adc_feature; 172 173 u32 sample_freq_avail[5]; 174 175 struct completion completion; 176 u16 buffer[8]; 177 }; 178 179 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; 180 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 }; 181 182 static inline void vf610_adc_calculate_rates(struct vf610_adc *info) 183 { 184 struct vf610_adc_feature *adc_feature = &info->adc_feature; 185 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); 186 u32 adck_period, lst_addr_min; 187 int divisor, i; 188 189 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; 190 191 if (adck_rate) { 192 /* calculate clk divider which is within specification */ 193 divisor = ipg_rate / adck_rate; 194 adc_feature->clk_div = 1 << fls(divisor + 1); 195 } else { 196 /* fall-back value using a safe divisor */ 197 adc_feature->clk_div = 8; 198 } 199 200 /* 201 * Determine the long sample time adder value to be used based 202 * on the default minimum sample time provided. 203 */ 204 adck_period = NSEC_PER_SEC / adck_rate; 205 lst_addr_min = adc_feature->default_sample_time / adck_period; 206 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) { 207 if (vf610_lst_adder[i] > lst_addr_min) { 208 adc_feature->lst_adder_index = i; 209 break; 210 } 211 } 212 213 /* 214 * Calculate ADC sample frequencies 215 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, 216 * which is the same as bus clock. 217 * 218 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 219 * SFCAdder: fixed to 6 ADCK cycles 220 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 221 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 222 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles 223 */ 224 adck_rate = ipg_rate / info->adc_feature.clk_div; 225 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++) 226 info->sample_freq_avail[i] = 227 adck_rate / (6 + vf610_hw_avgs[i] * 228 (25 + vf610_lst_adder[adc_feature->lst_adder_index])); 229 } 230 231 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 232 { 233 struct vf610_adc_feature *adc_feature = &info->adc_feature; 234 235 /* set default Configuration for ADC controller */ 236 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; 237 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET; 238 239 adc_feature->calibration = true; 240 adc_feature->ovwren = true; 241 242 adc_feature->res_mode = 12; 243 adc_feature->sample_rate = 1; 244 245 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; 246 247 vf610_adc_calculate_rates(info); 248 } 249 250 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 251 { 252 struct vf610_adc_feature *adc_feature = &info->adc_feature; 253 int cfg_data = 0; 254 int gc_data = 0; 255 256 switch (adc_feature->clk_sel) { 257 case VF610_ADCIOC_ALTCLK_SET: 258 cfg_data |= VF610_ADC_ALTCLK_SEL; 259 break; 260 case VF610_ADCIOC_ADACK_SET: 261 cfg_data |= VF610_ADC_ADACK_SEL; 262 break; 263 default: 264 break; 265 } 266 267 /* low power set for calibration */ 268 cfg_data |= VF610_ADC_ADLPC_EN; 269 270 /* enable high speed for calibration */ 271 cfg_data |= VF610_ADC_ADHSC_EN; 272 273 /* voltage reference */ 274 switch (adc_feature->vol_ref) { 275 case VF610_ADCIOC_VR_VREF_SET: 276 break; 277 case VF610_ADCIOC_VR_VALT_SET: 278 cfg_data |= VF610_ADC_REFSEL_VALT; 279 break; 280 case VF610_ADCIOC_VR_VBG_SET: 281 cfg_data |= VF610_ADC_REFSEL_VBG; 282 break; 283 default: 284 dev_err(info->dev, "error voltage reference\n"); 285 } 286 287 /* data overwrite enable */ 288 if (adc_feature->ovwren) 289 cfg_data |= VF610_ADC_OVWREN; 290 291 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 292 writel(gc_data, info->regs + VF610_REG_ADC_GC); 293 } 294 295 static void vf610_adc_calibration(struct vf610_adc *info) 296 { 297 int adc_gc, hc_cfg; 298 299 if (!info->adc_feature.calibration) 300 return; 301 302 /* enable calibration interrupt */ 303 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 304 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 305 306 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 307 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 308 309 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT)) 310 dev_err(info->dev, "Timeout for adc calibration\n"); 311 312 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 313 if (adc_gc & VF610_ADC_CALF) 314 dev_err(info->dev, "ADC calibration failed\n"); 315 316 info->adc_feature.calibration = false; 317 } 318 319 static void vf610_adc_cfg_set(struct vf610_adc *info) 320 { 321 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 322 int cfg_data; 323 324 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 325 326 cfg_data &= ~VF610_ADC_ADLPC_EN; 327 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) 328 cfg_data |= VF610_ADC_ADLPC_EN; 329 330 cfg_data &= ~VF610_ADC_ADHSC_EN; 331 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) 332 cfg_data |= VF610_ADC_ADHSC_EN; 333 334 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 335 } 336 337 static void vf610_adc_sample_set(struct vf610_adc *info) 338 { 339 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 340 int cfg_data, gc_data; 341 342 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 343 gc_data = readl(info->regs + VF610_REG_ADC_GC); 344 345 /* resolution mode */ 346 cfg_data &= ~VF610_ADC_MODE_MASK; 347 switch (adc_feature->res_mode) { 348 case 8: 349 cfg_data |= VF610_ADC_MODE_BIT8; 350 break; 351 case 10: 352 cfg_data |= VF610_ADC_MODE_BIT10; 353 break; 354 case 12: 355 cfg_data |= VF610_ADC_MODE_BIT12; 356 break; 357 default: 358 dev_err(info->dev, "error resolution mode\n"); 359 break; 360 } 361 362 /* clock select and clock divider */ 363 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 364 switch (adc_feature->clk_div) { 365 case 1: 366 break; 367 case 2: 368 cfg_data |= VF610_ADC_CLK_DIV2; 369 break; 370 case 4: 371 cfg_data |= VF610_ADC_CLK_DIV4; 372 break; 373 case 8: 374 cfg_data |= VF610_ADC_CLK_DIV8; 375 break; 376 case 16: 377 switch (adc_feature->clk_sel) { 378 case VF610_ADCIOC_BUSCLK_SET: 379 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 380 break; 381 default: 382 dev_err(info->dev, "error clk divider\n"); 383 break; 384 } 385 break; 386 } 387 388 /* 389 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value 390 * determined. 391 */ 392 switch (adc_feature->lst_adder_index) { 393 case VF610_ADCK_CYCLES_3: 394 break; 395 case VF610_ADCK_CYCLES_5: 396 cfg_data |= VF610_ADC_ADSTS_SHORT; 397 break; 398 case VF610_ADCK_CYCLES_7: 399 cfg_data |= VF610_ADC_ADSTS_NORMAL; 400 break; 401 case VF610_ADCK_CYCLES_9: 402 cfg_data |= VF610_ADC_ADSTS_LONG; 403 break; 404 case VF610_ADCK_CYCLES_13: 405 cfg_data |= VF610_ADC_ADLSMP_LONG; 406 break; 407 case VF610_ADCK_CYCLES_17: 408 cfg_data |= VF610_ADC_ADLSMP_LONG; 409 cfg_data |= VF610_ADC_ADSTS_SHORT; 410 break; 411 case VF610_ADCK_CYCLES_21: 412 cfg_data |= VF610_ADC_ADLSMP_LONG; 413 cfg_data |= VF610_ADC_ADSTS_NORMAL; 414 break; 415 case VF610_ADCK_CYCLES_25: 416 cfg_data |= VF610_ADC_ADLSMP_LONG; 417 cfg_data |= VF610_ADC_ADSTS_NORMAL; 418 break; 419 default: 420 dev_err(info->dev, "error in sample time select\n"); 421 } 422 423 /* update hardware average selection */ 424 cfg_data &= ~VF610_ADC_AVGS_MASK; 425 gc_data &= ~VF610_ADC_AVGEN; 426 switch (adc_feature->sample_rate) { 427 case VF610_ADC_SAMPLE_1: 428 break; 429 case VF610_ADC_SAMPLE_4: 430 gc_data |= VF610_ADC_AVGEN; 431 break; 432 case VF610_ADC_SAMPLE_8: 433 gc_data |= VF610_ADC_AVGEN; 434 cfg_data |= VF610_ADC_AVGS_8; 435 break; 436 case VF610_ADC_SAMPLE_16: 437 gc_data |= VF610_ADC_AVGEN; 438 cfg_data |= VF610_ADC_AVGS_16; 439 break; 440 case VF610_ADC_SAMPLE_32: 441 gc_data |= VF610_ADC_AVGEN; 442 cfg_data |= VF610_ADC_AVGS_32; 443 break; 444 default: 445 dev_err(info->dev, 446 "error hardware sample average select\n"); 447 } 448 449 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 450 writel(gc_data, info->regs + VF610_REG_ADC_GC); 451 } 452 453 static void vf610_adc_hw_init(struct vf610_adc *info) 454 { 455 /* CFG: Feature set */ 456 vf610_adc_cfg_post_set(info); 457 vf610_adc_sample_set(info); 458 459 /* adc calibration */ 460 vf610_adc_calibration(info); 461 462 /* CFG: power and speed set */ 463 vf610_adc_cfg_set(info); 464 } 465 466 static int vf610_set_conversion_mode(struct iio_dev *indio_dev, 467 const struct iio_chan_spec *chan, 468 unsigned int mode) 469 { 470 struct vf610_adc *info = iio_priv(indio_dev); 471 472 mutex_lock(&indio_dev->mlock); 473 info->adc_feature.conv_mode = mode; 474 vf610_adc_calculate_rates(info); 475 vf610_adc_hw_init(info); 476 mutex_unlock(&indio_dev->mlock); 477 478 return 0; 479 } 480 481 static int vf610_get_conversion_mode(struct iio_dev *indio_dev, 482 const struct iio_chan_spec *chan) 483 { 484 struct vf610_adc *info = iio_priv(indio_dev); 485 486 return info->adc_feature.conv_mode; 487 } 488 489 static const char * const vf610_conv_modes[] = { "normal", "high-speed", 490 "low-power" }; 491 492 static const struct iio_enum vf610_conversion_mode = { 493 .items = vf610_conv_modes, 494 .num_items = ARRAY_SIZE(vf610_conv_modes), 495 .get = vf610_get_conversion_mode, 496 .set = vf610_set_conversion_mode, 497 }; 498 499 static const struct iio_chan_spec_ext_info vf610_ext_info[] = { 500 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), 501 {}, 502 }; 503 504 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 505 .type = (_chan_type), \ 506 .indexed = 1, \ 507 .channel = (_idx), \ 508 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 509 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 510 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 511 .ext_info = vf610_ext_info, \ 512 .scan_index = (_idx), \ 513 .scan_type = { \ 514 .sign = 'u', \ 515 .realbits = 12, \ 516 .storagebits = 16, \ 517 }, \ 518 } 519 520 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 521 .type = (_chan_type), \ 522 .channel = (_idx), \ 523 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 524 .scan_index = (_idx), \ 525 .scan_type = { \ 526 .sign = 'u', \ 527 .realbits = 12, \ 528 .storagebits = 16, \ 529 }, \ 530 } 531 532 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 533 VF610_ADC_CHAN(0, IIO_VOLTAGE), 534 VF610_ADC_CHAN(1, IIO_VOLTAGE), 535 VF610_ADC_CHAN(2, IIO_VOLTAGE), 536 VF610_ADC_CHAN(3, IIO_VOLTAGE), 537 VF610_ADC_CHAN(4, IIO_VOLTAGE), 538 VF610_ADC_CHAN(5, IIO_VOLTAGE), 539 VF610_ADC_CHAN(6, IIO_VOLTAGE), 540 VF610_ADC_CHAN(7, IIO_VOLTAGE), 541 VF610_ADC_CHAN(8, IIO_VOLTAGE), 542 VF610_ADC_CHAN(9, IIO_VOLTAGE), 543 VF610_ADC_CHAN(10, IIO_VOLTAGE), 544 VF610_ADC_CHAN(11, IIO_VOLTAGE), 545 VF610_ADC_CHAN(12, IIO_VOLTAGE), 546 VF610_ADC_CHAN(13, IIO_VOLTAGE), 547 VF610_ADC_CHAN(14, IIO_VOLTAGE), 548 VF610_ADC_CHAN(15, IIO_VOLTAGE), 549 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 550 IIO_CHAN_SOFT_TIMESTAMP(32), 551 /* sentinel */ 552 }; 553 554 static int vf610_adc_read_data(struct vf610_adc *info) 555 { 556 int result; 557 558 result = readl(info->regs + VF610_REG_ADC_R0); 559 560 switch (info->adc_feature.res_mode) { 561 case 8: 562 result &= 0xFF; 563 break; 564 case 10: 565 result &= 0x3FF; 566 break; 567 case 12: 568 result &= 0xFFF; 569 break; 570 default: 571 break; 572 } 573 574 return result; 575 } 576 577 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 578 { 579 struct iio_dev *indio_dev = (struct iio_dev *)dev_id; 580 struct vf610_adc *info = iio_priv(indio_dev); 581 int coco; 582 583 coco = readl(info->regs + VF610_REG_ADC_HS); 584 if (coco & VF610_ADC_HS_COCO0) { 585 info->value = vf610_adc_read_data(info); 586 if (iio_buffer_enabled(indio_dev)) { 587 info->buffer[0] = info->value; 588 iio_push_to_buffers_with_timestamp(indio_dev, 589 info->buffer, iio_get_time_ns()); 590 iio_trigger_notify_done(indio_dev->trig); 591 } else 592 complete(&info->completion); 593 } 594 595 return IRQ_HANDLED; 596 } 597 598 static ssize_t vf610_show_samp_freq_avail(struct device *dev, 599 struct device_attribute *attr, char *buf) 600 { 601 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev)); 602 size_t len = 0; 603 int i; 604 605 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++) 606 len += scnprintf(buf + len, PAGE_SIZE - len, 607 "%u ", info->sample_freq_avail[i]); 608 609 /* replace trailing space by newline */ 610 buf[len - 1] = '\n'; 611 612 return len; 613 } 614 615 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail); 616 617 static struct attribute *vf610_attributes[] = { 618 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 619 NULL 620 }; 621 622 static const struct attribute_group vf610_attribute_group = { 623 .attrs = vf610_attributes, 624 }; 625 626 static int vf610_read_raw(struct iio_dev *indio_dev, 627 struct iio_chan_spec const *chan, 628 int *val, 629 int *val2, 630 long mask) 631 { 632 struct vf610_adc *info = iio_priv(indio_dev); 633 unsigned int hc_cfg; 634 long ret; 635 636 switch (mask) { 637 case IIO_CHAN_INFO_RAW: 638 case IIO_CHAN_INFO_PROCESSED: 639 mutex_lock(&indio_dev->mlock); 640 if (iio_buffer_enabled(indio_dev)) { 641 mutex_unlock(&indio_dev->mlock); 642 return -EBUSY; 643 } 644 645 reinit_completion(&info->completion); 646 hc_cfg = VF610_ADC_ADCHC(chan->channel); 647 hc_cfg |= VF610_ADC_AIEN; 648 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 649 ret = wait_for_completion_interruptible_timeout 650 (&info->completion, VF610_ADC_TIMEOUT); 651 if (ret == 0) { 652 mutex_unlock(&indio_dev->mlock); 653 return -ETIMEDOUT; 654 } 655 if (ret < 0) { 656 mutex_unlock(&indio_dev->mlock); 657 return ret; 658 } 659 660 switch (chan->type) { 661 case IIO_VOLTAGE: 662 *val = info->value; 663 break; 664 case IIO_TEMP: 665 /* 666 * Calculate in degree Celsius times 1000 667 * Using sensor slope of 1.84 mV/°C and 668 * V at 25°C of 696 mV 669 */ 670 *val = 25000 - ((int)info->value - 864) * 1000000 / 1840; 671 break; 672 default: 673 mutex_unlock(&indio_dev->mlock); 674 return -EINVAL; 675 } 676 677 mutex_unlock(&indio_dev->mlock); 678 return IIO_VAL_INT; 679 680 case IIO_CHAN_INFO_SCALE: 681 *val = info->vref_uv / 1000; 682 *val2 = info->adc_feature.res_mode; 683 return IIO_VAL_FRACTIONAL_LOG2; 684 685 case IIO_CHAN_INFO_SAMP_FREQ: 686 *val = info->sample_freq_avail[info->adc_feature.sample_rate]; 687 *val2 = 0; 688 return IIO_VAL_INT; 689 690 default: 691 break; 692 } 693 694 return -EINVAL; 695 } 696 697 static int vf610_write_raw(struct iio_dev *indio_dev, 698 struct iio_chan_spec const *chan, 699 int val, 700 int val2, 701 long mask) 702 { 703 struct vf610_adc *info = iio_priv(indio_dev); 704 int i; 705 706 switch (mask) { 707 case IIO_CHAN_INFO_SAMP_FREQ: 708 for (i = 0; 709 i < ARRAY_SIZE(info->sample_freq_avail); 710 i++) 711 if (val == info->sample_freq_avail[i]) { 712 info->adc_feature.sample_rate = i; 713 vf610_adc_sample_set(info); 714 return 0; 715 } 716 break; 717 718 default: 719 break; 720 } 721 722 return -EINVAL; 723 } 724 725 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev) 726 { 727 struct vf610_adc *info = iio_priv(indio_dev); 728 unsigned int channel; 729 int ret; 730 int val; 731 732 ret = iio_triggered_buffer_postenable(indio_dev); 733 if (ret) 734 return ret; 735 736 val = readl(info->regs + VF610_REG_ADC_GC); 737 val |= VF610_ADC_ADCON; 738 writel(val, info->regs + VF610_REG_ADC_GC); 739 740 channel = find_first_bit(indio_dev->active_scan_mask, 741 indio_dev->masklength); 742 743 val = VF610_ADC_ADCHC(channel); 744 val |= VF610_ADC_AIEN; 745 746 writel(val, info->regs + VF610_REG_ADC_HC0); 747 748 return 0; 749 } 750 751 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev) 752 { 753 struct vf610_adc *info = iio_priv(indio_dev); 754 unsigned int hc_cfg = 0; 755 int val; 756 757 val = readl(info->regs + VF610_REG_ADC_GC); 758 val &= ~VF610_ADC_ADCON; 759 writel(val, info->regs + VF610_REG_ADC_GC); 760 761 hc_cfg |= VF610_ADC_CONV_DISABLE; 762 hc_cfg &= ~VF610_ADC_AIEN; 763 764 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 765 766 return iio_triggered_buffer_predisable(indio_dev); 767 } 768 769 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { 770 .postenable = &vf610_adc_buffer_postenable, 771 .predisable = &vf610_adc_buffer_predisable, 772 .validate_scan_mask = &iio_validate_scan_mask_onehot, 773 }; 774 775 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 776 unsigned reg, unsigned writeval, 777 unsigned *readval) 778 { 779 struct vf610_adc *info = iio_priv(indio_dev); 780 781 if ((readval == NULL) || 782 ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) 783 return -EINVAL; 784 785 *readval = readl(info->regs + reg); 786 787 return 0; 788 } 789 790 static const struct iio_info vf610_adc_iio_info = { 791 .driver_module = THIS_MODULE, 792 .read_raw = &vf610_read_raw, 793 .write_raw = &vf610_write_raw, 794 .debugfs_reg_access = &vf610_adc_reg_access, 795 .attrs = &vf610_attribute_group, 796 }; 797 798 static const struct of_device_id vf610_adc_match[] = { 799 { .compatible = "fsl,vf610-adc", }, 800 { /* sentinel */ } 801 }; 802 MODULE_DEVICE_TABLE(of, vf610_adc_match); 803 804 static int vf610_adc_probe(struct platform_device *pdev) 805 { 806 struct vf610_adc *info; 807 struct iio_dev *indio_dev; 808 struct resource *mem; 809 int irq; 810 int ret; 811 812 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 813 if (!indio_dev) { 814 dev_err(&pdev->dev, "Failed allocating iio device\n"); 815 return -ENOMEM; 816 } 817 818 info = iio_priv(indio_dev); 819 info->dev = &pdev->dev; 820 821 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 822 info->regs = devm_ioremap_resource(&pdev->dev, mem); 823 if (IS_ERR(info->regs)) 824 return PTR_ERR(info->regs); 825 826 irq = platform_get_irq(pdev, 0); 827 if (irq < 0) { 828 dev_err(&pdev->dev, "no irq resource?\n"); 829 return irq; 830 } 831 832 ret = devm_request_irq(info->dev, irq, 833 vf610_adc_isr, 0, 834 dev_name(&pdev->dev), indio_dev); 835 if (ret < 0) { 836 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq); 837 return ret; 838 } 839 840 info->clk = devm_clk_get(&pdev->dev, "adc"); 841 if (IS_ERR(info->clk)) { 842 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 843 PTR_ERR(info->clk)); 844 return PTR_ERR(info->clk); 845 } 846 847 info->vref = devm_regulator_get(&pdev->dev, "vref"); 848 if (IS_ERR(info->vref)) 849 return PTR_ERR(info->vref); 850 851 ret = regulator_enable(info->vref); 852 if (ret) 853 return ret; 854 855 info->vref_uv = regulator_get_voltage(info->vref); 856 857 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency", 858 info->max_adck_rate, 3); 859 860 ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time", 861 &info->adc_feature.default_sample_time); 862 if (ret) 863 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; 864 865 platform_set_drvdata(pdev, indio_dev); 866 867 init_completion(&info->completion); 868 869 indio_dev->name = dev_name(&pdev->dev); 870 indio_dev->dev.parent = &pdev->dev; 871 indio_dev->dev.of_node = pdev->dev.of_node; 872 indio_dev->info = &vf610_adc_iio_info; 873 indio_dev->modes = INDIO_DIRECT_MODE; 874 indio_dev->channels = vf610_adc_iio_channels; 875 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels); 876 877 ret = clk_prepare_enable(info->clk); 878 if (ret) { 879 dev_err(&pdev->dev, 880 "Could not prepare or enable the clock.\n"); 881 goto error_adc_clk_enable; 882 } 883 884 vf610_adc_cfg_init(info); 885 vf610_adc_hw_init(info); 886 887 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, 888 NULL, &iio_triggered_buffer_setup_ops); 889 if (ret < 0) { 890 dev_err(&pdev->dev, "Couldn't initialise the buffer\n"); 891 goto error_iio_device_register; 892 } 893 894 ret = iio_device_register(indio_dev); 895 if (ret) { 896 dev_err(&pdev->dev, "Couldn't register the device.\n"); 897 goto error_adc_buffer_init; 898 } 899 900 return 0; 901 902 error_adc_buffer_init: 903 iio_triggered_buffer_cleanup(indio_dev); 904 error_iio_device_register: 905 clk_disable_unprepare(info->clk); 906 error_adc_clk_enable: 907 regulator_disable(info->vref); 908 909 return ret; 910 } 911 912 static int vf610_adc_remove(struct platform_device *pdev) 913 { 914 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 915 struct vf610_adc *info = iio_priv(indio_dev); 916 917 iio_device_unregister(indio_dev); 918 iio_triggered_buffer_cleanup(indio_dev); 919 regulator_disable(info->vref); 920 clk_disable_unprepare(info->clk); 921 922 return 0; 923 } 924 925 #ifdef CONFIG_PM_SLEEP 926 static int vf610_adc_suspend(struct device *dev) 927 { 928 struct iio_dev *indio_dev = dev_get_drvdata(dev); 929 struct vf610_adc *info = iio_priv(indio_dev); 930 int hc_cfg; 931 932 /* ADC controller enters to stop mode */ 933 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 934 hc_cfg |= VF610_ADC_CONV_DISABLE; 935 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 936 937 clk_disable_unprepare(info->clk); 938 regulator_disable(info->vref); 939 940 return 0; 941 } 942 943 static int vf610_adc_resume(struct device *dev) 944 { 945 struct iio_dev *indio_dev = dev_get_drvdata(dev); 946 struct vf610_adc *info = iio_priv(indio_dev); 947 int ret; 948 949 ret = regulator_enable(info->vref); 950 if (ret) 951 return ret; 952 953 ret = clk_prepare_enable(info->clk); 954 if (ret) 955 goto disable_reg; 956 957 vf610_adc_hw_init(info); 958 959 return 0; 960 961 disable_reg: 962 regulator_disable(info->vref); 963 return ret; 964 } 965 #endif 966 967 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume); 968 969 static struct platform_driver vf610_adc_driver = { 970 .probe = vf610_adc_probe, 971 .remove = vf610_adc_remove, 972 .driver = { 973 .name = DRIVER_NAME, 974 .of_match_table = vf610_adc_match, 975 .pm = &vf610_adc_pm_ops, 976 }, 977 }; 978 979 module_platform_driver(vf610_adc_driver); 980 981 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 982 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 983 MODULE_LICENSE("GPL v2"); 984