1 /* 2 * Freescale Vybrid vf610 ADC driver 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/io.h> 28 #include <linux/clk.h> 29 #include <linux/completion.h> 30 #include <linux/of.h> 31 #include <linux/of_irq.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/of_platform.h> 34 #include <linux/err.h> 35 36 #include <linux/iio/iio.h> 37 #include <linux/iio/sysfs.h> 38 #include <linux/iio/driver.h> 39 40 /* This will be the driver name the kernel reports */ 41 #define DRIVER_NAME "vf610-adc" 42 43 /* Vybrid/IMX ADC registers */ 44 #define VF610_REG_ADC_HC0 0x00 45 #define VF610_REG_ADC_HC1 0x04 46 #define VF610_REG_ADC_HS 0x08 47 #define VF610_REG_ADC_R0 0x0c 48 #define VF610_REG_ADC_R1 0x10 49 #define VF610_REG_ADC_CFG 0x14 50 #define VF610_REG_ADC_GC 0x18 51 #define VF610_REG_ADC_GS 0x1c 52 #define VF610_REG_ADC_CV 0x20 53 #define VF610_REG_ADC_OFS 0x24 54 #define VF610_REG_ADC_CAL 0x28 55 #define VF610_REG_ADC_PCTL 0x30 56 57 /* Configuration register field define */ 58 #define VF610_ADC_MODE_BIT8 0x00 59 #define VF610_ADC_MODE_BIT10 0x04 60 #define VF610_ADC_MODE_BIT12 0x08 61 #define VF610_ADC_MODE_MASK 0x0c 62 #define VF610_ADC_BUSCLK2_SEL 0x01 63 #define VF610_ADC_ALTCLK_SEL 0x02 64 #define VF610_ADC_ADACK_SEL 0x03 65 #define VF610_ADC_ADCCLK_MASK 0x03 66 #define VF610_ADC_CLK_DIV2 0x20 67 #define VF610_ADC_CLK_DIV4 0x40 68 #define VF610_ADC_CLK_DIV8 0x60 69 #define VF610_ADC_CLK_MASK 0x60 70 #define VF610_ADC_ADLSMP_LONG 0x10 71 #define VF610_ADC_ADSTS_MASK 0x300 72 #define VF610_ADC_ADLPC_EN 0x80 73 #define VF610_ADC_ADHSC_EN 0x400 74 #define VF610_ADC_REFSEL_VALT 0x100 75 #define VF610_ADC_REFSEL_VBG 0x1000 76 #define VF610_ADC_ADTRG_HARD 0x2000 77 #define VF610_ADC_AVGS_8 0x4000 78 #define VF610_ADC_AVGS_16 0x8000 79 #define VF610_ADC_AVGS_32 0xC000 80 #define VF610_ADC_AVGS_MASK 0xC000 81 #define VF610_ADC_OVWREN 0x10000 82 83 /* General control register field define */ 84 #define VF610_ADC_ADACKEN 0x1 85 #define VF610_ADC_DMAEN 0x2 86 #define VF610_ADC_ACREN 0x4 87 #define VF610_ADC_ACFGT 0x8 88 #define VF610_ADC_ACFE 0x10 89 #define VF610_ADC_AVGEN 0x20 90 #define VF610_ADC_ADCON 0x40 91 #define VF610_ADC_CAL 0x80 92 93 /* Other field define */ 94 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 95 #define VF610_ADC_AIEN (0x1 << 7) 96 #define VF610_ADC_CONV_DISABLE 0x1F 97 #define VF610_ADC_HS_COCO0 0x1 98 #define VF610_ADC_CALF 0x2 99 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 100 101 enum clk_sel { 102 VF610_ADCIOC_BUSCLK_SET, 103 VF610_ADCIOC_ALTCLK_SET, 104 VF610_ADCIOC_ADACK_SET, 105 }; 106 107 enum vol_ref { 108 VF610_ADCIOC_VR_VREF_SET, 109 VF610_ADCIOC_VR_VALT_SET, 110 VF610_ADCIOC_VR_VBG_SET, 111 }; 112 113 enum average_sel { 114 VF610_ADC_SAMPLE_1, 115 VF610_ADC_SAMPLE_4, 116 VF610_ADC_SAMPLE_8, 117 VF610_ADC_SAMPLE_16, 118 VF610_ADC_SAMPLE_32, 119 }; 120 121 struct vf610_adc_feature { 122 enum clk_sel clk_sel; 123 enum vol_ref vol_ref; 124 125 int clk_div; 126 int sample_rate; 127 int res_mode; 128 129 bool lpm; 130 bool calibration; 131 bool ovwren; 132 }; 133 134 struct vf610_adc { 135 struct device *dev; 136 void __iomem *regs; 137 struct clk *clk; 138 139 u32 vref_uv; 140 u32 value; 141 struct regulator *vref; 142 struct vf610_adc_feature adc_feature; 143 144 struct completion completion; 145 }; 146 147 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 148 .type = (_chan_type), \ 149 .indexed = 1, \ 150 .channel = (_idx), \ 151 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 152 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 153 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 154 } 155 156 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 157 .type = (_chan_type), \ 158 .channel = (_idx), \ 159 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 160 } 161 162 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 163 VF610_ADC_CHAN(0, IIO_VOLTAGE), 164 VF610_ADC_CHAN(1, IIO_VOLTAGE), 165 VF610_ADC_CHAN(2, IIO_VOLTAGE), 166 VF610_ADC_CHAN(3, IIO_VOLTAGE), 167 VF610_ADC_CHAN(4, IIO_VOLTAGE), 168 VF610_ADC_CHAN(5, IIO_VOLTAGE), 169 VF610_ADC_CHAN(6, IIO_VOLTAGE), 170 VF610_ADC_CHAN(7, IIO_VOLTAGE), 171 VF610_ADC_CHAN(8, IIO_VOLTAGE), 172 VF610_ADC_CHAN(9, IIO_VOLTAGE), 173 VF610_ADC_CHAN(10, IIO_VOLTAGE), 174 VF610_ADC_CHAN(11, IIO_VOLTAGE), 175 VF610_ADC_CHAN(12, IIO_VOLTAGE), 176 VF610_ADC_CHAN(13, IIO_VOLTAGE), 177 VF610_ADC_CHAN(14, IIO_VOLTAGE), 178 VF610_ADC_CHAN(15, IIO_VOLTAGE), 179 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 180 /* sentinel */ 181 }; 182 183 /* 184 * ADC sample frequency, unit is ADCK cycles. 185 * ADC clk source is ipg clock, which is the same as bus clock. 186 * 187 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 188 * SFCAdder: fixed to 6 ADCK cycles 189 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 190 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 191 * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles 192 * 193 * By default, enable 12 bit resolution mode, clock source 194 * set to ipg clock, So get below frequency group: 195 */ 196 static const u32 vf610_sample_freq_avail[5] = 197 {1941176, 559332, 286957, 145374, 73171}; 198 199 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 200 { 201 /* set default Configuration for ADC controller */ 202 info->adc_feature.clk_sel = VF610_ADCIOC_BUSCLK_SET; 203 info->adc_feature.vol_ref = VF610_ADCIOC_VR_VREF_SET; 204 205 info->adc_feature.calibration = true; 206 info->adc_feature.ovwren = true; 207 208 info->adc_feature.clk_div = 1; 209 info->adc_feature.res_mode = 12; 210 info->adc_feature.sample_rate = 1; 211 info->adc_feature.lpm = true; 212 } 213 214 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 215 { 216 struct vf610_adc_feature *adc_feature = &info->adc_feature; 217 int cfg_data = 0; 218 int gc_data = 0; 219 220 switch (adc_feature->clk_sel) { 221 case VF610_ADCIOC_ALTCLK_SET: 222 cfg_data |= VF610_ADC_ALTCLK_SEL; 223 break; 224 case VF610_ADCIOC_ADACK_SET: 225 cfg_data |= VF610_ADC_ADACK_SEL; 226 break; 227 default: 228 break; 229 } 230 231 /* low power set for calibration */ 232 cfg_data |= VF610_ADC_ADLPC_EN; 233 234 /* enable high speed for calibration */ 235 cfg_data |= VF610_ADC_ADHSC_EN; 236 237 /* voltage reference */ 238 switch (adc_feature->vol_ref) { 239 case VF610_ADCIOC_VR_VREF_SET: 240 break; 241 case VF610_ADCIOC_VR_VALT_SET: 242 cfg_data |= VF610_ADC_REFSEL_VALT; 243 break; 244 case VF610_ADCIOC_VR_VBG_SET: 245 cfg_data |= VF610_ADC_REFSEL_VBG; 246 break; 247 default: 248 dev_err(info->dev, "error voltage reference\n"); 249 } 250 251 /* data overwrite enable */ 252 if (adc_feature->ovwren) 253 cfg_data |= VF610_ADC_OVWREN; 254 255 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 256 writel(gc_data, info->regs + VF610_REG_ADC_GC); 257 } 258 259 static void vf610_adc_calibration(struct vf610_adc *info) 260 { 261 int adc_gc, hc_cfg; 262 int timeout; 263 264 if (!info->adc_feature.calibration) 265 return; 266 267 /* enable calibration interrupt */ 268 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 269 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 270 271 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 272 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 273 274 timeout = wait_for_completion_timeout 275 (&info->completion, VF610_ADC_TIMEOUT); 276 if (timeout == 0) 277 dev_err(info->dev, "Timeout for adc calibration\n"); 278 279 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 280 if (adc_gc & VF610_ADC_CALF) 281 dev_err(info->dev, "ADC calibration failed\n"); 282 283 info->adc_feature.calibration = false; 284 } 285 286 static void vf610_adc_cfg_set(struct vf610_adc *info) 287 { 288 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 289 int cfg_data; 290 291 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 292 293 /* low power configuration */ 294 cfg_data &= ~VF610_ADC_ADLPC_EN; 295 if (adc_feature->lpm) 296 cfg_data |= VF610_ADC_ADLPC_EN; 297 298 /* disable high speed */ 299 cfg_data &= ~VF610_ADC_ADHSC_EN; 300 301 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 302 } 303 304 static void vf610_adc_sample_set(struct vf610_adc *info) 305 { 306 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 307 int cfg_data, gc_data; 308 309 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 310 gc_data = readl(info->regs + VF610_REG_ADC_GC); 311 312 /* resolution mode */ 313 cfg_data &= ~VF610_ADC_MODE_MASK; 314 switch (adc_feature->res_mode) { 315 case 8: 316 cfg_data |= VF610_ADC_MODE_BIT8; 317 break; 318 case 10: 319 cfg_data |= VF610_ADC_MODE_BIT10; 320 break; 321 case 12: 322 cfg_data |= VF610_ADC_MODE_BIT12; 323 break; 324 default: 325 dev_err(info->dev, "error resolution mode\n"); 326 break; 327 } 328 329 /* clock select and clock divider */ 330 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 331 switch (adc_feature->clk_div) { 332 case 1: 333 break; 334 case 2: 335 cfg_data |= VF610_ADC_CLK_DIV2; 336 break; 337 case 4: 338 cfg_data |= VF610_ADC_CLK_DIV4; 339 break; 340 case 8: 341 cfg_data |= VF610_ADC_CLK_DIV8; 342 break; 343 case 16: 344 switch (adc_feature->clk_sel) { 345 case VF610_ADCIOC_BUSCLK_SET: 346 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 347 break; 348 default: 349 dev_err(info->dev, "error clk divider\n"); 350 break; 351 } 352 break; 353 } 354 355 /* Use the short sample mode */ 356 cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK); 357 358 /* update hardware average selection */ 359 cfg_data &= ~VF610_ADC_AVGS_MASK; 360 gc_data &= ~VF610_ADC_AVGEN; 361 switch (adc_feature->sample_rate) { 362 case VF610_ADC_SAMPLE_1: 363 break; 364 case VF610_ADC_SAMPLE_4: 365 gc_data |= VF610_ADC_AVGEN; 366 break; 367 case VF610_ADC_SAMPLE_8: 368 gc_data |= VF610_ADC_AVGEN; 369 cfg_data |= VF610_ADC_AVGS_8; 370 break; 371 case VF610_ADC_SAMPLE_16: 372 gc_data |= VF610_ADC_AVGEN; 373 cfg_data |= VF610_ADC_AVGS_16; 374 break; 375 case VF610_ADC_SAMPLE_32: 376 gc_data |= VF610_ADC_AVGEN; 377 cfg_data |= VF610_ADC_AVGS_32; 378 break; 379 default: 380 dev_err(info->dev, 381 "error hardware sample average select\n"); 382 } 383 384 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 385 writel(gc_data, info->regs + VF610_REG_ADC_GC); 386 } 387 388 static void vf610_adc_hw_init(struct vf610_adc *info) 389 { 390 /* CFG: Feature set */ 391 vf610_adc_cfg_post_set(info); 392 vf610_adc_sample_set(info); 393 394 /* adc calibration */ 395 vf610_adc_calibration(info); 396 397 /* CFG: power and speed set */ 398 vf610_adc_cfg_set(info); 399 } 400 401 static int vf610_adc_read_data(struct vf610_adc *info) 402 { 403 int result; 404 405 result = readl(info->regs + VF610_REG_ADC_R0); 406 407 switch (info->adc_feature.res_mode) { 408 case 8: 409 result &= 0xFF; 410 break; 411 case 10: 412 result &= 0x3FF; 413 break; 414 case 12: 415 result &= 0xFFF; 416 break; 417 default: 418 break; 419 } 420 421 return result; 422 } 423 424 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 425 { 426 struct vf610_adc *info = (struct vf610_adc *)dev_id; 427 int coco; 428 429 coco = readl(info->regs + VF610_REG_ADC_HS); 430 if (coco & VF610_ADC_HS_COCO0) { 431 info->value = vf610_adc_read_data(info); 432 complete(&info->completion); 433 } 434 435 return IRQ_HANDLED; 436 } 437 438 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1941176, 559332, 286957, 145374, 73171"); 439 440 static struct attribute *vf610_attributes[] = { 441 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 442 NULL 443 }; 444 445 static const struct attribute_group vf610_attribute_group = { 446 .attrs = vf610_attributes, 447 }; 448 449 static int vf610_read_raw(struct iio_dev *indio_dev, 450 struct iio_chan_spec const *chan, 451 int *val, 452 int *val2, 453 long mask) 454 { 455 struct vf610_adc *info = iio_priv(indio_dev); 456 unsigned int hc_cfg; 457 long ret; 458 459 switch (mask) { 460 case IIO_CHAN_INFO_RAW: 461 case IIO_CHAN_INFO_PROCESSED: 462 mutex_lock(&indio_dev->mlock); 463 reinit_completion(&info->completion); 464 465 hc_cfg = VF610_ADC_ADCHC(chan->channel); 466 hc_cfg |= VF610_ADC_AIEN; 467 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 468 ret = wait_for_completion_interruptible_timeout 469 (&info->completion, VF610_ADC_TIMEOUT); 470 if (ret == 0) { 471 mutex_unlock(&indio_dev->mlock); 472 return -ETIMEDOUT; 473 } 474 if (ret < 0) { 475 mutex_unlock(&indio_dev->mlock); 476 return ret; 477 } 478 479 switch (chan->type) { 480 case IIO_VOLTAGE: 481 *val = info->value; 482 break; 483 case IIO_TEMP: 484 /* 485 * Calculate in degree Celsius times 1000 486 * Using sensor slope of 1.84 mV/°C and 487 * V at 25°C of 696 mV 488 */ 489 *val = 25000 - ((int)info->value - 864) * 1000000 / 1840; 490 break; 491 default: 492 mutex_unlock(&indio_dev->mlock); 493 return -EINVAL; 494 } 495 496 mutex_unlock(&indio_dev->mlock); 497 return IIO_VAL_INT; 498 499 case IIO_CHAN_INFO_SCALE: 500 *val = info->vref_uv / 1000; 501 *val2 = info->adc_feature.res_mode; 502 return IIO_VAL_FRACTIONAL_LOG2; 503 504 case IIO_CHAN_INFO_SAMP_FREQ: 505 *val = vf610_sample_freq_avail[info->adc_feature.sample_rate]; 506 *val2 = 0; 507 return IIO_VAL_INT; 508 509 default: 510 break; 511 } 512 513 return -EINVAL; 514 } 515 516 static int vf610_write_raw(struct iio_dev *indio_dev, 517 struct iio_chan_spec const *chan, 518 int val, 519 int val2, 520 long mask) 521 { 522 struct vf610_adc *info = iio_priv(indio_dev); 523 int i; 524 525 switch (mask) { 526 case IIO_CHAN_INFO_SAMP_FREQ: 527 for (i = 0; 528 i < ARRAY_SIZE(vf610_sample_freq_avail); 529 i++) 530 if (val == vf610_sample_freq_avail[i]) { 531 info->adc_feature.sample_rate = i; 532 vf610_adc_sample_set(info); 533 return 0; 534 } 535 break; 536 537 default: 538 break; 539 } 540 541 return -EINVAL; 542 } 543 544 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 545 unsigned reg, unsigned writeval, 546 unsigned *readval) 547 { 548 struct vf610_adc *info = iio_priv(indio_dev); 549 550 if ((readval == NULL) || 551 (!(reg % 4) || (reg > VF610_REG_ADC_PCTL))) 552 return -EINVAL; 553 554 *readval = readl(info->regs + reg); 555 556 return 0; 557 } 558 559 static const struct iio_info vf610_adc_iio_info = { 560 .driver_module = THIS_MODULE, 561 .read_raw = &vf610_read_raw, 562 .write_raw = &vf610_write_raw, 563 .debugfs_reg_access = &vf610_adc_reg_access, 564 .attrs = &vf610_attribute_group, 565 }; 566 567 static const struct of_device_id vf610_adc_match[] = { 568 { .compatible = "fsl,vf610-adc", }, 569 { /* sentinel */ } 570 }; 571 MODULE_DEVICE_TABLE(of, vf610_adc_match); 572 573 static int vf610_adc_probe(struct platform_device *pdev) 574 { 575 struct vf610_adc *info; 576 struct iio_dev *indio_dev; 577 struct resource *mem; 578 int irq; 579 int ret; 580 581 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 582 if (!indio_dev) { 583 dev_err(&pdev->dev, "Failed allocating iio device\n"); 584 return -ENOMEM; 585 } 586 587 info = iio_priv(indio_dev); 588 info->dev = &pdev->dev; 589 590 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 591 info->regs = devm_ioremap_resource(&pdev->dev, mem); 592 if (IS_ERR(info->regs)) 593 return PTR_ERR(info->regs); 594 595 irq = platform_get_irq(pdev, 0); 596 if (irq < 0) { 597 dev_err(&pdev->dev, "no irq resource?\n"); 598 return irq; 599 } 600 601 ret = devm_request_irq(info->dev, irq, 602 vf610_adc_isr, 0, 603 dev_name(&pdev->dev), info); 604 if (ret < 0) { 605 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq); 606 return ret; 607 } 608 609 info->clk = devm_clk_get(&pdev->dev, "adc"); 610 if (IS_ERR(info->clk)) { 611 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 612 PTR_ERR(info->clk)); 613 return PTR_ERR(info->clk); 614 } 615 616 info->vref = devm_regulator_get(&pdev->dev, "vref"); 617 if (IS_ERR(info->vref)) 618 return PTR_ERR(info->vref); 619 620 ret = regulator_enable(info->vref); 621 if (ret) 622 return ret; 623 624 info->vref_uv = regulator_get_voltage(info->vref); 625 626 platform_set_drvdata(pdev, indio_dev); 627 628 init_completion(&info->completion); 629 630 indio_dev->name = dev_name(&pdev->dev); 631 indio_dev->dev.parent = &pdev->dev; 632 indio_dev->dev.of_node = pdev->dev.of_node; 633 indio_dev->info = &vf610_adc_iio_info; 634 indio_dev->modes = INDIO_DIRECT_MODE; 635 indio_dev->channels = vf610_adc_iio_channels; 636 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels); 637 638 ret = clk_prepare_enable(info->clk); 639 if (ret) { 640 dev_err(&pdev->dev, 641 "Could not prepare or enable the clock.\n"); 642 goto error_adc_clk_enable; 643 } 644 645 vf610_adc_cfg_init(info); 646 vf610_adc_hw_init(info); 647 648 ret = iio_device_register(indio_dev); 649 if (ret) { 650 dev_err(&pdev->dev, "Couldn't register the device.\n"); 651 goto error_iio_device_register; 652 } 653 654 return 0; 655 656 657 error_iio_device_register: 658 clk_disable_unprepare(info->clk); 659 error_adc_clk_enable: 660 regulator_disable(info->vref); 661 662 return ret; 663 } 664 665 static int vf610_adc_remove(struct platform_device *pdev) 666 { 667 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 668 struct vf610_adc *info = iio_priv(indio_dev); 669 670 iio_device_unregister(indio_dev); 671 regulator_disable(info->vref); 672 clk_disable_unprepare(info->clk); 673 674 return 0; 675 } 676 677 #ifdef CONFIG_PM_SLEEP 678 static int vf610_adc_suspend(struct device *dev) 679 { 680 struct iio_dev *indio_dev = dev_get_drvdata(dev); 681 struct vf610_adc *info = iio_priv(indio_dev); 682 int hc_cfg; 683 684 /* ADC controller enters to stop mode */ 685 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 686 hc_cfg |= VF610_ADC_CONV_DISABLE; 687 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 688 689 clk_disable_unprepare(info->clk); 690 regulator_disable(info->vref); 691 692 return 0; 693 } 694 695 static int vf610_adc_resume(struct device *dev) 696 { 697 struct iio_dev *indio_dev = dev_get_drvdata(dev); 698 struct vf610_adc *info = iio_priv(indio_dev); 699 int ret; 700 701 ret = regulator_enable(info->vref); 702 if (ret) 703 return ret; 704 705 ret = clk_prepare_enable(info->clk); 706 if (ret) 707 goto disable_reg; 708 709 vf610_adc_hw_init(info); 710 711 return 0; 712 713 disable_reg: 714 regulator_disable(info->vref); 715 return ret; 716 } 717 #endif 718 719 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume); 720 721 static struct platform_driver vf610_adc_driver = { 722 .probe = vf610_adc_probe, 723 .remove = vf610_adc_remove, 724 .driver = { 725 .name = DRIVER_NAME, 726 .of_match_table = vf610_adc_match, 727 .pm = &vf610_adc_pm_ops, 728 }, 729 }; 730 731 module_platform_driver(vf610_adc_driver); 732 733 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 734 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 735 MODULE_LICENSE("GPL v2"); 736