1 /* 2 * 3 * TWL4030 MADC module driver-This driver monitors the real time 4 * conversion of analog signals like battery temperature, 5 * battery type, battery level etc. 6 * 7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 8 * J Keerthy <j-keerthy@ti.com> 9 * 10 * Based on twl4030-madc.c 11 * Copyright (C) 2008 Nokia Corporation 12 * Mikko Ylinen <mikko.k.ylinen@nokia.com> 13 * 14 * Amit Kucheria <amit.kucheria@canonical.com> 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License 18 * version 2 as published by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, but 21 * WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 * General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 28 * 02110-1301 USA 29 * 30 */ 31 32 #include <linux/device.h> 33 #include <linux/interrupt.h> 34 #include <linux/kernel.h> 35 #include <linux/delay.h> 36 #include <linux/platform_device.h> 37 #include <linux/slab.h> 38 #include <linux/mfd/twl.h> 39 #include <linux/module.h> 40 #include <linux/stddef.h> 41 #include <linux/mutex.h> 42 #include <linux/bitops.h> 43 #include <linux/jiffies.h> 44 #include <linux/types.h> 45 #include <linux/gfp.h> 46 #include <linux/err.h> 47 #include <linux/regulator/consumer.h> 48 49 #include <linux/iio/iio.h> 50 51 #define TWL4030_MADC_MAX_CHANNELS 16 52 53 #define TWL4030_MADC_CTRL1 0x00 54 #define TWL4030_MADC_CTRL2 0x01 55 56 #define TWL4030_MADC_RTSELECT_LSB 0x02 57 #define TWL4030_MADC_SW1SELECT_LSB 0x06 58 #define TWL4030_MADC_SW2SELECT_LSB 0x0A 59 60 #define TWL4030_MADC_RTAVERAGE_LSB 0x04 61 #define TWL4030_MADC_SW1AVERAGE_LSB 0x08 62 #define TWL4030_MADC_SW2AVERAGE_LSB 0x0C 63 64 #define TWL4030_MADC_CTRL_SW1 0x12 65 #define TWL4030_MADC_CTRL_SW2 0x13 66 67 #define TWL4030_MADC_RTCH0_LSB 0x17 68 #define TWL4030_MADC_GPCH0_LSB 0x37 69 70 #define TWL4030_MADC_MADCON (1 << 0) /* MADC power on */ 71 #define TWL4030_MADC_BUSY (1 << 0) /* MADC busy */ 72 /* MADC conversion completion */ 73 #define TWL4030_MADC_EOC_SW (1 << 1) 74 /* MADC SWx start conversion */ 75 #define TWL4030_MADC_SW_START (1 << 5) 76 #define TWL4030_MADC_ADCIN0 (1 << 0) 77 #define TWL4030_MADC_ADCIN1 (1 << 1) 78 #define TWL4030_MADC_ADCIN2 (1 << 2) 79 #define TWL4030_MADC_ADCIN3 (1 << 3) 80 #define TWL4030_MADC_ADCIN4 (1 << 4) 81 #define TWL4030_MADC_ADCIN5 (1 << 5) 82 #define TWL4030_MADC_ADCIN6 (1 << 6) 83 #define TWL4030_MADC_ADCIN7 (1 << 7) 84 #define TWL4030_MADC_ADCIN8 (1 << 8) 85 #define TWL4030_MADC_ADCIN9 (1 << 9) 86 #define TWL4030_MADC_ADCIN10 (1 << 10) 87 #define TWL4030_MADC_ADCIN11 (1 << 11) 88 #define TWL4030_MADC_ADCIN12 (1 << 12) 89 #define TWL4030_MADC_ADCIN13 (1 << 13) 90 #define TWL4030_MADC_ADCIN14 (1 << 14) 91 #define TWL4030_MADC_ADCIN15 (1 << 15) 92 93 /* Fixed channels */ 94 #define TWL4030_MADC_BTEMP TWL4030_MADC_ADCIN1 95 #define TWL4030_MADC_VBUS TWL4030_MADC_ADCIN8 96 #define TWL4030_MADC_VBKB TWL4030_MADC_ADCIN9 97 #define TWL4030_MADC_ICHG TWL4030_MADC_ADCIN10 98 #define TWL4030_MADC_VCHG TWL4030_MADC_ADCIN11 99 #define TWL4030_MADC_VBAT TWL4030_MADC_ADCIN12 100 101 /* Step size and prescaler ratio */ 102 #define TEMP_STEP_SIZE 147 103 #define TEMP_PSR_R 100 104 #define CURR_STEP_SIZE 147 105 #define CURR_PSR_R1 44 106 #define CURR_PSR_R2 88 107 108 #define TWL4030_BCI_BCICTL1 0x23 109 #define TWL4030_BCI_CGAIN 0x020 110 #define TWL4030_BCI_MESBAT (1 << 1) 111 #define TWL4030_BCI_TYPEN (1 << 4) 112 #define TWL4030_BCI_ITHEN (1 << 3) 113 114 #define REG_BCICTL2 0x024 115 #define TWL4030_BCI_ITHSENS 0x007 116 117 /* Register and bits for GPBR1 register */ 118 #define TWL4030_REG_GPBR1 0x0c 119 #define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7) 120 121 #define TWL4030_USB_SEL_MADC_MCPC (1<<3) 122 #define TWL4030_USB_CARKIT_ANA_CTRL 0xBB 123 124 struct twl4030_madc_conversion_method { 125 u8 sel; 126 u8 avg; 127 u8 rbase; 128 u8 ctrl; 129 }; 130 131 /** 132 * struct twl4030_madc_request - madc request packet for channel conversion 133 * @channels: 16 bit bitmap for individual channels 134 * @do_avg: sample the input channel for 4 consecutive cycles 135 * @method: RT, SW1, SW2 136 * @type: Polling or interrupt based method 137 * @active: Flag if request is active 138 * @result_pending: Flag from irq handler, that result is ready 139 * @raw: Return raw value, do not convert it 140 * @rbuf: Result buffer 141 */ 142 struct twl4030_madc_request { 143 unsigned long channels; 144 bool do_avg; 145 u16 method; 146 u16 type; 147 bool active; 148 bool result_pending; 149 bool raw; 150 int rbuf[TWL4030_MADC_MAX_CHANNELS]; 151 }; 152 153 enum conversion_methods { 154 TWL4030_MADC_RT, 155 TWL4030_MADC_SW1, 156 TWL4030_MADC_SW2, 157 TWL4030_MADC_NUM_METHODS 158 }; 159 160 enum sample_type { 161 TWL4030_MADC_WAIT, 162 TWL4030_MADC_IRQ_ONESHOT, 163 TWL4030_MADC_IRQ_REARM 164 }; 165 166 /** 167 * struct twl4030_madc_data - a container for madc info 168 * @dev: Pointer to device structure for madc 169 * @lock: Mutex protecting this data structure 170 * @regulator: Pointer to bias regulator for madc 171 * @requests: Array of request struct corresponding to SW1, SW2 and RT 172 * @use_second_irq: IRQ selection (main or co-processor) 173 * @imr: Interrupt mask register of MADC 174 * @isr: Interrupt status register of MADC 175 */ 176 struct twl4030_madc_data { 177 struct device *dev; 178 struct mutex lock; /* mutex protecting this data structure */ 179 struct regulator *usb3v1; 180 struct twl4030_madc_request requests[TWL4030_MADC_NUM_METHODS]; 181 bool use_second_irq; 182 u8 imr; 183 u8 isr; 184 }; 185 186 static int twl4030_madc_conversion(struct twl4030_madc_request *req); 187 188 static int twl4030_madc_read(struct iio_dev *iio_dev, 189 const struct iio_chan_spec *chan, 190 int *val, int *val2, long mask) 191 { 192 struct twl4030_madc_data *madc = iio_priv(iio_dev); 193 struct twl4030_madc_request req; 194 int ret; 195 196 req.method = madc->use_second_irq ? TWL4030_MADC_SW2 : TWL4030_MADC_SW1; 197 198 req.channels = BIT(chan->channel); 199 req.active = false; 200 req.type = TWL4030_MADC_WAIT; 201 req.raw = !(mask == IIO_CHAN_INFO_PROCESSED); 202 req.do_avg = (mask == IIO_CHAN_INFO_AVERAGE_RAW); 203 204 ret = twl4030_madc_conversion(&req); 205 if (ret < 0) 206 return ret; 207 208 *val = req.rbuf[chan->channel]; 209 210 return IIO_VAL_INT; 211 } 212 213 static const struct iio_info twl4030_madc_iio_info = { 214 .read_raw = &twl4030_madc_read, 215 }; 216 217 #define TWL4030_ADC_CHANNEL(_channel, _type, _name) { \ 218 .type = _type, \ 219 .channel = _channel, \ 220 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 221 BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \ 222 BIT(IIO_CHAN_INFO_PROCESSED), \ 223 .datasheet_name = _name, \ 224 .indexed = 1, \ 225 } 226 227 static const struct iio_chan_spec twl4030_madc_iio_channels[] = { 228 TWL4030_ADC_CHANNEL(0, IIO_VOLTAGE, "ADCIN0"), 229 TWL4030_ADC_CHANNEL(1, IIO_TEMP, "ADCIN1"), 230 TWL4030_ADC_CHANNEL(2, IIO_VOLTAGE, "ADCIN2"), 231 TWL4030_ADC_CHANNEL(3, IIO_VOLTAGE, "ADCIN3"), 232 TWL4030_ADC_CHANNEL(4, IIO_VOLTAGE, "ADCIN4"), 233 TWL4030_ADC_CHANNEL(5, IIO_VOLTAGE, "ADCIN5"), 234 TWL4030_ADC_CHANNEL(6, IIO_VOLTAGE, "ADCIN6"), 235 TWL4030_ADC_CHANNEL(7, IIO_VOLTAGE, "ADCIN7"), 236 TWL4030_ADC_CHANNEL(8, IIO_VOLTAGE, "ADCIN8"), 237 TWL4030_ADC_CHANNEL(9, IIO_VOLTAGE, "ADCIN9"), 238 TWL4030_ADC_CHANNEL(10, IIO_CURRENT, "ADCIN10"), 239 TWL4030_ADC_CHANNEL(11, IIO_VOLTAGE, "ADCIN11"), 240 TWL4030_ADC_CHANNEL(12, IIO_VOLTAGE, "ADCIN12"), 241 TWL4030_ADC_CHANNEL(13, IIO_VOLTAGE, "ADCIN13"), 242 TWL4030_ADC_CHANNEL(14, IIO_VOLTAGE, "ADCIN14"), 243 TWL4030_ADC_CHANNEL(15, IIO_VOLTAGE, "ADCIN15"), 244 }; 245 246 static struct twl4030_madc_data *twl4030_madc; 247 248 struct twl4030_prescale_divider_ratios { 249 s16 numerator; 250 s16 denominator; 251 }; 252 253 static const struct twl4030_prescale_divider_ratios 254 twl4030_divider_ratios[16] = { 255 {1, 1}, /* CHANNEL 0 No Prescaler */ 256 {1, 1}, /* CHANNEL 1 No Prescaler */ 257 {6, 10}, /* CHANNEL 2 */ 258 {6, 10}, /* CHANNEL 3 */ 259 {6, 10}, /* CHANNEL 4 */ 260 {6, 10}, /* CHANNEL 5 */ 261 {6, 10}, /* CHANNEL 6 */ 262 {6, 10}, /* CHANNEL 7 */ 263 {3, 14}, /* CHANNEL 8 */ 264 {1, 3}, /* CHANNEL 9 */ 265 {1, 1}, /* CHANNEL 10 No Prescaler */ 266 {15, 100}, /* CHANNEL 11 */ 267 {1, 4}, /* CHANNEL 12 */ 268 {1, 1}, /* CHANNEL 13 Reserved channels */ 269 {1, 1}, /* CHANNEL 14 Reseved channels */ 270 {5, 11}, /* CHANNEL 15 */ 271 }; 272 273 274 /* Conversion table from -3 to 55 degrees Celcius */ 275 static int twl4030_therm_tbl[] = { 276 30800, 29500, 28300, 27100, 277 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 278 17900, 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 279 12600, 12100, 11600, 11200, 10800, 10400, 10000, 9630, 9280, 280 8950, 8620, 8310, 8020, 7730, 7460, 7200, 6950, 6710, 281 6470, 6250, 6040, 5830, 5640, 5450, 5260, 5090, 4920, 282 4760, 4600, 4450, 4310, 4170, 4040, 3910, 3790, 3670, 283 3550 284 }; 285 286 /* 287 * Structure containing the registers 288 * of different conversion methods supported by MADC. 289 * Hardware or RT real time conversion request initiated by external host 290 * processor for RT Signal conversions. 291 * External host processors can also request for non RT conversions 292 * SW1 and SW2 software conversions also called asynchronous or GPC request. 293 */ 294 static 295 const struct twl4030_madc_conversion_method twl4030_conversion_methods[] = { 296 [TWL4030_MADC_RT] = { 297 .sel = TWL4030_MADC_RTSELECT_LSB, 298 .avg = TWL4030_MADC_RTAVERAGE_LSB, 299 .rbase = TWL4030_MADC_RTCH0_LSB, 300 }, 301 [TWL4030_MADC_SW1] = { 302 .sel = TWL4030_MADC_SW1SELECT_LSB, 303 .avg = TWL4030_MADC_SW1AVERAGE_LSB, 304 .rbase = TWL4030_MADC_GPCH0_LSB, 305 .ctrl = TWL4030_MADC_CTRL_SW1, 306 }, 307 [TWL4030_MADC_SW2] = { 308 .sel = TWL4030_MADC_SW2SELECT_LSB, 309 .avg = TWL4030_MADC_SW2AVERAGE_LSB, 310 .rbase = TWL4030_MADC_GPCH0_LSB, 311 .ctrl = TWL4030_MADC_CTRL_SW2, 312 }, 313 }; 314 315 /** 316 * twl4030_madc_channel_raw_read() - Function to read a particular channel value 317 * @madc: pointer to struct twl4030_madc_data 318 * @reg: lsb of ADC Channel 319 * 320 * Return: 0 on success, an error code otherwise. 321 */ 322 static int twl4030_madc_channel_raw_read(struct twl4030_madc_data *madc, u8 reg) 323 { 324 u16 val; 325 int ret; 326 /* 327 * For each ADC channel, we have MSB and LSB register pair. MSB address 328 * is always LSB address+1. reg parameter is the address of LSB register 329 */ 330 ret = twl_i2c_read_u16(TWL4030_MODULE_MADC, &val, reg); 331 if (ret) { 332 dev_err(madc->dev, "unable to read register 0x%X\n", reg); 333 return ret; 334 } 335 336 return (int)(val >> 6); 337 } 338 339 /* 340 * Return battery temperature in degrees Celsius 341 * Or < 0 on failure. 342 */ 343 static int twl4030battery_temperature(int raw_volt) 344 { 345 u8 val; 346 int temp, curr, volt, res, ret; 347 348 volt = (raw_volt * TEMP_STEP_SIZE) / TEMP_PSR_R; 349 /* Getting and calculating the supply current in micro amperes */ 350 ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, 351 REG_BCICTL2); 352 if (ret < 0) 353 return ret; 354 355 curr = ((val & TWL4030_BCI_ITHSENS) + 1) * 10; 356 /* Getting and calculating the thermistor resistance in ohms */ 357 res = volt * 1000 / curr; 358 /* calculating temperature */ 359 for (temp = 58; temp >= 0; temp--) { 360 int actual = twl4030_therm_tbl[temp]; 361 if ((actual - res) >= 0) 362 break; 363 } 364 365 return temp + 1; 366 } 367 368 static int twl4030battery_current(int raw_volt) 369 { 370 int ret; 371 u8 val; 372 373 ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, 374 TWL4030_BCI_BCICTL1); 375 if (ret) 376 return ret; 377 if (val & TWL4030_BCI_CGAIN) /* slope of 0.44 mV/mA */ 378 return (raw_volt * CURR_STEP_SIZE) / CURR_PSR_R1; 379 else /* slope of 0.88 mV/mA */ 380 return (raw_volt * CURR_STEP_SIZE) / CURR_PSR_R2; 381 } 382 383 /* 384 * Function to read channel values 385 * @madc - pointer to twl4030_madc_data struct 386 * @reg_base - Base address of the first channel 387 * @Channels - 16 bit bitmap. If the bit is set, channel's value is read 388 * @buf - The channel values are stored here. if read fails error 389 * @raw - Return raw values without conversion 390 * value is stored 391 * Returns the number of successfully read channels. 392 */ 393 static int twl4030_madc_read_channels(struct twl4030_madc_data *madc, 394 u8 reg_base, unsigned 395 long channels, int *buf, 396 bool raw) 397 { 398 int count = 0; 399 int i; 400 u8 reg; 401 402 for_each_set_bit(i, &channels, TWL4030_MADC_MAX_CHANNELS) { 403 reg = reg_base + (2 * i); 404 buf[i] = twl4030_madc_channel_raw_read(madc, reg); 405 if (buf[i] < 0) { 406 dev_err(madc->dev, "Unable to read register 0x%X\n", 407 reg); 408 return buf[i]; 409 } 410 if (raw) { 411 count++; 412 continue; 413 } 414 switch (i) { 415 case 10: 416 buf[i] = twl4030battery_current(buf[i]); 417 if (buf[i] < 0) { 418 dev_err(madc->dev, "err reading current\n"); 419 return buf[i]; 420 } else { 421 count++; 422 buf[i] = buf[i] - 750; 423 } 424 break; 425 case 1: 426 buf[i] = twl4030battery_temperature(buf[i]); 427 if (buf[i] < 0) { 428 dev_err(madc->dev, "err reading temperature\n"); 429 return buf[i]; 430 } else { 431 buf[i] -= 3; 432 count++; 433 } 434 break; 435 default: 436 count++; 437 /* Analog Input (V) = conv_result * step_size / R 438 * conv_result = decimal value of 10-bit conversion 439 * result 440 * step size = 1.5 / (2 ^ 10 -1) 441 * R = Prescaler ratio for input channels. 442 * Result given in mV hence multiplied by 1000. 443 */ 444 buf[i] = (buf[i] * 3 * 1000 * 445 twl4030_divider_ratios[i].denominator) 446 / (2 * 1023 * 447 twl4030_divider_ratios[i].numerator); 448 } 449 } 450 451 return count; 452 } 453 454 /* 455 * Disables irq. 456 * @madc - pointer to twl4030_madc_data struct 457 * @id - irq number to be disabled 458 * can take one of TWL4030_MADC_RT, TWL4030_MADC_SW1, TWL4030_MADC_SW2 459 * corresponding to RT, SW1, SW2 conversion requests. 460 * Returns error if i2c read/write fails. 461 */ 462 static int twl4030_madc_disable_irq(struct twl4030_madc_data *madc, u8 id) 463 { 464 u8 val; 465 int ret; 466 467 ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, madc->imr); 468 if (ret) { 469 dev_err(madc->dev, "unable to read imr register 0x%X\n", 470 madc->imr); 471 return ret; 472 } 473 val |= (1 << id); 474 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, madc->imr); 475 if (ret) { 476 dev_err(madc->dev, 477 "unable to write imr register 0x%X\n", madc->imr); 478 return ret; 479 } 480 481 return 0; 482 } 483 484 static irqreturn_t twl4030_madc_threaded_irq_handler(int irq, void *_madc) 485 { 486 struct twl4030_madc_data *madc = _madc; 487 const struct twl4030_madc_conversion_method *method; 488 u8 isr_val, imr_val; 489 int i, len, ret; 490 struct twl4030_madc_request *r; 491 492 mutex_lock(&madc->lock); 493 ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &isr_val, madc->isr); 494 if (ret) { 495 dev_err(madc->dev, "unable to read isr register 0x%X\n", 496 madc->isr); 497 goto err_i2c; 498 } 499 ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &imr_val, madc->imr); 500 if (ret) { 501 dev_err(madc->dev, "unable to read imr register 0x%X\n", 502 madc->imr); 503 goto err_i2c; 504 } 505 isr_val &= ~imr_val; 506 for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { 507 if (!(isr_val & (1 << i))) 508 continue; 509 ret = twl4030_madc_disable_irq(madc, i); 510 if (ret < 0) 511 dev_dbg(madc->dev, "Disable interrupt failed %d\n", i); 512 madc->requests[i].result_pending = 1; 513 } 514 for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { 515 r = &madc->requests[i]; 516 /* No pending results for this method, move to next one */ 517 if (!r->result_pending) 518 continue; 519 method = &twl4030_conversion_methods[r->method]; 520 /* Read results */ 521 len = twl4030_madc_read_channels(madc, method->rbase, 522 r->channels, r->rbuf, r->raw); 523 /* Free request */ 524 r->result_pending = 0; 525 r->active = 0; 526 } 527 mutex_unlock(&madc->lock); 528 529 return IRQ_HANDLED; 530 531 err_i2c: 532 /* 533 * In case of error check whichever request is active 534 * and service the same. 535 */ 536 for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { 537 r = &madc->requests[i]; 538 if (r->active == 0) 539 continue; 540 method = &twl4030_conversion_methods[r->method]; 541 /* Read results */ 542 len = twl4030_madc_read_channels(madc, method->rbase, 543 r->channels, r->rbuf, r->raw); 544 /* Free request */ 545 r->result_pending = 0; 546 r->active = 0; 547 } 548 mutex_unlock(&madc->lock); 549 550 return IRQ_HANDLED; 551 } 552 553 /* 554 * Function which enables the madc conversion 555 * by writing to the control register. 556 * @madc - pointer to twl4030_madc_data struct 557 * @conv_method - can be TWL4030_MADC_RT, TWL4030_MADC_SW2, TWL4030_MADC_SW1 558 * corresponding to RT SW1 or SW2 conversion methods. 559 * Returns 0 if succeeds else a negative error value 560 */ 561 static int twl4030_madc_start_conversion(struct twl4030_madc_data *madc, 562 int conv_method) 563 { 564 const struct twl4030_madc_conversion_method *method; 565 int ret = 0; 566 567 if (conv_method != TWL4030_MADC_SW1 && conv_method != TWL4030_MADC_SW2) 568 return -ENOTSUPP; 569 570 method = &twl4030_conversion_methods[conv_method]; 571 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, TWL4030_MADC_SW_START, 572 method->ctrl); 573 if (ret) { 574 dev_err(madc->dev, "unable to write ctrl register 0x%X\n", 575 method->ctrl); 576 return ret; 577 } 578 579 return 0; 580 } 581 582 /* 583 * Function that waits for conversion to be ready 584 * @madc - pointer to twl4030_madc_data struct 585 * @timeout_ms - timeout value in milliseconds 586 * @status_reg - ctrl register 587 * returns 0 if succeeds else a negative error value 588 */ 589 static int twl4030_madc_wait_conversion_ready(struct twl4030_madc_data *madc, 590 unsigned int timeout_ms, 591 u8 status_reg) 592 { 593 unsigned long timeout; 594 int ret; 595 596 timeout = jiffies + msecs_to_jiffies(timeout_ms); 597 do { 598 u8 reg; 599 600 ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, ®, status_reg); 601 if (ret) { 602 dev_err(madc->dev, 603 "unable to read status register 0x%X\n", 604 status_reg); 605 return ret; 606 } 607 if (!(reg & TWL4030_MADC_BUSY) && (reg & TWL4030_MADC_EOC_SW)) 608 return 0; 609 usleep_range(500, 2000); 610 } while (!time_after(jiffies, timeout)); 611 dev_err(madc->dev, "conversion timeout!\n"); 612 613 return -EAGAIN; 614 } 615 616 /* 617 * An exported function which can be called from other kernel drivers. 618 * @req twl4030_madc_request structure 619 * req->rbuf will be filled with read values of channels based on the 620 * channel index. If a particular channel reading fails there will 621 * be a negative error value in the corresponding array element. 622 * returns 0 if succeeds else error value 623 */ 624 static int twl4030_madc_conversion(struct twl4030_madc_request *req) 625 { 626 const struct twl4030_madc_conversion_method *method; 627 int ret; 628 629 if (!req || !twl4030_madc) 630 return -EINVAL; 631 632 mutex_lock(&twl4030_madc->lock); 633 if (req->method < TWL4030_MADC_RT || req->method > TWL4030_MADC_SW2) { 634 ret = -EINVAL; 635 goto out; 636 } 637 /* Do we have a conversion request ongoing */ 638 if (twl4030_madc->requests[req->method].active) { 639 ret = -EBUSY; 640 goto out; 641 } 642 method = &twl4030_conversion_methods[req->method]; 643 /* Select channels to be converted */ 644 ret = twl_i2c_write_u16(TWL4030_MODULE_MADC, req->channels, method->sel); 645 if (ret) { 646 dev_err(twl4030_madc->dev, 647 "unable to write sel register 0x%X\n", method->sel); 648 goto out; 649 } 650 /* Select averaging for all channels if do_avg is set */ 651 if (req->do_avg) { 652 ret = twl_i2c_write_u16(TWL4030_MODULE_MADC, req->channels, 653 method->avg); 654 if (ret) { 655 dev_err(twl4030_madc->dev, 656 "unable to write avg register 0x%X\n", 657 method->avg); 658 goto out; 659 } 660 } 661 /* With RT method we should not be here anymore */ 662 if (req->method == TWL4030_MADC_RT) { 663 ret = -EINVAL; 664 goto out; 665 } 666 ret = twl4030_madc_start_conversion(twl4030_madc, req->method); 667 if (ret < 0) 668 goto out; 669 twl4030_madc->requests[req->method].active = 1; 670 /* Wait until conversion is ready (ctrl register returns EOC) */ 671 ret = twl4030_madc_wait_conversion_ready(twl4030_madc, 5, method->ctrl); 672 if (ret) { 673 twl4030_madc->requests[req->method].active = 0; 674 goto out; 675 } 676 ret = twl4030_madc_read_channels(twl4030_madc, method->rbase, 677 req->channels, req->rbuf, req->raw); 678 twl4030_madc->requests[req->method].active = 0; 679 680 out: 681 mutex_unlock(&twl4030_madc->lock); 682 683 return ret; 684 } 685 686 /** 687 * twl4030_madc_set_current_generator() - setup bias current 688 * 689 * @madc: pointer to twl4030_madc_data struct 690 * @chan: can be one of the two values: 691 * 0 - Enables bias current for main battery type reading 692 * 1 - Enables bias current for main battery temperature sensing 693 * @on: enable or disable chan. 694 * 695 * Function to enable or disable bias current for 696 * main battery type reading or temperature sensing 697 */ 698 static int twl4030_madc_set_current_generator(struct twl4030_madc_data *madc, 699 int chan, int on) 700 { 701 int ret; 702 int regmask; 703 u8 regval; 704 705 ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, 706 ®val, TWL4030_BCI_BCICTL1); 707 if (ret) { 708 dev_err(madc->dev, "unable to read BCICTL1 reg 0x%X", 709 TWL4030_BCI_BCICTL1); 710 return ret; 711 } 712 713 regmask = chan ? TWL4030_BCI_ITHEN : TWL4030_BCI_TYPEN; 714 if (on) 715 regval |= regmask; 716 else 717 regval &= ~regmask; 718 719 ret = twl_i2c_write_u8(TWL_MODULE_MAIN_CHARGE, 720 regval, TWL4030_BCI_BCICTL1); 721 if (ret) { 722 dev_err(madc->dev, "unable to write BCICTL1 reg 0x%X\n", 723 TWL4030_BCI_BCICTL1); 724 return ret; 725 } 726 727 return 0; 728 } 729 730 /* 731 * Function that sets MADC software power on bit to enable MADC 732 * @madc - pointer to twl4030_madc_data struct 733 * @on - Enable or disable MADC software power on bit. 734 * returns error if i2c read/write fails else 0 735 */ 736 static int twl4030_madc_set_power(struct twl4030_madc_data *madc, int on) 737 { 738 u8 regval; 739 int ret; 740 741 ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, 742 ®val, TWL4030_MADC_CTRL1); 743 if (ret) { 744 dev_err(madc->dev, "unable to read madc ctrl1 reg 0x%X\n", 745 TWL4030_MADC_CTRL1); 746 return ret; 747 } 748 if (on) 749 regval |= TWL4030_MADC_MADCON; 750 else 751 regval &= ~TWL4030_MADC_MADCON; 752 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); 753 if (ret) { 754 dev_err(madc->dev, "unable to write madc ctrl1 reg 0x%X\n", 755 TWL4030_MADC_CTRL1); 756 return ret; 757 } 758 759 return 0; 760 } 761 762 /* 763 * Initialize MADC and request for threaded irq 764 */ 765 static int twl4030_madc_probe(struct platform_device *pdev) 766 { 767 struct twl4030_madc_data *madc; 768 struct twl4030_madc_platform_data *pdata = dev_get_platdata(&pdev->dev); 769 struct device_node *np = pdev->dev.of_node; 770 int irq, ret; 771 u8 regval; 772 struct iio_dev *iio_dev = NULL; 773 774 if (!pdata && !np) { 775 dev_err(&pdev->dev, "neither platform data nor Device Tree node available\n"); 776 return -EINVAL; 777 } 778 779 iio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*madc)); 780 if (!iio_dev) { 781 dev_err(&pdev->dev, "failed allocating iio device\n"); 782 return -ENOMEM; 783 } 784 785 madc = iio_priv(iio_dev); 786 madc->dev = &pdev->dev; 787 788 iio_dev->name = dev_name(&pdev->dev); 789 iio_dev->dev.parent = &pdev->dev; 790 iio_dev->dev.of_node = pdev->dev.of_node; 791 iio_dev->info = &twl4030_madc_iio_info; 792 iio_dev->modes = INDIO_DIRECT_MODE; 793 iio_dev->channels = twl4030_madc_iio_channels; 794 iio_dev->num_channels = ARRAY_SIZE(twl4030_madc_iio_channels); 795 796 /* 797 * Phoenix provides 2 interrupt lines. The first one is connected to 798 * the OMAP. The other one can be connected to the other processor such 799 * as modem. Hence two separate ISR and IMR registers. 800 */ 801 if (pdata) 802 madc->use_second_irq = (pdata->irq_line != 1); 803 else 804 madc->use_second_irq = of_property_read_bool(np, 805 "ti,system-uses-second-madc-irq"); 806 807 madc->imr = madc->use_second_irq ? TWL4030_MADC_IMR2 : 808 TWL4030_MADC_IMR1; 809 madc->isr = madc->use_second_irq ? TWL4030_MADC_ISR2 : 810 TWL4030_MADC_ISR1; 811 812 ret = twl4030_madc_set_power(madc, 1); 813 if (ret < 0) 814 return ret; 815 ret = twl4030_madc_set_current_generator(madc, 0, 1); 816 if (ret < 0) 817 goto err_current_generator; 818 819 ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, 820 ®val, TWL4030_BCI_BCICTL1); 821 if (ret) { 822 dev_err(&pdev->dev, "unable to read reg BCI CTL1 0x%X\n", 823 TWL4030_BCI_BCICTL1); 824 goto err_i2c; 825 } 826 regval |= TWL4030_BCI_MESBAT; 827 ret = twl_i2c_write_u8(TWL_MODULE_MAIN_CHARGE, 828 regval, TWL4030_BCI_BCICTL1); 829 if (ret) { 830 dev_err(&pdev->dev, "unable to write reg BCI Ctl1 0x%X\n", 831 TWL4030_BCI_BCICTL1); 832 goto err_i2c; 833 } 834 835 /* Check that MADC clock is on */ 836 ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, ®val, TWL4030_REG_GPBR1); 837 if (ret) { 838 dev_err(&pdev->dev, "unable to read reg GPBR1 0x%X\n", 839 TWL4030_REG_GPBR1); 840 goto err_i2c; 841 } 842 843 /* If MADC clk is not on, turn it on */ 844 if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) { 845 dev_info(&pdev->dev, "clk disabled, enabling\n"); 846 regval |= TWL4030_GPBR1_MADC_HFCLK_EN; 847 ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval, 848 TWL4030_REG_GPBR1); 849 if (ret) { 850 dev_err(&pdev->dev, "unable to write reg GPBR1 0x%X\n", 851 TWL4030_REG_GPBR1); 852 goto err_i2c; 853 } 854 } 855 856 platform_set_drvdata(pdev, iio_dev); 857 mutex_init(&madc->lock); 858 859 irq = platform_get_irq(pdev, 0); 860 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 861 twl4030_madc_threaded_irq_handler, 862 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 863 "twl4030_madc", madc); 864 if (ret) { 865 dev_err(&pdev->dev, "could not request irq\n"); 866 goto err_i2c; 867 } 868 twl4030_madc = madc; 869 870 /* Configure MADC[3:6] */ 871 ret = twl_i2c_read_u8(TWL_MODULE_USB, ®val, 872 TWL4030_USB_CARKIT_ANA_CTRL); 873 if (ret) { 874 dev_err(&pdev->dev, "unable to read reg CARKIT_ANA_CTRL 0x%X\n", 875 TWL4030_USB_CARKIT_ANA_CTRL); 876 goto err_i2c; 877 } 878 regval |= TWL4030_USB_SEL_MADC_MCPC; 879 ret = twl_i2c_write_u8(TWL_MODULE_USB, regval, 880 TWL4030_USB_CARKIT_ANA_CTRL); 881 if (ret) { 882 dev_err(&pdev->dev, "unable to write reg CARKIT_ANA_CTRL 0x%X\n", 883 TWL4030_USB_CARKIT_ANA_CTRL); 884 goto err_i2c; 885 } 886 887 /* Enable 3v1 bias regulator for MADC[3:6] */ 888 madc->usb3v1 = devm_regulator_get(madc->dev, "vusb3v1"); 889 if (IS_ERR(madc->usb3v1)) { 890 ret = -ENODEV; 891 goto err_i2c; 892 } 893 894 ret = regulator_enable(madc->usb3v1); 895 if (ret) { 896 dev_err(madc->dev, "could not enable 3v1 bias regulator\n"); 897 goto err_i2c; 898 } 899 900 ret = iio_device_register(iio_dev); 901 if (ret) { 902 dev_err(&pdev->dev, "could not register iio device\n"); 903 goto err_usb3v1; 904 } 905 906 return 0; 907 908 err_usb3v1: 909 regulator_disable(madc->usb3v1); 910 err_i2c: 911 twl4030_madc_set_current_generator(madc, 0, 0); 912 err_current_generator: 913 twl4030_madc_set_power(madc, 0); 914 return ret; 915 } 916 917 static int twl4030_madc_remove(struct platform_device *pdev) 918 { 919 struct iio_dev *iio_dev = platform_get_drvdata(pdev); 920 struct twl4030_madc_data *madc = iio_priv(iio_dev); 921 922 iio_device_unregister(iio_dev); 923 924 twl4030_madc_set_current_generator(madc, 0, 0); 925 twl4030_madc_set_power(madc, 0); 926 927 regulator_disable(madc->usb3v1); 928 929 return 0; 930 } 931 932 #ifdef CONFIG_OF 933 static const struct of_device_id twl_madc_of_match[] = { 934 { .compatible = "ti,twl4030-madc", }, 935 { }, 936 }; 937 MODULE_DEVICE_TABLE(of, twl_madc_of_match); 938 #endif 939 940 static struct platform_driver twl4030_madc_driver = { 941 .probe = twl4030_madc_probe, 942 .remove = twl4030_madc_remove, 943 .driver = { 944 .name = "twl4030_madc", 945 .of_match_table = of_match_ptr(twl_madc_of_match), 946 }, 947 }; 948 949 module_platform_driver(twl4030_madc_driver); 950 951 MODULE_DESCRIPTION("TWL4030 ADC driver"); 952 MODULE_LICENSE("GPL"); 953 MODULE_AUTHOR("J Keerthy"); 954 MODULE_ALIAS("platform:twl4030_madc"); 955