1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI ADC MFD driver 4 * 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/interrupt.h> 13 #include <linux/platform_device.h> 14 #include <linux/io.h> 15 #include <linux/iio/iio.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/iio/machine.h> 19 #include <linux/iio/driver.h> 20 #include <linux/iopoll.h> 21 22 #include <linux/mfd/ti_am335x_tscadc.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/kfifo_buf.h> 25 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 29 #define DMA_BUFFER_SIZE SZ_2K 30 31 struct tiadc_dma { 32 struct dma_slave_config conf; 33 struct dma_chan *chan; 34 dma_addr_t addr; 35 dma_cookie_t cookie; 36 u8 *buf; 37 int current_period; 38 int period_size; 39 u8 fifo_thresh; 40 }; 41 42 struct tiadc_device { 43 struct ti_tscadc_dev *mfd_tscadc; 44 struct tiadc_dma dma; 45 struct mutex fifo1_lock; /* to protect fifo access */ 46 int channels; 47 int total_ch_enabled; 48 u8 channel_line[8]; 49 u8 channel_step[8]; 50 int buffer_en_ch_steps; 51 u16 data[8]; 52 u32 open_delay[8], sample_delay[8], step_avg[8]; 53 }; 54 55 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) 56 { 57 return readl(adc->mfd_tscadc->tscadc_base + reg); 58 } 59 60 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, 61 unsigned int val) 62 { 63 writel(val, adc->mfd_tscadc->tscadc_base + reg); 64 } 65 66 static u32 get_adc_step_mask(struct tiadc_device *adc_dev) 67 { 68 u32 step_en; 69 70 step_en = ((1 << adc_dev->channels) - 1); 71 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; 72 return step_en; 73 } 74 75 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, 76 struct iio_chan_spec const *chan) 77 { 78 int i; 79 80 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { 81 if (chan->channel == adc_dev->channel_line[i]) { 82 u32 step; 83 84 step = adc_dev->channel_step[i]; 85 /* +1 for the charger */ 86 return 1 << (step + 1); 87 } 88 } 89 WARN_ON(1); 90 return 0; 91 } 92 93 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) 94 { 95 return 1 << adc_dev->channel_step[chan]; 96 } 97 98 static int tiadc_wait_idle(struct tiadc_device *adc_dev) 99 { 100 u32 val; 101 102 return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM, 103 val, !(val & SEQ_STATUS), 10, 104 IDLE_TIMEOUT * 1000 * adc_dev->channels); 105 } 106 107 static void tiadc_step_config(struct iio_dev *indio_dev) 108 { 109 struct tiadc_device *adc_dev = iio_priv(indio_dev); 110 struct device *dev = adc_dev->mfd_tscadc->dev; 111 unsigned int stepconfig; 112 int i, steps = 0; 113 114 /* 115 * There are 16 configurable steps and 8 analog input 116 * lines available which are shared between Touchscreen and ADC. 117 * 118 * Steps forwards i.e. from 0 towards 16 are used by ADC 119 * depending on number of input lines needed. 120 * Channel would represent which analog input 121 * needs to be given to ADC to digitalize data. 122 */ 123 124 125 for (i = 0; i < adc_dev->channels; i++) { 126 int chan; 127 128 chan = adc_dev->channel_line[i]; 129 130 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { 131 dev_warn(dev, "chan %d: wrong step avg, truncated to %ld\n", 132 chan, STEPCONFIG_AVG_16); 133 adc_dev->step_avg[i] = STEPCONFIG_AVG_16; 134 } 135 136 if (adc_dev->step_avg[i]) 137 stepconfig = 138 STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | 139 STEPCONFIG_FIFO1; 140 else 141 stepconfig = STEPCONFIG_FIFO1; 142 143 if (iio_buffer_enabled(indio_dev)) 144 stepconfig |= STEPCONFIG_MODE_SWCNT; 145 146 tiadc_writel(adc_dev, REG_STEPCONFIG(steps), 147 stepconfig | STEPCONFIG_INP(chan) | 148 STEPCONFIG_INM_ADCREFM | 149 STEPCONFIG_RFP_VREFP | 150 STEPCONFIG_RFM_VREFN); 151 152 if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) { 153 dev_warn(dev, "chan %d: wrong open delay, truncated to 0x%lX\n", 154 chan, STEPCONFIG_MAX_OPENDLY); 155 adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY; 156 } 157 158 if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) { 159 dev_warn(dev, "chan %d: wrong sample delay, truncated to 0x%lX\n", 160 chan, STEPCONFIG_MAX_SAMPLE); 161 adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE; 162 } 163 164 tiadc_writel(adc_dev, REG_STEPDELAY(steps), 165 STEPDELAY_OPEN(adc_dev->open_delay[i]) | 166 STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); 167 168 adc_dev->channel_step[i] = steps; 169 steps++; 170 } 171 } 172 173 static irqreturn_t tiadc_irq_h(int irq, void *private) 174 { 175 struct iio_dev *indio_dev = private; 176 struct tiadc_device *adc_dev = iio_priv(indio_dev); 177 unsigned int status, config, adc_fsm; 178 unsigned short count = 0; 179 180 status = tiadc_readl(adc_dev, REG_IRQSTATUS); 181 182 /* 183 * ADC and touchscreen share the IRQ line. 184 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only 185 */ 186 if (status & IRQENB_FIFO1OVRRUN) { 187 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ 188 config = tiadc_readl(adc_dev, REG_CTRL); 189 config &= ~(CNTRLREG_SSENB); 190 tiadc_writel(adc_dev, REG_CTRL, config); 191 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN 192 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); 193 194 /* wait for idle state. 195 * ADC needs to finish the current conversion 196 * before disabling the module 197 */ 198 do { 199 adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); 200 } while (adc_fsm != 0x10 && count++ < 100); 201 202 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB)); 203 return IRQ_HANDLED; 204 } else if (status & IRQENB_FIFO1THRES) { 205 /* Disable irq and wake worker thread */ 206 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); 207 return IRQ_WAKE_THREAD; 208 } 209 210 return IRQ_NONE; 211 } 212 213 static irqreturn_t tiadc_worker_h(int irq, void *private) 214 { 215 struct iio_dev *indio_dev = private; 216 struct tiadc_device *adc_dev = iio_priv(indio_dev); 217 int i, k, fifo1count, read; 218 u16 *data = adc_dev->data; 219 220 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 221 for (k = 0; k < fifo1count; k = k + i) { 222 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { 223 read = tiadc_readl(adc_dev, REG_FIFO1); 224 data[i] = read & FIFOREAD_DATA_MASK; 225 } 226 iio_push_to_buffers(indio_dev, (u8 *) data); 227 } 228 229 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); 230 tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); 231 232 return IRQ_HANDLED; 233 } 234 235 static void tiadc_dma_rx_complete(void *param) 236 { 237 struct iio_dev *indio_dev = param; 238 struct tiadc_device *adc_dev = iio_priv(indio_dev); 239 struct tiadc_dma *dma = &adc_dev->dma; 240 u8 *data; 241 int i; 242 243 data = dma->buf + dma->current_period * dma->period_size; 244 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ 245 246 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { 247 iio_push_to_buffers(indio_dev, data); 248 data += indio_dev->scan_bytes; 249 } 250 } 251 252 static int tiadc_start_dma(struct iio_dev *indio_dev) 253 { 254 struct tiadc_device *adc_dev = iio_priv(indio_dev); 255 struct tiadc_dma *dma = &adc_dev->dma; 256 struct dma_async_tx_descriptor *desc; 257 258 dma->current_period = 0; /* We start to fill period 0 */ 259 /* 260 * Make the fifo thresh as the multiple of total number of 261 * channels enabled, so make sure that cyclic DMA period 262 * length is also a multiple of total number of channels 263 * enabled. This ensures that no invalid data is reported 264 * to the stack via iio_push_to_buffers(). 265 */ 266 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, 267 adc_dev->total_ch_enabled) - 1; 268 /* Make sure that period length is multiple of fifo thresh level */ 269 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, 270 (dma->fifo_thresh + 1) * sizeof(u16)); 271 272 dma->conf.src_maxburst = dma->fifo_thresh + 1; 273 dmaengine_slave_config(dma->chan, &dma->conf); 274 275 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, 276 dma->period_size * 2, 277 dma->period_size, DMA_DEV_TO_MEM, 278 DMA_PREP_INTERRUPT); 279 if (!desc) 280 return -EBUSY; 281 282 desc->callback = tiadc_dma_rx_complete; 283 desc->callback_param = indio_dev; 284 285 dma->cookie = dmaengine_submit(desc); 286 287 dma_async_issue_pending(dma->chan); 288 289 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); 290 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); 291 tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); 292 293 return 0; 294 } 295 296 static int tiadc_buffer_preenable(struct iio_dev *indio_dev) 297 { 298 struct tiadc_device *adc_dev = iio_priv(indio_dev); 299 int i, fifo1count; 300 int ret; 301 302 ret = tiadc_wait_idle(adc_dev); 303 if (ret) 304 return ret; 305 306 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 307 IRQENB_FIFO1OVRRUN | 308 IRQENB_FIFO1UNDRFLW)); 309 310 /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ 311 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 312 for (i = 0; i < fifo1count; i++) 313 tiadc_readl(adc_dev, REG_FIFO1); 314 315 return 0; 316 } 317 318 static int tiadc_buffer_postenable(struct iio_dev *indio_dev) 319 { 320 struct tiadc_device *adc_dev = iio_priv(indio_dev); 321 struct tiadc_dma *dma = &adc_dev->dma; 322 unsigned int irq_enable; 323 unsigned int enb = 0; 324 u8 bit; 325 326 tiadc_step_config(indio_dev); 327 for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { 328 enb |= (get_adc_step_bit(adc_dev, bit) << 1); 329 adc_dev->total_ch_enabled++; 330 } 331 adc_dev->buffer_en_ch_steps = enb; 332 333 if (dma->chan) 334 tiadc_start_dma(indio_dev); 335 336 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); 337 338 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES 339 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); 340 341 irq_enable = IRQENB_FIFO1OVRRUN; 342 if (!dma->chan) 343 irq_enable |= IRQENB_FIFO1THRES; 344 tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); 345 346 return 0; 347 } 348 349 static int tiadc_buffer_predisable(struct iio_dev *indio_dev) 350 { 351 struct tiadc_device *adc_dev = iio_priv(indio_dev); 352 struct tiadc_dma *dma = &adc_dev->dma; 353 int fifo1count, i; 354 355 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 356 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); 357 am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); 358 adc_dev->buffer_en_ch_steps = 0; 359 adc_dev->total_ch_enabled = 0; 360 if (dma->chan) { 361 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); 362 dmaengine_terminate_async(dma->chan); 363 } 364 365 /* Flush FIFO of leftover data in the time it takes to disable adc */ 366 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 367 for (i = 0; i < fifo1count; i++) 368 tiadc_readl(adc_dev, REG_FIFO1); 369 370 return 0; 371 } 372 373 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) 374 { 375 tiadc_step_config(indio_dev); 376 377 return 0; 378 } 379 380 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { 381 .preenable = &tiadc_buffer_preenable, 382 .postenable = &tiadc_buffer_postenable, 383 .predisable = &tiadc_buffer_predisable, 384 .postdisable = &tiadc_buffer_postdisable, 385 }; 386 387 static int tiadc_iio_buffered_hardware_setup(struct device *dev, 388 struct iio_dev *indio_dev, 389 irqreturn_t (*pollfunc_bh)(int irq, void *p), 390 irqreturn_t (*pollfunc_th)(int irq, void *p), 391 int irq, 392 unsigned long flags, 393 const struct iio_buffer_setup_ops *setup_ops) 394 { 395 int ret; 396 397 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 398 INDIO_BUFFER_SOFTWARE, 399 setup_ops); 400 if (ret) 401 return ret; 402 403 return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh, 404 flags, indio_dev->name, indio_dev); 405 } 406 407 static const char * const chan_name_ain[] = { 408 "AIN0", 409 "AIN1", 410 "AIN2", 411 "AIN3", 412 "AIN4", 413 "AIN5", 414 "AIN6", 415 "AIN7", 416 }; 417 418 static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, 419 int channels) 420 { 421 struct tiadc_device *adc_dev = iio_priv(indio_dev); 422 struct iio_chan_spec *chan_array; 423 struct iio_chan_spec *chan; 424 int i; 425 426 indio_dev->num_channels = channels; 427 chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array), 428 GFP_KERNEL); 429 if (chan_array == NULL) 430 return -ENOMEM; 431 432 chan = chan_array; 433 for (i = 0; i < channels; i++, chan++) { 434 435 chan->type = IIO_VOLTAGE; 436 chan->indexed = 1; 437 chan->channel = adc_dev->channel_line[i]; 438 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 439 chan->datasheet_name = chan_name_ain[chan->channel]; 440 chan->scan_index = i; 441 chan->scan_type.sign = 'u'; 442 chan->scan_type.realbits = 12; 443 chan->scan_type.storagebits = 16; 444 } 445 446 indio_dev->channels = chan_array; 447 448 return 0; 449 } 450 451 static int tiadc_read_raw(struct iio_dev *indio_dev, 452 struct iio_chan_spec const *chan, 453 int *val, int *val2, long mask) 454 { 455 struct tiadc_device *adc_dev = iio_priv(indio_dev); 456 int i, map_val; 457 unsigned int fifo1count, read, stepid; 458 bool found = false; 459 u32 step_en; 460 unsigned long timeout; 461 int ret; 462 463 if (iio_buffer_enabled(indio_dev)) 464 return -EBUSY; 465 466 step_en = get_adc_chan_step_mask(adc_dev, chan); 467 if (!step_en) 468 return -EINVAL; 469 470 mutex_lock(&adc_dev->fifo1_lock); 471 472 ret = tiadc_wait_idle(adc_dev); 473 if (ret) 474 goto err_unlock; 475 476 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 477 while (fifo1count--) 478 tiadc_readl(adc_dev, REG_FIFO1); 479 480 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); 481 482 timeout = jiffies + msecs_to_jiffies 483 (IDLE_TIMEOUT * adc_dev->channels); 484 /* Wait for Fifo threshold interrupt */ 485 while (1) { 486 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 487 if (fifo1count) 488 break; 489 490 if (time_after(jiffies, timeout)) { 491 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 492 ret = -EAGAIN; 493 goto err_unlock; 494 } 495 } 496 map_val = adc_dev->channel_step[chan->scan_index]; 497 498 /* 499 * We check the complete FIFO. We programmed just one entry but in case 500 * something went wrong we left empty handed (-EAGAIN previously) and 501 * then the value apeared somehow in the FIFO we would have two entries. 502 * Therefore we read every item and keep only the latest version of the 503 * requested channel. 504 */ 505 for (i = 0; i < fifo1count; i++) { 506 read = tiadc_readl(adc_dev, REG_FIFO1); 507 stepid = read & FIFOREAD_CHNLID_MASK; 508 stepid = stepid >> 0x10; 509 510 if (stepid == map_val) { 511 read = read & FIFOREAD_DATA_MASK; 512 found = true; 513 *val = (u16) read; 514 } 515 } 516 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 517 518 if (!found) 519 ret = -EBUSY; 520 521 err_unlock: 522 mutex_unlock(&adc_dev->fifo1_lock); 523 return ret ? ret : IIO_VAL_INT; 524 } 525 526 static const struct iio_info tiadc_info = { 527 .read_raw = &tiadc_read_raw, 528 }; 529 530 static int tiadc_request_dma(struct platform_device *pdev, 531 struct tiadc_device *adc_dev) 532 { 533 struct tiadc_dma *dma = &adc_dev->dma; 534 dma_cap_mask_t mask; 535 536 /* Default slave configuration parameters */ 537 dma->conf.direction = DMA_DEV_TO_MEM; 538 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 539 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; 540 541 dma_cap_zero(mask); 542 dma_cap_set(DMA_CYCLIC, mask); 543 544 /* Get a channel for RX */ 545 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); 546 if (IS_ERR(dma->chan)) { 547 int ret = PTR_ERR(dma->chan); 548 549 dma->chan = NULL; 550 return ret; 551 } 552 553 /* RX buffer */ 554 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 555 &dma->addr, GFP_KERNEL); 556 if (!dma->buf) 557 goto err; 558 559 return 0; 560 err: 561 dma_release_channel(dma->chan); 562 return -ENOMEM; 563 } 564 565 static int tiadc_parse_dt(struct platform_device *pdev, 566 struct tiadc_device *adc_dev) 567 { 568 struct device_node *node = pdev->dev.of_node; 569 struct property *prop; 570 const __be32 *cur; 571 int channels = 0; 572 u32 val; 573 574 of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { 575 adc_dev->channel_line[channels] = val; 576 577 /* Set Default values for optional DT parameters */ 578 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; 579 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; 580 adc_dev->step_avg[channels] = 16; 581 582 channels++; 583 } 584 585 of_property_read_u32_array(node, "ti,chan-step-avg", 586 adc_dev->step_avg, channels); 587 of_property_read_u32_array(node, "ti,chan-step-opendelay", 588 adc_dev->open_delay, channels); 589 of_property_read_u32_array(node, "ti,chan-step-sampledelay", 590 adc_dev->sample_delay, channels); 591 592 adc_dev->channels = channels; 593 return 0; 594 } 595 596 static int tiadc_probe(struct platform_device *pdev) 597 { 598 struct iio_dev *indio_dev; 599 struct tiadc_device *adc_dev; 600 struct device_node *node = pdev->dev.of_node; 601 int err; 602 603 if (!node) { 604 dev_err(&pdev->dev, "Could not find valid DT data.\n"); 605 return -EINVAL; 606 } 607 608 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); 609 if (indio_dev == NULL) { 610 dev_err(&pdev->dev, "failed to allocate iio device\n"); 611 return -ENOMEM; 612 } 613 adc_dev = iio_priv(indio_dev); 614 615 adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); 616 tiadc_parse_dt(pdev, adc_dev); 617 618 indio_dev->name = dev_name(&pdev->dev); 619 indio_dev->modes = INDIO_DIRECT_MODE; 620 indio_dev->info = &tiadc_info; 621 622 tiadc_step_config(indio_dev); 623 tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); 624 mutex_init(&adc_dev->fifo1_lock); 625 626 err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels); 627 if (err < 0) 628 return err; 629 630 err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev, 631 &tiadc_worker_h, 632 &tiadc_irq_h, 633 adc_dev->mfd_tscadc->irq, 634 IRQF_SHARED, 635 &tiadc_buffer_setup_ops); 636 637 if (err) 638 goto err_free_channels; 639 640 err = iio_device_register(indio_dev); 641 if (err) 642 goto err_buffer_unregister; 643 644 platform_set_drvdata(pdev, indio_dev); 645 646 err = tiadc_request_dma(pdev, adc_dev); 647 if (err && err == -EPROBE_DEFER) 648 goto err_dma; 649 650 return 0; 651 652 err_dma: 653 iio_device_unregister(indio_dev); 654 err_buffer_unregister: 655 err_free_channels: 656 return err; 657 } 658 659 static int tiadc_remove(struct platform_device *pdev) 660 { 661 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 662 struct tiadc_device *adc_dev = iio_priv(indio_dev); 663 struct tiadc_dma *dma = &adc_dev->dma; 664 u32 step_en; 665 666 if (dma->chan) { 667 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 668 dma->buf, dma->addr); 669 dma_release_channel(dma->chan); 670 } 671 iio_device_unregister(indio_dev); 672 673 step_en = get_adc_step_mask(adc_dev); 674 am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); 675 676 return 0; 677 } 678 679 static int __maybe_unused tiadc_suspend(struct device *dev) 680 { 681 struct iio_dev *indio_dev = dev_get_drvdata(dev); 682 struct tiadc_device *adc_dev = iio_priv(indio_dev); 683 unsigned int idle; 684 685 idle = tiadc_readl(adc_dev, REG_CTRL); 686 idle &= ~(CNTRLREG_SSENB); 687 tiadc_writel(adc_dev, REG_CTRL, (idle | 688 CNTRLREG_POWERDOWN)); 689 690 return 0; 691 } 692 693 static int __maybe_unused tiadc_resume(struct device *dev) 694 { 695 struct iio_dev *indio_dev = dev_get_drvdata(dev); 696 struct tiadc_device *adc_dev = iio_priv(indio_dev); 697 unsigned int restore; 698 699 /* Make sure ADC is powered up */ 700 restore = tiadc_readl(adc_dev, REG_CTRL); 701 restore &= ~(CNTRLREG_POWERDOWN); 702 tiadc_writel(adc_dev, REG_CTRL, restore); 703 704 tiadc_step_config(indio_dev); 705 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, 706 adc_dev->buffer_en_ch_steps); 707 return 0; 708 } 709 710 static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); 711 712 static const struct of_device_id ti_adc_dt_ids[] = { 713 { .compatible = "ti,am3359-adc", }, 714 { } 715 }; 716 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); 717 718 static struct platform_driver tiadc_driver = { 719 .driver = { 720 .name = "TI-am335x-adc", 721 .pm = &tiadc_pm_ops, 722 .of_match_table = ti_adc_dt_ids, 723 }, 724 .probe = tiadc_probe, 725 .remove = tiadc_remove, 726 }; 727 module_platform_driver(tiadc_driver); 728 729 MODULE_DESCRIPTION("TI ADC controller driver"); 730 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); 731 MODULE_LICENSE("GPL"); 732