1 /* 2 * TI ADC MFD driver 3 * 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/err.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/iio/iio.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/iio/machine.h> 27 #include <linux/iio/driver.h> 28 #include <linux/iopoll.h> 29 30 #include <linux/mfd/ti_am335x_tscadc.h> 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/kfifo_buf.h> 33 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 37 #define DMA_BUFFER_SIZE SZ_2K 38 39 struct tiadc_dma { 40 struct dma_slave_config conf; 41 struct dma_chan *chan; 42 dma_addr_t addr; 43 dma_cookie_t cookie; 44 u8 *buf; 45 int current_period; 46 int period_size; 47 u8 fifo_thresh; 48 }; 49 50 struct tiadc_device { 51 struct ti_tscadc_dev *mfd_tscadc; 52 struct tiadc_dma dma; 53 struct mutex fifo1_lock; /* to protect fifo access */ 54 int channels; 55 int total_ch_enabled; 56 u8 channel_line[8]; 57 u8 channel_step[8]; 58 int buffer_en_ch_steps; 59 u16 data[8]; 60 u32 open_delay[8], sample_delay[8], step_avg[8]; 61 }; 62 63 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) 64 { 65 return readl(adc->mfd_tscadc->tscadc_base + reg); 66 } 67 68 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, 69 unsigned int val) 70 { 71 writel(val, adc->mfd_tscadc->tscadc_base + reg); 72 } 73 74 static u32 get_adc_step_mask(struct tiadc_device *adc_dev) 75 { 76 u32 step_en; 77 78 step_en = ((1 << adc_dev->channels) - 1); 79 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; 80 return step_en; 81 } 82 83 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, 84 struct iio_chan_spec const *chan) 85 { 86 int i; 87 88 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { 89 if (chan->channel == adc_dev->channel_line[i]) { 90 u32 step; 91 92 step = adc_dev->channel_step[i]; 93 /* +1 for the charger */ 94 return 1 << (step + 1); 95 } 96 } 97 WARN_ON(1); 98 return 0; 99 } 100 101 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) 102 { 103 return 1 << adc_dev->channel_step[chan]; 104 } 105 106 static int tiadc_wait_idle(struct tiadc_device *adc_dev) 107 { 108 u32 val; 109 110 return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM, 111 val, !(val & SEQ_STATUS), 10, 112 IDLE_TIMEOUT * 1000 * adc_dev->channels); 113 } 114 115 static void tiadc_step_config(struct iio_dev *indio_dev) 116 { 117 struct tiadc_device *adc_dev = iio_priv(indio_dev); 118 struct device *dev = adc_dev->mfd_tscadc->dev; 119 unsigned int stepconfig; 120 int i, steps = 0; 121 122 /* 123 * There are 16 configurable steps and 8 analog input 124 * lines available which are shared between Touchscreen and ADC. 125 * 126 * Steps forwards i.e. from 0 towards 16 are used by ADC 127 * depending on number of input lines needed. 128 * Channel would represent which analog input 129 * needs to be given to ADC to digitalize data. 130 */ 131 132 133 for (i = 0; i < adc_dev->channels; i++) { 134 int chan; 135 136 chan = adc_dev->channel_line[i]; 137 138 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { 139 dev_warn(dev, "chan %d: wrong step avg, truncated to %ld\n", 140 chan, STEPCONFIG_AVG_16); 141 adc_dev->step_avg[i] = STEPCONFIG_AVG_16; 142 } 143 144 if (adc_dev->step_avg[i]) 145 stepconfig = 146 STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | 147 STEPCONFIG_FIFO1; 148 else 149 stepconfig = STEPCONFIG_FIFO1; 150 151 if (iio_buffer_enabled(indio_dev)) 152 stepconfig |= STEPCONFIG_MODE_SWCNT; 153 154 tiadc_writel(adc_dev, REG_STEPCONFIG(steps), 155 stepconfig | STEPCONFIG_INP(chan) | 156 STEPCONFIG_INM_ADCREFM | 157 STEPCONFIG_RFP_VREFP | 158 STEPCONFIG_RFM_VREFN); 159 160 if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) { 161 dev_warn(dev, "chan %d: wrong open delay, truncated to 0x%lX\n", 162 chan, STEPCONFIG_MAX_OPENDLY); 163 adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY; 164 } 165 166 if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) { 167 dev_warn(dev, "chan %d: wrong sample delay, truncated to 0x%lX\n", 168 chan, STEPCONFIG_MAX_SAMPLE); 169 adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE; 170 } 171 172 tiadc_writel(adc_dev, REG_STEPDELAY(steps), 173 STEPDELAY_OPEN(adc_dev->open_delay[i]) | 174 STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); 175 176 adc_dev->channel_step[i] = steps; 177 steps++; 178 } 179 } 180 181 static irqreturn_t tiadc_irq_h(int irq, void *private) 182 { 183 struct iio_dev *indio_dev = private; 184 struct tiadc_device *adc_dev = iio_priv(indio_dev); 185 unsigned int status, config, adc_fsm; 186 unsigned short count = 0; 187 188 status = tiadc_readl(adc_dev, REG_IRQSTATUS); 189 190 /* 191 * ADC and touchscreen share the IRQ line. 192 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only 193 */ 194 if (status & IRQENB_FIFO1OVRRUN) { 195 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ 196 config = tiadc_readl(adc_dev, REG_CTRL); 197 config &= ~(CNTRLREG_SSENB); 198 tiadc_writel(adc_dev, REG_CTRL, config); 199 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN 200 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); 201 202 /* wait for idle state. 203 * ADC needs to finish the current conversion 204 * before disabling the module 205 */ 206 do { 207 adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); 208 } while (adc_fsm != 0x10 && count++ < 100); 209 210 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB)); 211 return IRQ_HANDLED; 212 } else if (status & IRQENB_FIFO1THRES) { 213 /* Disable irq and wake worker thread */ 214 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); 215 return IRQ_WAKE_THREAD; 216 } 217 218 return IRQ_NONE; 219 } 220 221 static irqreturn_t tiadc_worker_h(int irq, void *private) 222 { 223 struct iio_dev *indio_dev = private; 224 struct tiadc_device *adc_dev = iio_priv(indio_dev); 225 int i, k, fifo1count, read; 226 u16 *data = adc_dev->data; 227 228 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 229 for (k = 0; k < fifo1count; k = k + i) { 230 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { 231 read = tiadc_readl(adc_dev, REG_FIFO1); 232 data[i] = read & FIFOREAD_DATA_MASK; 233 } 234 iio_push_to_buffers(indio_dev, (u8 *) data); 235 } 236 237 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); 238 tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); 239 240 return IRQ_HANDLED; 241 } 242 243 static void tiadc_dma_rx_complete(void *param) 244 { 245 struct iio_dev *indio_dev = param; 246 struct tiadc_device *adc_dev = iio_priv(indio_dev); 247 struct tiadc_dma *dma = &adc_dev->dma; 248 u8 *data; 249 int i; 250 251 data = dma->buf + dma->current_period * dma->period_size; 252 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ 253 254 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { 255 iio_push_to_buffers(indio_dev, data); 256 data += indio_dev->scan_bytes; 257 } 258 } 259 260 static int tiadc_start_dma(struct iio_dev *indio_dev) 261 { 262 struct tiadc_device *adc_dev = iio_priv(indio_dev); 263 struct tiadc_dma *dma = &adc_dev->dma; 264 struct dma_async_tx_descriptor *desc; 265 266 dma->current_period = 0; /* We start to fill period 0 */ 267 /* 268 * Make the fifo thresh as the multiple of total number of 269 * channels enabled, so make sure that cyclic DMA period 270 * length is also a multiple of total number of channels 271 * enabled. This ensures that no invalid data is reported 272 * to the stack via iio_push_to_buffers(). 273 */ 274 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, 275 adc_dev->total_ch_enabled) - 1; 276 /* Make sure that period length is multiple of fifo thresh level */ 277 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, 278 (dma->fifo_thresh + 1) * sizeof(u16)); 279 280 dma->conf.src_maxburst = dma->fifo_thresh + 1; 281 dmaengine_slave_config(dma->chan, &dma->conf); 282 283 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, 284 dma->period_size * 2, 285 dma->period_size, DMA_DEV_TO_MEM, 286 DMA_PREP_INTERRUPT); 287 if (!desc) 288 return -EBUSY; 289 290 desc->callback = tiadc_dma_rx_complete; 291 desc->callback_param = indio_dev; 292 293 dma->cookie = dmaengine_submit(desc); 294 295 dma_async_issue_pending(dma->chan); 296 297 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); 298 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); 299 tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); 300 301 return 0; 302 } 303 304 static int tiadc_buffer_preenable(struct iio_dev *indio_dev) 305 { 306 struct tiadc_device *adc_dev = iio_priv(indio_dev); 307 int i, fifo1count; 308 int ret; 309 310 ret = tiadc_wait_idle(adc_dev); 311 if (ret) 312 return ret; 313 314 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 315 IRQENB_FIFO1OVRRUN | 316 IRQENB_FIFO1UNDRFLW)); 317 318 /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ 319 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 320 for (i = 0; i < fifo1count; i++) 321 tiadc_readl(adc_dev, REG_FIFO1); 322 323 return 0; 324 } 325 326 static int tiadc_buffer_postenable(struct iio_dev *indio_dev) 327 { 328 struct tiadc_device *adc_dev = iio_priv(indio_dev); 329 struct tiadc_dma *dma = &adc_dev->dma; 330 unsigned int irq_enable; 331 unsigned int enb = 0; 332 u8 bit; 333 334 tiadc_step_config(indio_dev); 335 for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { 336 enb |= (get_adc_step_bit(adc_dev, bit) << 1); 337 adc_dev->total_ch_enabled++; 338 } 339 adc_dev->buffer_en_ch_steps = enb; 340 341 if (dma->chan) 342 tiadc_start_dma(indio_dev); 343 344 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); 345 346 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES 347 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); 348 349 irq_enable = IRQENB_FIFO1OVRRUN; 350 if (!dma->chan) 351 irq_enable |= IRQENB_FIFO1THRES; 352 tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); 353 354 return 0; 355 } 356 357 static int tiadc_buffer_predisable(struct iio_dev *indio_dev) 358 { 359 struct tiadc_device *adc_dev = iio_priv(indio_dev); 360 struct tiadc_dma *dma = &adc_dev->dma; 361 int fifo1count, i; 362 363 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 364 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); 365 am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); 366 adc_dev->buffer_en_ch_steps = 0; 367 adc_dev->total_ch_enabled = 0; 368 if (dma->chan) { 369 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); 370 dmaengine_terminate_async(dma->chan); 371 } 372 373 /* Flush FIFO of leftover data in the time it takes to disable adc */ 374 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 375 for (i = 0; i < fifo1count; i++) 376 tiadc_readl(adc_dev, REG_FIFO1); 377 378 return 0; 379 } 380 381 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) 382 { 383 tiadc_step_config(indio_dev); 384 385 return 0; 386 } 387 388 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { 389 .preenable = &tiadc_buffer_preenable, 390 .postenable = &tiadc_buffer_postenable, 391 .predisable = &tiadc_buffer_predisable, 392 .postdisable = &tiadc_buffer_postdisable, 393 }; 394 395 static int tiadc_iio_buffered_hardware_setup(struct device *dev, 396 struct iio_dev *indio_dev, 397 irqreturn_t (*pollfunc_bh)(int irq, void *p), 398 irqreturn_t (*pollfunc_th)(int irq, void *p), 399 int irq, 400 unsigned long flags, 401 const struct iio_buffer_setup_ops *setup_ops) 402 { 403 int ret; 404 405 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 406 INDIO_BUFFER_SOFTWARE, 407 setup_ops); 408 if (ret) 409 return ret; 410 411 return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh, 412 flags, indio_dev->name, indio_dev); 413 } 414 415 static const char * const chan_name_ain[] = { 416 "AIN0", 417 "AIN1", 418 "AIN2", 419 "AIN3", 420 "AIN4", 421 "AIN5", 422 "AIN6", 423 "AIN7", 424 }; 425 426 static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, 427 int channels) 428 { 429 struct tiadc_device *adc_dev = iio_priv(indio_dev); 430 struct iio_chan_spec *chan_array; 431 struct iio_chan_spec *chan; 432 int i; 433 434 indio_dev->num_channels = channels; 435 chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array), 436 GFP_KERNEL); 437 if (chan_array == NULL) 438 return -ENOMEM; 439 440 chan = chan_array; 441 for (i = 0; i < channels; i++, chan++) { 442 443 chan->type = IIO_VOLTAGE; 444 chan->indexed = 1; 445 chan->channel = adc_dev->channel_line[i]; 446 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 447 chan->datasheet_name = chan_name_ain[chan->channel]; 448 chan->scan_index = i; 449 chan->scan_type.sign = 'u'; 450 chan->scan_type.realbits = 12; 451 chan->scan_type.storagebits = 16; 452 } 453 454 indio_dev->channels = chan_array; 455 456 return 0; 457 } 458 459 static int tiadc_read_raw(struct iio_dev *indio_dev, 460 struct iio_chan_spec const *chan, 461 int *val, int *val2, long mask) 462 { 463 struct tiadc_device *adc_dev = iio_priv(indio_dev); 464 int i, map_val; 465 unsigned int fifo1count, read, stepid; 466 bool found = false; 467 u32 step_en; 468 unsigned long timeout; 469 int ret; 470 471 if (iio_buffer_enabled(indio_dev)) 472 return -EBUSY; 473 474 step_en = get_adc_chan_step_mask(adc_dev, chan); 475 if (!step_en) 476 return -EINVAL; 477 478 mutex_lock(&adc_dev->fifo1_lock); 479 480 ret = tiadc_wait_idle(adc_dev); 481 if (ret) 482 goto err_unlock; 483 484 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 485 while (fifo1count--) 486 tiadc_readl(adc_dev, REG_FIFO1); 487 488 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); 489 490 timeout = jiffies + msecs_to_jiffies 491 (IDLE_TIMEOUT * adc_dev->channels); 492 /* Wait for Fifo threshold interrupt */ 493 while (1) { 494 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 495 if (fifo1count) 496 break; 497 498 if (time_after(jiffies, timeout)) { 499 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 500 ret = -EAGAIN; 501 goto err_unlock; 502 } 503 } 504 map_val = adc_dev->channel_step[chan->scan_index]; 505 506 /* 507 * We check the complete FIFO. We programmed just one entry but in case 508 * something went wrong we left empty handed (-EAGAIN previously) and 509 * then the value apeared somehow in the FIFO we would have two entries. 510 * Therefore we read every item and keep only the latest version of the 511 * requested channel. 512 */ 513 for (i = 0; i < fifo1count; i++) { 514 read = tiadc_readl(adc_dev, REG_FIFO1); 515 stepid = read & FIFOREAD_CHNLID_MASK; 516 stepid = stepid >> 0x10; 517 518 if (stepid == map_val) { 519 read = read & FIFOREAD_DATA_MASK; 520 found = true; 521 *val = (u16) read; 522 } 523 } 524 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 525 526 if (!found) 527 ret = -EBUSY; 528 529 err_unlock: 530 mutex_unlock(&adc_dev->fifo1_lock); 531 return ret ? ret : IIO_VAL_INT; 532 } 533 534 static const struct iio_info tiadc_info = { 535 .read_raw = &tiadc_read_raw, 536 }; 537 538 static int tiadc_request_dma(struct platform_device *pdev, 539 struct tiadc_device *adc_dev) 540 { 541 struct tiadc_dma *dma = &adc_dev->dma; 542 dma_cap_mask_t mask; 543 544 /* Default slave configuration parameters */ 545 dma->conf.direction = DMA_DEV_TO_MEM; 546 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 547 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; 548 549 dma_cap_zero(mask); 550 dma_cap_set(DMA_CYCLIC, mask); 551 552 /* Get a channel for RX */ 553 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); 554 if (IS_ERR(dma->chan)) { 555 int ret = PTR_ERR(dma->chan); 556 557 dma->chan = NULL; 558 return ret; 559 } 560 561 /* RX buffer */ 562 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 563 &dma->addr, GFP_KERNEL); 564 if (!dma->buf) 565 goto err; 566 567 return 0; 568 err: 569 dma_release_channel(dma->chan); 570 return -ENOMEM; 571 } 572 573 static int tiadc_parse_dt(struct platform_device *pdev, 574 struct tiadc_device *adc_dev) 575 { 576 struct device_node *node = pdev->dev.of_node; 577 struct property *prop; 578 const __be32 *cur; 579 int channels = 0; 580 u32 val; 581 582 of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { 583 adc_dev->channel_line[channels] = val; 584 585 /* Set Default values for optional DT parameters */ 586 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; 587 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; 588 adc_dev->step_avg[channels] = 16; 589 590 channels++; 591 } 592 593 of_property_read_u32_array(node, "ti,chan-step-avg", 594 adc_dev->step_avg, channels); 595 of_property_read_u32_array(node, "ti,chan-step-opendelay", 596 adc_dev->open_delay, channels); 597 of_property_read_u32_array(node, "ti,chan-step-sampledelay", 598 adc_dev->sample_delay, channels); 599 600 adc_dev->channels = channels; 601 return 0; 602 } 603 604 static int tiadc_probe(struct platform_device *pdev) 605 { 606 struct iio_dev *indio_dev; 607 struct tiadc_device *adc_dev; 608 struct device_node *node = pdev->dev.of_node; 609 int err; 610 611 if (!node) { 612 dev_err(&pdev->dev, "Could not find valid DT data.\n"); 613 return -EINVAL; 614 } 615 616 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); 617 if (indio_dev == NULL) { 618 dev_err(&pdev->dev, "failed to allocate iio device\n"); 619 return -ENOMEM; 620 } 621 adc_dev = iio_priv(indio_dev); 622 623 adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); 624 tiadc_parse_dt(pdev, adc_dev); 625 626 indio_dev->name = dev_name(&pdev->dev); 627 indio_dev->modes = INDIO_DIRECT_MODE; 628 indio_dev->info = &tiadc_info; 629 630 tiadc_step_config(indio_dev); 631 tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); 632 mutex_init(&adc_dev->fifo1_lock); 633 634 err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels); 635 if (err < 0) 636 return err; 637 638 err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev, 639 &tiadc_worker_h, 640 &tiadc_irq_h, 641 adc_dev->mfd_tscadc->irq, 642 IRQF_SHARED, 643 &tiadc_buffer_setup_ops); 644 645 if (err) 646 goto err_free_channels; 647 648 err = iio_device_register(indio_dev); 649 if (err) 650 goto err_buffer_unregister; 651 652 platform_set_drvdata(pdev, indio_dev); 653 654 err = tiadc_request_dma(pdev, adc_dev); 655 if (err && err == -EPROBE_DEFER) 656 goto err_dma; 657 658 return 0; 659 660 err_dma: 661 iio_device_unregister(indio_dev); 662 err_buffer_unregister: 663 err_free_channels: 664 return err; 665 } 666 667 static int tiadc_remove(struct platform_device *pdev) 668 { 669 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 670 struct tiadc_device *adc_dev = iio_priv(indio_dev); 671 struct tiadc_dma *dma = &adc_dev->dma; 672 u32 step_en; 673 674 if (dma->chan) { 675 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 676 dma->buf, dma->addr); 677 dma_release_channel(dma->chan); 678 } 679 iio_device_unregister(indio_dev); 680 681 step_en = get_adc_step_mask(adc_dev); 682 am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); 683 684 return 0; 685 } 686 687 static int __maybe_unused tiadc_suspend(struct device *dev) 688 { 689 struct iio_dev *indio_dev = dev_get_drvdata(dev); 690 struct tiadc_device *adc_dev = iio_priv(indio_dev); 691 unsigned int idle; 692 693 idle = tiadc_readl(adc_dev, REG_CTRL); 694 idle &= ~(CNTRLREG_SSENB); 695 tiadc_writel(adc_dev, REG_CTRL, (idle | 696 CNTRLREG_POWERDOWN)); 697 698 return 0; 699 } 700 701 static int __maybe_unused tiadc_resume(struct device *dev) 702 { 703 struct iio_dev *indio_dev = dev_get_drvdata(dev); 704 struct tiadc_device *adc_dev = iio_priv(indio_dev); 705 unsigned int restore; 706 707 /* Make sure ADC is powered up */ 708 restore = tiadc_readl(adc_dev, REG_CTRL); 709 restore &= ~(CNTRLREG_POWERDOWN); 710 tiadc_writel(adc_dev, REG_CTRL, restore); 711 712 tiadc_step_config(indio_dev); 713 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, 714 adc_dev->buffer_en_ch_steps); 715 return 0; 716 } 717 718 static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); 719 720 static const struct of_device_id ti_adc_dt_ids[] = { 721 { .compatible = "ti,am3359-adc", }, 722 { } 723 }; 724 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); 725 726 static struct platform_driver tiadc_driver = { 727 .driver = { 728 .name = "TI-am335x-adc", 729 .pm = &tiadc_pm_ops, 730 .of_match_table = ti_adc_dt_ids, 731 }, 732 .probe = tiadc_probe, 733 .remove = tiadc_remove, 734 }; 735 module_platform_driver(tiadc_driver); 736 737 MODULE_DESCRIPTION("TI ADC controller driver"); 738 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); 739 MODULE_LICENSE("GPL"); 740