1 /* 2 * TI ADC MFD driver 3 * 4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/err.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/iio/iio.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/iio/machine.h> 27 #include <linux/iio/driver.h> 28 29 #include <linux/mfd/ti_am335x_tscadc.h> 30 #include <linux/iio/buffer.h> 31 #include <linux/iio/kfifo_buf.h> 32 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 36 #define DMA_BUFFER_SIZE SZ_2K 37 38 struct tiadc_dma { 39 struct dma_slave_config conf; 40 struct dma_chan *chan; 41 dma_addr_t addr; 42 dma_cookie_t cookie; 43 u8 *buf; 44 int current_period; 45 int period_size; 46 u8 fifo_thresh; 47 }; 48 49 struct tiadc_device { 50 struct ti_tscadc_dev *mfd_tscadc; 51 struct tiadc_dma dma; 52 struct mutex fifo1_lock; /* to protect fifo access */ 53 int channels; 54 int total_ch_enabled; 55 u8 channel_line[8]; 56 u8 channel_step[8]; 57 int buffer_en_ch_steps; 58 u16 data[8]; 59 u32 open_delay[8], sample_delay[8], step_avg[8]; 60 }; 61 62 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) 63 { 64 return readl(adc->mfd_tscadc->tscadc_base + reg); 65 } 66 67 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, 68 unsigned int val) 69 { 70 writel(val, adc->mfd_tscadc->tscadc_base + reg); 71 } 72 73 static u32 get_adc_step_mask(struct tiadc_device *adc_dev) 74 { 75 u32 step_en; 76 77 step_en = ((1 << adc_dev->channels) - 1); 78 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; 79 return step_en; 80 } 81 82 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, 83 struct iio_chan_spec const *chan) 84 { 85 int i; 86 87 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { 88 if (chan->channel == adc_dev->channel_line[i]) { 89 u32 step; 90 91 step = adc_dev->channel_step[i]; 92 /* +1 for the charger */ 93 return 1 << (step + 1); 94 } 95 } 96 WARN_ON(1); 97 return 0; 98 } 99 100 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) 101 { 102 return 1 << adc_dev->channel_step[chan]; 103 } 104 105 static void tiadc_step_config(struct iio_dev *indio_dev) 106 { 107 struct tiadc_device *adc_dev = iio_priv(indio_dev); 108 struct device *dev = adc_dev->mfd_tscadc->dev; 109 unsigned int stepconfig; 110 int i, steps = 0; 111 112 /* 113 * There are 16 configurable steps and 8 analog input 114 * lines available which are shared between Touchscreen and ADC. 115 * 116 * Steps forwards i.e. from 0 towards 16 are used by ADC 117 * depending on number of input lines needed. 118 * Channel would represent which analog input 119 * needs to be given to ADC to digitalize data. 120 */ 121 122 123 for (i = 0; i < adc_dev->channels; i++) { 124 int chan; 125 126 chan = adc_dev->channel_line[i]; 127 128 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { 129 dev_warn(dev, "chan %d step_avg truncating to %d\n", 130 chan, STEPCONFIG_AVG_16); 131 adc_dev->step_avg[i] = STEPCONFIG_AVG_16; 132 } 133 134 if (adc_dev->step_avg[i]) 135 stepconfig = 136 STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | 137 STEPCONFIG_FIFO1; 138 else 139 stepconfig = STEPCONFIG_FIFO1; 140 141 if (iio_buffer_enabled(indio_dev)) 142 stepconfig |= STEPCONFIG_MODE_SWCNT; 143 144 tiadc_writel(adc_dev, REG_STEPCONFIG(steps), 145 stepconfig | STEPCONFIG_INP(chan)); 146 147 if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) { 148 dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n", 149 chan); 150 adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK; 151 } 152 153 if (adc_dev->sample_delay[i] > 0xFF) { 154 dev_warn(dev, "chan %d sample delay truncating to 0xFF\n", 155 chan); 156 adc_dev->sample_delay[i] = 0xFF; 157 } 158 159 tiadc_writel(adc_dev, REG_STEPDELAY(steps), 160 STEPDELAY_OPEN(adc_dev->open_delay[i]) | 161 STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); 162 163 adc_dev->channel_step[i] = steps; 164 steps++; 165 } 166 } 167 168 static irqreturn_t tiadc_irq_h(int irq, void *private) 169 { 170 struct iio_dev *indio_dev = private; 171 struct tiadc_device *adc_dev = iio_priv(indio_dev); 172 unsigned int status, config; 173 status = tiadc_readl(adc_dev, REG_IRQSTATUS); 174 175 /* 176 * ADC and touchscreen share the IRQ line. 177 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only 178 */ 179 if (status & IRQENB_FIFO1OVRRUN) { 180 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ 181 config = tiadc_readl(adc_dev, REG_CTRL); 182 config &= ~(CNTRLREG_TSCSSENB); 183 tiadc_writel(adc_dev, REG_CTRL, config); 184 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN 185 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); 186 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB)); 187 return IRQ_HANDLED; 188 } else if (status & IRQENB_FIFO1THRES) { 189 /* Disable irq and wake worker thread */ 190 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); 191 return IRQ_WAKE_THREAD; 192 } 193 194 return IRQ_NONE; 195 } 196 197 static irqreturn_t tiadc_worker_h(int irq, void *private) 198 { 199 struct iio_dev *indio_dev = private; 200 struct tiadc_device *adc_dev = iio_priv(indio_dev); 201 int i, k, fifo1count, read; 202 u16 *data = adc_dev->data; 203 204 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 205 for (k = 0; k < fifo1count; k = k + i) { 206 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { 207 read = tiadc_readl(adc_dev, REG_FIFO1); 208 data[i] = read & FIFOREAD_DATA_MASK; 209 } 210 iio_push_to_buffers(indio_dev, (u8 *) data); 211 } 212 213 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); 214 tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); 215 216 return IRQ_HANDLED; 217 } 218 219 static void tiadc_dma_rx_complete(void *param) 220 { 221 struct iio_dev *indio_dev = param; 222 struct tiadc_device *adc_dev = iio_priv(indio_dev); 223 struct tiadc_dma *dma = &adc_dev->dma; 224 u8 *data; 225 int i; 226 227 data = dma->buf + dma->current_period * dma->period_size; 228 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ 229 230 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { 231 iio_push_to_buffers(indio_dev, data); 232 data += indio_dev->scan_bytes; 233 } 234 } 235 236 static int tiadc_start_dma(struct iio_dev *indio_dev) 237 { 238 struct tiadc_device *adc_dev = iio_priv(indio_dev); 239 struct tiadc_dma *dma = &adc_dev->dma; 240 struct dma_async_tx_descriptor *desc; 241 242 dma->current_period = 0; /* We start to fill period 0 */ 243 /* 244 * Make the fifo thresh as the multiple of total number of 245 * channels enabled, so make sure that cyclic DMA period 246 * length is also a multiple of total number of channels 247 * enabled. This ensures that no invalid data is reported 248 * to the stack via iio_push_to_buffers(). 249 */ 250 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, 251 adc_dev->total_ch_enabled) - 1; 252 /* Make sure that period length is multiple of fifo thresh level */ 253 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, 254 (dma->fifo_thresh + 1) * sizeof(u16)); 255 256 dma->conf.src_maxburst = dma->fifo_thresh + 1; 257 dmaengine_slave_config(dma->chan, &dma->conf); 258 259 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, 260 dma->period_size * 2, 261 dma->period_size, DMA_DEV_TO_MEM, 262 DMA_PREP_INTERRUPT); 263 if (!desc) 264 return -EBUSY; 265 266 desc->callback = tiadc_dma_rx_complete; 267 desc->callback_param = indio_dev; 268 269 dma->cookie = dmaengine_submit(desc); 270 271 dma_async_issue_pending(dma->chan); 272 273 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); 274 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); 275 tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); 276 277 return 0; 278 } 279 280 static int tiadc_buffer_preenable(struct iio_dev *indio_dev) 281 { 282 struct tiadc_device *adc_dev = iio_priv(indio_dev); 283 int i, fifo1count, read; 284 285 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 286 IRQENB_FIFO1OVRRUN | 287 IRQENB_FIFO1UNDRFLW)); 288 289 /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ 290 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 291 for (i = 0; i < fifo1count; i++) 292 read = tiadc_readl(adc_dev, REG_FIFO1); 293 294 return 0; 295 } 296 297 static int tiadc_buffer_postenable(struct iio_dev *indio_dev) 298 { 299 struct tiadc_device *adc_dev = iio_priv(indio_dev); 300 struct tiadc_dma *dma = &adc_dev->dma; 301 unsigned int irq_enable; 302 unsigned int enb = 0; 303 u8 bit; 304 305 tiadc_step_config(indio_dev); 306 for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { 307 enb |= (get_adc_step_bit(adc_dev, bit) << 1); 308 adc_dev->total_ch_enabled++; 309 } 310 adc_dev->buffer_en_ch_steps = enb; 311 312 if (dma->chan) 313 tiadc_start_dma(indio_dev); 314 315 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); 316 317 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES 318 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); 319 320 irq_enable = IRQENB_FIFO1OVRRUN; 321 if (!dma->chan) 322 irq_enable |= IRQENB_FIFO1THRES; 323 tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); 324 325 return 0; 326 } 327 328 static int tiadc_buffer_predisable(struct iio_dev *indio_dev) 329 { 330 struct tiadc_device *adc_dev = iio_priv(indio_dev); 331 struct tiadc_dma *dma = &adc_dev->dma; 332 int fifo1count, i, read; 333 334 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 335 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); 336 am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); 337 adc_dev->buffer_en_ch_steps = 0; 338 adc_dev->total_ch_enabled = 0; 339 if (dma->chan) { 340 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); 341 dmaengine_terminate_async(dma->chan); 342 } 343 344 /* Flush FIFO of leftover data in the time it takes to disable adc */ 345 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 346 for (i = 0; i < fifo1count; i++) 347 read = tiadc_readl(adc_dev, REG_FIFO1); 348 349 return 0; 350 } 351 352 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) 353 { 354 tiadc_step_config(indio_dev); 355 356 return 0; 357 } 358 359 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { 360 .preenable = &tiadc_buffer_preenable, 361 .postenable = &tiadc_buffer_postenable, 362 .predisable = &tiadc_buffer_predisable, 363 .postdisable = &tiadc_buffer_postdisable, 364 }; 365 366 static int tiadc_iio_buffered_hardware_setup(struct iio_dev *indio_dev, 367 irqreturn_t (*pollfunc_bh)(int irq, void *p), 368 irqreturn_t (*pollfunc_th)(int irq, void *p), 369 int irq, 370 unsigned long flags, 371 const struct iio_buffer_setup_ops *setup_ops) 372 { 373 struct iio_buffer *buffer; 374 int ret; 375 376 buffer = iio_kfifo_allocate(); 377 if (!buffer) 378 return -ENOMEM; 379 380 iio_device_attach_buffer(indio_dev, buffer); 381 382 ret = request_threaded_irq(irq, pollfunc_th, pollfunc_bh, 383 flags, indio_dev->name, indio_dev); 384 if (ret) 385 goto error_kfifo_free; 386 387 indio_dev->setup_ops = setup_ops; 388 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 389 390 return 0; 391 392 error_kfifo_free: 393 iio_kfifo_free(indio_dev->buffer); 394 return ret; 395 } 396 397 static void tiadc_iio_buffered_hardware_remove(struct iio_dev *indio_dev) 398 { 399 struct tiadc_device *adc_dev = iio_priv(indio_dev); 400 401 free_irq(adc_dev->mfd_tscadc->irq, indio_dev); 402 iio_kfifo_free(indio_dev->buffer); 403 } 404 405 406 static const char * const chan_name_ain[] = { 407 "AIN0", 408 "AIN1", 409 "AIN2", 410 "AIN3", 411 "AIN4", 412 "AIN5", 413 "AIN6", 414 "AIN7", 415 }; 416 417 static int tiadc_channel_init(struct iio_dev *indio_dev, int channels) 418 { 419 struct tiadc_device *adc_dev = iio_priv(indio_dev); 420 struct iio_chan_spec *chan_array; 421 struct iio_chan_spec *chan; 422 int i; 423 424 indio_dev->num_channels = channels; 425 chan_array = kcalloc(channels, sizeof(*chan_array), GFP_KERNEL); 426 if (chan_array == NULL) 427 return -ENOMEM; 428 429 chan = chan_array; 430 for (i = 0; i < channels; i++, chan++) { 431 432 chan->type = IIO_VOLTAGE; 433 chan->indexed = 1; 434 chan->channel = adc_dev->channel_line[i]; 435 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 436 chan->datasheet_name = chan_name_ain[chan->channel]; 437 chan->scan_index = i; 438 chan->scan_type.sign = 'u'; 439 chan->scan_type.realbits = 12; 440 chan->scan_type.storagebits = 16; 441 } 442 443 indio_dev->channels = chan_array; 444 445 return 0; 446 } 447 448 static void tiadc_channels_remove(struct iio_dev *indio_dev) 449 { 450 kfree(indio_dev->channels); 451 } 452 453 static int tiadc_read_raw(struct iio_dev *indio_dev, 454 struct iio_chan_spec const *chan, 455 int *val, int *val2, long mask) 456 { 457 struct tiadc_device *adc_dev = iio_priv(indio_dev); 458 int ret = IIO_VAL_INT; 459 int i, map_val; 460 unsigned int fifo1count, read, stepid; 461 bool found = false; 462 u32 step_en; 463 unsigned long timeout; 464 465 if (iio_buffer_enabled(indio_dev)) 466 return -EBUSY; 467 468 step_en = get_adc_chan_step_mask(adc_dev, chan); 469 if (!step_en) 470 return -EINVAL; 471 472 mutex_lock(&adc_dev->fifo1_lock); 473 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 474 while (fifo1count--) 475 tiadc_readl(adc_dev, REG_FIFO1); 476 477 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); 478 479 timeout = jiffies + msecs_to_jiffies 480 (IDLE_TIMEOUT * adc_dev->channels); 481 /* Wait for Fifo threshold interrupt */ 482 while (1) { 483 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 484 if (fifo1count) 485 break; 486 487 if (time_after(jiffies, timeout)) { 488 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 489 ret = -EAGAIN; 490 goto err_unlock; 491 } 492 } 493 map_val = adc_dev->channel_step[chan->scan_index]; 494 495 /* 496 * We check the complete FIFO. We programmed just one entry but in case 497 * something went wrong we left empty handed (-EAGAIN previously) and 498 * then the value apeared somehow in the FIFO we would have two entries. 499 * Therefore we read every item and keep only the latest version of the 500 * requested channel. 501 */ 502 for (i = 0; i < fifo1count; i++) { 503 read = tiadc_readl(adc_dev, REG_FIFO1); 504 stepid = read & FIFOREAD_CHNLID_MASK; 505 stepid = stepid >> 0x10; 506 507 if (stepid == map_val) { 508 read = read & FIFOREAD_DATA_MASK; 509 found = true; 510 *val = (u16) read; 511 } 512 } 513 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 514 515 if (found == false) 516 ret = -EBUSY; 517 518 err_unlock: 519 mutex_unlock(&adc_dev->fifo1_lock); 520 return ret; 521 } 522 523 static const struct iio_info tiadc_info = { 524 .read_raw = &tiadc_read_raw, 525 .driver_module = THIS_MODULE, 526 }; 527 528 static int tiadc_request_dma(struct platform_device *pdev, 529 struct tiadc_device *adc_dev) 530 { 531 struct tiadc_dma *dma = &adc_dev->dma; 532 dma_cap_mask_t mask; 533 534 /* Default slave configuration parameters */ 535 dma->conf.direction = DMA_DEV_TO_MEM; 536 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 537 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; 538 539 dma_cap_zero(mask); 540 dma_cap_set(DMA_CYCLIC, mask); 541 542 /* Get a channel for RX */ 543 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); 544 if (IS_ERR(dma->chan)) { 545 int ret = PTR_ERR(dma->chan); 546 547 dma->chan = NULL; 548 return ret; 549 } 550 551 /* RX buffer */ 552 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 553 &dma->addr, GFP_KERNEL); 554 if (!dma->buf) 555 goto err; 556 557 return 0; 558 err: 559 dma_release_channel(dma->chan); 560 return -ENOMEM; 561 } 562 563 static int tiadc_parse_dt(struct platform_device *pdev, 564 struct tiadc_device *adc_dev) 565 { 566 struct device_node *node = pdev->dev.of_node; 567 struct property *prop; 568 const __be32 *cur; 569 int channels = 0; 570 u32 val; 571 572 of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { 573 adc_dev->channel_line[channels] = val; 574 575 /* Set Default values for optional DT parameters */ 576 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; 577 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; 578 adc_dev->step_avg[channels] = 16; 579 580 channels++; 581 } 582 583 of_property_read_u32_array(node, "ti,chan-step-avg", 584 adc_dev->step_avg, channels); 585 of_property_read_u32_array(node, "ti,chan-step-opendelay", 586 adc_dev->open_delay, channels); 587 of_property_read_u32_array(node, "ti,chan-step-sampledelay", 588 adc_dev->sample_delay, channels); 589 590 adc_dev->channels = channels; 591 return 0; 592 } 593 594 static int tiadc_probe(struct platform_device *pdev) 595 { 596 struct iio_dev *indio_dev; 597 struct tiadc_device *adc_dev; 598 struct device_node *node = pdev->dev.of_node; 599 int err; 600 601 if (!node) { 602 dev_err(&pdev->dev, "Could not find valid DT data.\n"); 603 return -EINVAL; 604 } 605 606 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*indio_dev)); 607 if (indio_dev == NULL) { 608 dev_err(&pdev->dev, "failed to allocate iio device\n"); 609 return -ENOMEM; 610 } 611 adc_dev = iio_priv(indio_dev); 612 613 adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); 614 tiadc_parse_dt(pdev, adc_dev); 615 616 indio_dev->dev.parent = &pdev->dev; 617 indio_dev->name = dev_name(&pdev->dev); 618 indio_dev->modes = INDIO_DIRECT_MODE; 619 indio_dev->info = &tiadc_info; 620 621 tiadc_step_config(indio_dev); 622 tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); 623 mutex_init(&adc_dev->fifo1_lock); 624 625 err = tiadc_channel_init(indio_dev, adc_dev->channels); 626 if (err < 0) 627 return err; 628 629 err = tiadc_iio_buffered_hardware_setup(indio_dev, 630 &tiadc_worker_h, 631 &tiadc_irq_h, 632 adc_dev->mfd_tscadc->irq, 633 IRQF_SHARED, 634 &tiadc_buffer_setup_ops); 635 636 if (err) 637 goto err_free_channels; 638 639 err = iio_device_register(indio_dev); 640 if (err) 641 goto err_buffer_unregister; 642 643 platform_set_drvdata(pdev, indio_dev); 644 645 err = tiadc_request_dma(pdev, adc_dev); 646 if (err && err == -EPROBE_DEFER) 647 goto err_dma; 648 649 return 0; 650 651 err_dma: 652 iio_device_unregister(indio_dev); 653 err_buffer_unregister: 654 tiadc_iio_buffered_hardware_remove(indio_dev); 655 err_free_channels: 656 tiadc_channels_remove(indio_dev); 657 return err; 658 } 659 660 static int tiadc_remove(struct platform_device *pdev) 661 { 662 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 663 struct tiadc_device *adc_dev = iio_priv(indio_dev); 664 struct tiadc_dma *dma = &adc_dev->dma; 665 u32 step_en; 666 667 if (dma->chan) { 668 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 669 dma->buf, dma->addr); 670 dma_release_channel(dma->chan); 671 } 672 iio_device_unregister(indio_dev); 673 tiadc_iio_buffered_hardware_remove(indio_dev); 674 tiadc_channels_remove(indio_dev); 675 676 step_en = get_adc_step_mask(adc_dev); 677 am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); 678 679 return 0; 680 } 681 682 static int __maybe_unused tiadc_suspend(struct device *dev) 683 { 684 struct iio_dev *indio_dev = dev_get_drvdata(dev); 685 struct tiadc_device *adc_dev = iio_priv(indio_dev); 686 struct ti_tscadc_dev *tscadc_dev; 687 unsigned int idle; 688 689 tscadc_dev = ti_tscadc_dev_get(to_platform_device(dev)); 690 if (!device_may_wakeup(tscadc_dev->dev)) { 691 idle = tiadc_readl(adc_dev, REG_CTRL); 692 idle &= ~(CNTRLREG_TSCSSENB); 693 tiadc_writel(adc_dev, REG_CTRL, (idle | 694 CNTRLREG_POWERDOWN)); 695 } 696 697 return 0; 698 } 699 700 static int __maybe_unused tiadc_resume(struct device *dev) 701 { 702 struct iio_dev *indio_dev = dev_get_drvdata(dev); 703 struct tiadc_device *adc_dev = iio_priv(indio_dev); 704 unsigned int restore; 705 706 /* Make sure ADC is powered up */ 707 restore = tiadc_readl(adc_dev, REG_CTRL); 708 restore &= ~(CNTRLREG_POWERDOWN); 709 tiadc_writel(adc_dev, REG_CTRL, restore); 710 711 tiadc_step_config(indio_dev); 712 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, 713 adc_dev->buffer_en_ch_steps); 714 return 0; 715 } 716 717 static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); 718 719 static const struct of_device_id ti_adc_dt_ids[] = { 720 { .compatible = "ti,am3359-adc", }, 721 { } 722 }; 723 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); 724 725 static struct platform_driver tiadc_driver = { 726 .driver = { 727 .name = "TI-am335x-adc", 728 .pm = &tiadc_pm_ops, 729 .of_match_table = ti_adc_dt_ids, 730 }, 731 .probe = tiadc_probe, 732 .remove = tiadc_remove, 733 }; 734 module_platform_driver(tiadc_driver); 735 736 MODULE_DESCRIPTION("TI ADC controller driver"); 737 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); 738 MODULE_LICENSE("GPL"); 739