1*d935edddSTomislav Denis // SPDX-License-Identifier: GPL-2.0 2*d935edddSTomislav Denis /* 3*d935edddSTomislav Denis * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs 4*d935edddSTomislav Denis * 5*d935edddSTomislav Denis * Copyright (c) 2020 AVL DiTEST GmbH 6*d935edddSTomislav Denis * Tomislav Denis <tomislav.denis@avl.com> 7*d935edddSTomislav Denis * 8*d935edddSTomislav Denis * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf 9*d935edddSTomislav Denis */ 10*d935edddSTomislav Denis 11*d935edddSTomislav Denis #include <linux/bitfield.h> 12*d935edddSTomislav Denis #include <linux/clk.h> 13*d935edddSTomislav Denis #include <linux/delay.h> 14*d935edddSTomislav Denis #include <linux/module.h> 15*d935edddSTomislav Denis 16*d935edddSTomislav Denis #include <linux/iio/buffer.h> 17*d935edddSTomislav Denis #include <linux/iio/iio.h> 18*d935edddSTomislav Denis #include <linux/iio/sysfs.h> 19*d935edddSTomislav Denis #include <linux/iio/trigger.h> 20*d935edddSTomislav Denis #include <linux/iio/trigger_consumer.h> 21*d935edddSTomislav Denis #include <linux/iio/triggered_buffer.h> 22*d935edddSTomislav Denis 23*d935edddSTomislav Denis #include <linux/regulator/consumer.h> 24*d935edddSTomislav Denis #include <linux/spi/spi.h> 25*d935edddSTomislav Denis 26*d935edddSTomislav Denis #include <asm/unaligned.h> 27*d935edddSTomislav Denis 28*d935edddSTomislav Denis /* Commands */ 29*d935edddSTomislav Denis #define ADS131E08_CMD_RESET 0x06 30*d935edddSTomislav Denis #define ADS131E08_CMD_START 0x08 31*d935edddSTomislav Denis #define ADS131E08_CMD_STOP 0x0A 32*d935edddSTomislav Denis #define ADS131E08_CMD_OFFSETCAL 0x1A 33*d935edddSTomislav Denis #define ADS131E08_CMD_SDATAC 0x11 34*d935edddSTomislav Denis #define ADS131E08_CMD_RDATA 0x12 35*d935edddSTomislav Denis #define ADS131E08_CMD_RREG(r) (BIT(5) | (r & GENMASK(4, 0))) 36*d935edddSTomislav Denis #define ADS131E08_CMD_WREG(r) (BIT(6) | (r & GENMASK(4, 0))) 37*d935edddSTomislav Denis 38*d935edddSTomislav Denis /* Registers */ 39*d935edddSTomislav Denis #define ADS131E08_ADR_CFG1R 0x01 40*d935edddSTomislav Denis #define ADS131E08_ADR_CFG3R 0x03 41*d935edddSTomislav Denis #define ADS131E08_ADR_CH0R 0x05 42*d935edddSTomislav Denis 43*d935edddSTomislav Denis /* Configuration register 1 */ 44*d935edddSTomislav Denis #define ADS131E08_CFG1R_DR_MASK GENMASK(2, 0) 45*d935edddSTomislav Denis 46*d935edddSTomislav Denis /* Configuration register 3 */ 47*d935edddSTomislav Denis #define ADS131E08_CFG3R_PDB_REFBUF_MASK BIT(7) 48*d935edddSTomislav Denis #define ADS131E08_CFG3R_VREF_4V_MASK BIT(5) 49*d935edddSTomislav Denis 50*d935edddSTomislav Denis /* Channel settings register */ 51*d935edddSTomislav Denis #define ADS131E08_CHR_GAIN_MASK GENMASK(6, 4) 52*d935edddSTomislav Denis #define ADS131E08_CHR_MUX_MASK GENMASK(2, 0) 53*d935edddSTomislav Denis #define ADS131E08_CHR_PWD_MASK BIT(7) 54*d935edddSTomislav Denis 55*d935edddSTomislav Denis /* ADC misc */ 56*d935edddSTomislav Denis #define ADS131E08_DEFAULT_DATA_RATE 1 57*d935edddSTomislav Denis #define ADS131E08_DEFAULT_PGA_GAIN 1 58*d935edddSTomislav Denis #define ADS131E08_DEFAULT_MUX 0 59*d935edddSTomislav Denis 60*d935edddSTomislav Denis #define ADS131E08_VREF_2V4_mV 2400 61*d935edddSTomislav Denis #define ADS131E08_VREF_4V_mV 4000 62*d935edddSTomislav Denis 63*d935edddSTomislav Denis #define ADS131E08_WAIT_RESET_CYCLES 18 64*d935edddSTomislav Denis #define ADS131E08_WAIT_SDECODE_CYCLES 4 65*d935edddSTomislav Denis #define ADS131E08_WAIT_OFFSETCAL_MS 153 66*d935edddSTomislav Denis #define ADS131E08_MAX_SETTLING_TIME_MS 6 67*d935edddSTomislav Denis 68*d935edddSTomislav Denis #define ADS131E08_NUM_STATUS_BYTES 3 69*d935edddSTomislav Denis #define ADS131E08_NUM_DATA_BYTES_MAX 24 70*d935edddSTomislav Denis #define ADS131E08_NUM_DATA_BYTES(dr) (((dr) >= 32) ? 2 : 3) 71*d935edddSTomislav Denis #define ADS131E08_NUM_DATA_BITS(dr) (ADS131E08_NUM_DATA_BYTES(dr) * 8) 72*d935edddSTomislav Denis #define ADS131E08_NUM_STORAGE_BYTES 4 73*d935edddSTomislav Denis 74*d935edddSTomislav Denis enum ads131e08_ids { 75*d935edddSTomislav Denis ads131e04, 76*d935edddSTomislav Denis ads131e06, 77*d935edddSTomislav Denis ads131e08, 78*d935edddSTomislav Denis }; 79*d935edddSTomislav Denis 80*d935edddSTomislav Denis struct ads131e08_info { 81*d935edddSTomislav Denis unsigned int max_channels; 82*d935edddSTomislav Denis const char *name; 83*d935edddSTomislav Denis }; 84*d935edddSTomislav Denis 85*d935edddSTomislav Denis struct ads131e08_channel_config { 86*d935edddSTomislav Denis unsigned int pga_gain; 87*d935edddSTomislav Denis unsigned int mux; 88*d935edddSTomislav Denis }; 89*d935edddSTomislav Denis 90*d935edddSTomislav Denis struct ads131e08_state { 91*d935edddSTomislav Denis const struct ads131e08_info *info; 92*d935edddSTomislav Denis struct spi_device *spi; 93*d935edddSTomislav Denis struct iio_trigger *trig; 94*d935edddSTomislav Denis struct clk *adc_clk; 95*d935edddSTomislav Denis struct regulator *vref_reg; 96*d935edddSTomislav Denis struct ads131e08_channel_config *channel_config; 97*d935edddSTomislav Denis unsigned int data_rate; 98*d935edddSTomislav Denis unsigned int vref_mv; 99*d935edddSTomislav Denis unsigned int sdecode_delay_us; 100*d935edddSTomislav Denis unsigned int reset_delay_us; 101*d935edddSTomislav Denis unsigned int readback_len; 102*d935edddSTomislav Denis struct completion completion; 103*d935edddSTomislav Denis struct { 104*d935edddSTomislav Denis u8 data[ADS131E08_NUM_DATA_BYTES_MAX]; 105*d935edddSTomislav Denis s64 ts __aligned(8); 106*d935edddSTomislav Denis } tmp_buf; 107*d935edddSTomislav Denis 108*d935edddSTomislav Denis u8 tx_buf[3] ____cacheline_aligned; 109*d935edddSTomislav Denis /* 110*d935edddSTomislav Denis * Add extra one padding byte to be able to access the last channel 111*d935edddSTomislav Denis * value using u32 pointer 112*d935edddSTomislav Denis */ 113*d935edddSTomislav Denis u8 rx_buf[ADS131E08_NUM_STATUS_BYTES + 114*d935edddSTomislav Denis ADS131E08_NUM_DATA_BYTES_MAX + 1]; 115*d935edddSTomislav Denis }; 116*d935edddSTomislav Denis 117*d935edddSTomislav Denis static const struct ads131e08_info ads131e08_info_tbl[] = { 118*d935edddSTomislav Denis [ads131e04] = { 119*d935edddSTomislav Denis .max_channels = 4, 120*d935edddSTomislav Denis .name = "ads131e04", 121*d935edddSTomislav Denis }, 122*d935edddSTomislav Denis [ads131e06] = { 123*d935edddSTomislav Denis .max_channels = 6, 124*d935edddSTomislav Denis .name = "ads131e06", 125*d935edddSTomislav Denis }, 126*d935edddSTomislav Denis [ads131e08] = { 127*d935edddSTomislav Denis .max_channels = 8, 128*d935edddSTomislav Denis .name = "ads131e08", 129*d935edddSTomislav Denis }, 130*d935edddSTomislav Denis }; 131*d935edddSTomislav Denis 132*d935edddSTomislav Denis struct ads131e08_data_rate_desc { 133*d935edddSTomislav Denis unsigned int rate; /* data rate in kSPS */ 134*d935edddSTomislav Denis u8 reg; /* reg value */ 135*d935edddSTomislav Denis }; 136*d935edddSTomislav Denis 137*d935edddSTomislav Denis static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = { 138*d935edddSTomislav Denis { .rate = 64, .reg = 0x00 }, 139*d935edddSTomislav Denis { .rate = 32, .reg = 0x01 }, 140*d935edddSTomislav Denis { .rate = 16, .reg = 0x02 }, 141*d935edddSTomislav Denis { .rate = 8, .reg = 0x03 }, 142*d935edddSTomislav Denis { .rate = 4, .reg = 0x04 }, 143*d935edddSTomislav Denis { .rate = 2, .reg = 0x05 }, 144*d935edddSTomislav Denis { .rate = 1, .reg = 0x06 }, 145*d935edddSTomislav Denis }; 146*d935edddSTomislav Denis 147*d935edddSTomislav Denis struct ads131e08_pga_gain_desc { 148*d935edddSTomislav Denis unsigned int gain; /* PGA gain value */ 149*d935edddSTomislav Denis u8 reg; /* field value */ 150*d935edddSTomislav Denis }; 151*d935edddSTomislav Denis 152*d935edddSTomislav Denis static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = { 153*d935edddSTomislav Denis { .gain = 1, .reg = 0x01 }, 154*d935edddSTomislav Denis { .gain = 2, .reg = 0x02 }, 155*d935edddSTomislav Denis { .gain = 4, .reg = 0x04 }, 156*d935edddSTomislav Denis { .gain = 8, .reg = 0x05 }, 157*d935edddSTomislav Denis { .gain = 12, .reg = 0x06 }, 158*d935edddSTomislav Denis }; 159*d935edddSTomislav Denis 160*d935edddSTomislav Denis static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 }; 161*d935edddSTomislav Denis 162*d935edddSTomislav Denis static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd) 163*d935edddSTomislav Denis { 164*d935edddSTomislav Denis int ret; 165*d935edddSTomislav Denis 166*d935edddSTomislav Denis ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0); 167*d935edddSTomislav Denis if (ret) 168*d935edddSTomislav Denis dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd); 169*d935edddSTomislav Denis 170*d935edddSTomislav Denis return ret; 171*d935edddSTomislav Denis } 172*d935edddSTomislav Denis 173*d935edddSTomislav Denis static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg) 174*d935edddSTomislav Denis { 175*d935edddSTomislav Denis int ret; 176*d935edddSTomislav Denis struct spi_transfer transfer[] = { 177*d935edddSTomislav Denis { 178*d935edddSTomislav Denis .tx_buf = &st->tx_buf, 179*d935edddSTomislav Denis .len = 2, 1804a0225c3SLinus Torvalds .delay = { 1814a0225c3SLinus Torvalds .value = st->sdecode_delay_us, 1824a0225c3SLinus Torvalds .unit = SPI_DELAY_UNIT_USECS, 1834a0225c3SLinus Torvalds }, 184*d935edddSTomislav Denis }, { 185*d935edddSTomislav Denis .rx_buf = &st->rx_buf, 186*d935edddSTomislav Denis .len = 1, 187*d935edddSTomislav Denis }, 188*d935edddSTomislav Denis }; 189*d935edddSTomislav Denis 190*d935edddSTomislav Denis st->tx_buf[0] = ADS131E08_CMD_RREG(reg); 191*d935edddSTomislav Denis st->tx_buf[1] = 0; 192*d935edddSTomislav Denis 193*d935edddSTomislav Denis ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer)); 194*d935edddSTomislav Denis if (ret) { 195*d935edddSTomislav Denis dev_err(&st->spi->dev, "Read register failed\n"); 196*d935edddSTomislav Denis return ret; 197*d935edddSTomislav Denis } 198*d935edddSTomislav Denis 199*d935edddSTomislav Denis return st->rx_buf[0]; 200*d935edddSTomislav Denis } 201*d935edddSTomislav Denis 202*d935edddSTomislav Denis static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value) 203*d935edddSTomislav Denis { 204*d935edddSTomislav Denis int ret; 205*d935edddSTomislav Denis struct spi_transfer transfer[] = { 206*d935edddSTomislav Denis { 207*d935edddSTomislav Denis .tx_buf = &st->tx_buf, 208*d935edddSTomislav Denis .len = 3, 2094a0225c3SLinus Torvalds .delay = { 2104a0225c3SLinus Torvalds .value = st->sdecode_delay_us, 2114a0225c3SLinus Torvalds .unit = SPI_DELAY_UNIT_USECS, 2124a0225c3SLinus Torvalds }, 213*d935edddSTomislav Denis } 214*d935edddSTomislav Denis }; 215*d935edddSTomislav Denis 216*d935edddSTomislav Denis st->tx_buf[0] = ADS131E08_CMD_WREG(reg); 217*d935edddSTomislav Denis st->tx_buf[1] = 0; 218*d935edddSTomislav Denis st->tx_buf[2] = value; 219*d935edddSTomislav Denis 220*d935edddSTomislav Denis ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer)); 221*d935edddSTomislav Denis if (ret) 222*d935edddSTomislav Denis dev_err(&st->spi->dev, "Write register failed\n"); 223*d935edddSTomislav Denis 224*d935edddSTomislav Denis return ret; 225*d935edddSTomislav Denis } 226*d935edddSTomislav Denis 227*d935edddSTomislav Denis static int ads131e08_read_data(struct ads131e08_state *st, int rx_len) 228*d935edddSTomislav Denis { 229*d935edddSTomislav Denis int ret; 230*d935edddSTomislav Denis struct spi_transfer transfer[] = { 231*d935edddSTomislav Denis { 232*d935edddSTomislav Denis .tx_buf = &st->tx_buf, 233*d935edddSTomislav Denis .len = 1, 234*d935edddSTomislav Denis }, { 235*d935edddSTomislav Denis .rx_buf = &st->rx_buf, 236*d935edddSTomislav Denis .len = rx_len, 237*d935edddSTomislav Denis }, 238*d935edddSTomislav Denis }; 239*d935edddSTomislav Denis 240*d935edddSTomislav Denis st->tx_buf[0] = ADS131E08_CMD_RDATA; 241*d935edddSTomislav Denis 242*d935edddSTomislav Denis ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer)); 243*d935edddSTomislav Denis if (ret) 244*d935edddSTomislav Denis dev_err(&st->spi->dev, "Read data failed\n"); 245*d935edddSTomislav Denis 246*d935edddSTomislav Denis return ret; 247*d935edddSTomislav Denis } 248*d935edddSTomislav Denis 249*d935edddSTomislav Denis static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate) 250*d935edddSTomislav Denis { 251*d935edddSTomislav Denis int i, reg, ret; 252*d935edddSTomislav Denis 253*d935edddSTomislav Denis for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) { 254*d935edddSTomislav Denis if (ads131e08_data_rate_tbl[i].rate == data_rate) 255*d935edddSTomislav Denis break; 256*d935edddSTomislav Denis } 257*d935edddSTomislav Denis 258*d935edddSTomislav Denis if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) { 259*d935edddSTomislav Denis dev_err(&st->spi->dev, "invalid data rate value\n"); 260*d935edddSTomislav Denis return -EINVAL; 261*d935edddSTomislav Denis } 262*d935edddSTomislav Denis 263*d935edddSTomislav Denis reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R); 264*d935edddSTomislav Denis if (reg < 0) 265*d935edddSTomislav Denis return reg; 266*d935edddSTomislav Denis 267*d935edddSTomislav Denis reg &= ~ADS131E08_CFG1R_DR_MASK; 268*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK, 269*d935edddSTomislav Denis ads131e08_data_rate_tbl[i].reg); 270*d935edddSTomislav Denis 271*d935edddSTomislav Denis ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg); 272*d935edddSTomislav Denis if (ret) 273*d935edddSTomislav Denis return ret; 274*d935edddSTomislav Denis 275*d935edddSTomislav Denis st->data_rate = data_rate; 276*d935edddSTomislav Denis st->readback_len = ADS131E08_NUM_STATUS_BYTES + 277*d935edddSTomislav Denis ADS131E08_NUM_DATA_BYTES(st->data_rate) * 278*d935edddSTomislav Denis st->info->max_channels; 279*d935edddSTomislav Denis 280*d935edddSTomislav Denis return 0; 281*d935edddSTomislav Denis } 282*d935edddSTomislav Denis 283*d935edddSTomislav Denis static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st, 284*d935edddSTomislav Denis unsigned int pga_gain) 285*d935edddSTomislav Denis { 286*d935edddSTomislav Denis int i; 287*d935edddSTomislav Denis 288*d935edddSTomislav Denis for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) { 289*d935edddSTomislav Denis if (ads131e08_pga_gain_tbl[i].gain == pga_gain) 290*d935edddSTomislav Denis break; 291*d935edddSTomislav Denis } 292*d935edddSTomislav Denis 293*d935edddSTomislav Denis if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) { 294*d935edddSTomislav Denis dev_err(&st->spi->dev, "invalid PGA gain value\n"); 295*d935edddSTomislav Denis return -EINVAL; 296*d935edddSTomislav Denis } 297*d935edddSTomislav Denis 298*d935edddSTomislav Denis return ads131e08_pga_gain_tbl[i].reg; 299*d935edddSTomislav Denis } 300*d935edddSTomislav Denis 301*d935edddSTomislav Denis static int ads131e08_set_pga_gain(struct ads131e08_state *st, 302*d935edddSTomislav Denis unsigned int channel, unsigned int pga_gain) 303*d935edddSTomislav Denis { 304*d935edddSTomislav Denis int field_value, reg; 305*d935edddSTomislav Denis 306*d935edddSTomislav Denis field_value = ads131e08_pga_gain_to_field_value(st, pga_gain); 307*d935edddSTomislav Denis if (field_value < 0) 308*d935edddSTomislav Denis return field_value; 309*d935edddSTomislav Denis 310*d935edddSTomislav Denis reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel); 311*d935edddSTomislav Denis if (reg < 0) 312*d935edddSTomislav Denis return reg; 313*d935edddSTomislav Denis 314*d935edddSTomislav Denis reg &= ~ADS131E08_CHR_GAIN_MASK; 315*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value); 316*d935edddSTomislav Denis 317*d935edddSTomislav Denis return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg); 318*d935edddSTomislav Denis } 319*d935edddSTomislav Denis 320*d935edddSTomislav Denis static int ads131e08_validate_channel_mux(struct ads131e08_state *st, 321*d935edddSTomislav Denis unsigned int mux) 322*d935edddSTomislav Denis { 323*d935edddSTomislav Denis int i; 324*d935edddSTomislav Denis 325*d935edddSTomislav Denis for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) { 326*d935edddSTomislav Denis if (ads131e08_valid_channel_mux_values[i] == mux) 327*d935edddSTomislav Denis break; 328*d935edddSTomislav Denis } 329*d935edddSTomislav Denis 330*d935edddSTomislav Denis if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) { 331*d935edddSTomislav Denis dev_err(&st->spi->dev, "invalid channel mux value\n"); 332*d935edddSTomislav Denis return -EINVAL; 333*d935edddSTomislav Denis } 334*d935edddSTomislav Denis 335*d935edddSTomislav Denis return 0; 336*d935edddSTomislav Denis } 337*d935edddSTomislav Denis 338*d935edddSTomislav Denis static int ads131e08_set_channel_mux(struct ads131e08_state *st, 339*d935edddSTomislav Denis unsigned int channel, unsigned int mux) 340*d935edddSTomislav Denis { 341*d935edddSTomislav Denis int reg; 342*d935edddSTomislav Denis 343*d935edddSTomislav Denis reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel); 344*d935edddSTomislav Denis if (reg < 0) 345*d935edddSTomislav Denis return reg; 346*d935edddSTomislav Denis 347*d935edddSTomislav Denis reg &= ~ADS131E08_CHR_MUX_MASK; 348*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux); 349*d935edddSTomislav Denis 350*d935edddSTomislav Denis return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg); 351*d935edddSTomislav Denis } 352*d935edddSTomislav Denis 353*d935edddSTomislav Denis static int ads131e08_power_down_channel(struct ads131e08_state *st, 354*d935edddSTomislav Denis unsigned int channel, bool value) 355*d935edddSTomislav Denis { 356*d935edddSTomislav Denis int reg; 357*d935edddSTomislav Denis 358*d935edddSTomislav Denis reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel); 359*d935edddSTomislav Denis if (reg < 0) 360*d935edddSTomislav Denis return reg; 361*d935edddSTomislav Denis 362*d935edddSTomislav Denis reg &= ~ADS131E08_CHR_PWD_MASK; 363*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value); 364*d935edddSTomislav Denis 365*d935edddSTomislav Denis return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg); 366*d935edddSTomislav Denis } 367*d935edddSTomislav Denis 368*d935edddSTomislav Denis static int ads131e08_config_reference_voltage(struct ads131e08_state *st) 369*d935edddSTomislav Denis { 370*d935edddSTomislav Denis int reg; 371*d935edddSTomislav Denis 372*d935edddSTomislav Denis reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R); 373*d935edddSTomislav Denis if (reg < 0) 374*d935edddSTomislav Denis return reg; 375*d935edddSTomislav Denis 376*d935edddSTomislav Denis reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK; 377*d935edddSTomislav Denis if (!st->vref_reg) { 378*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1); 379*d935edddSTomislav Denis reg &= ~ADS131E08_CFG3R_VREF_4V_MASK; 380*d935edddSTomislav Denis reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK, 381*d935edddSTomislav Denis st->vref_mv == ADS131E08_VREF_4V_mV); 382*d935edddSTomislav Denis } 383*d935edddSTomislav Denis 384*d935edddSTomislav Denis return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg); 385*d935edddSTomislav Denis } 386*d935edddSTomislav Denis 387*d935edddSTomislav Denis static int ads131e08_initial_config(struct iio_dev *indio_dev) 388*d935edddSTomislav Denis { 389*d935edddSTomislav Denis const struct iio_chan_spec *channel = indio_dev->channels; 390*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 391*d935edddSTomislav Denis unsigned long active_channels = 0; 392*d935edddSTomislav Denis int ret, i; 393*d935edddSTomislav Denis 394*d935edddSTomislav Denis ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET); 395*d935edddSTomislav Denis if (ret) 396*d935edddSTomislav Denis return ret; 397*d935edddSTomislav Denis 398*d935edddSTomislav Denis udelay(st->reset_delay_us); 399*d935edddSTomislav Denis 400*d935edddSTomislav Denis /* Disable read data in continuous mode (enabled by default) */ 401*d935edddSTomislav Denis ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC); 402*d935edddSTomislav Denis if (ret) 403*d935edddSTomislav Denis return ret; 404*d935edddSTomislav Denis 405*d935edddSTomislav Denis ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE); 406*d935edddSTomislav Denis if (ret) 407*d935edddSTomislav Denis return ret; 408*d935edddSTomislav Denis 409*d935edddSTomislav Denis ret = ads131e08_config_reference_voltage(st); 410*d935edddSTomislav Denis if (ret) 411*d935edddSTomislav Denis return ret; 412*d935edddSTomislav Denis 413*d935edddSTomislav Denis for (i = 0; i < indio_dev->num_channels; i++) { 414*d935edddSTomislav Denis ret = ads131e08_set_pga_gain(st, channel->channel, 415*d935edddSTomislav Denis st->channel_config[i].pga_gain); 416*d935edddSTomislav Denis if (ret) 417*d935edddSTomislav Denis return ret; 418*d935edddSTomislav Denis 419*d935edddSTomislav Denis ret = ads131e08_set_channel_mux(st, channel->channel, 420*d935edddSTomislav Denis st->channel_config[i].mux); 421*d935edddSTomislav Denis if (ret) 422*d935edddSTomislav Denis return ret; 423*d935edddSTomislav Denis 424*d935edddSTomislav Denis active_channels |= BIT(channel->channel); 425*d935edddSTomislav Denis channel++; 426*d935edddSTomislav Denis } 427*d935edddSTomislav Denis 428*d935edddSTomislav Denis /* Power down unused channels */ 429*d935edddSTomislav Denis for_each_clear_bit(i, &active_channels, st->info->max_channels) { 430*d935edddSTomislav Denis ret = ads131e08_power_down_channel(st, i, true); 431*d935edddSTomislav Denis if (ret) 432*d935edddSTomislav Denis return ret; 433*d935edddSTomislav Denis } 434*d935edddSTomislav Denis 435*d935edddSTomislav Denis /* Request channel offset calibration */ 436*d935edddSTomislav Denis ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL); 437*d935edddSTomislav Denis if (ret) 438*d935edddSTomislav Denis return ret; 439*d935edddSTomislav Denis 440*d935edddSTomislav Denis /* 441*d935edddSTomislav Denis * Channel offset calibration is triggered with the first START 442*d935edddSTomislav Denis * command. Since calibration takes more time than settling operation, 443*d935edddSTomislav Denis * this causes timeout error when command START is sent first 444*d935edddSTomislav Denis * time (e.g. first call of the ads131e08_read_direct method). 445*d935edddSTomislav Denis * To avoid this problem offset calibration is triggered here. 446*d935edddSTomislav Denis */ 447*d935edddSTomislav Denis ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START); 448*d935edddSTomislav Denis if (ret) 449*d935edddSTomislav Denis return ret; 450*d935edddSTomislav Denis 451*d935edddSTomislav Denis msleep(ADS131E08_WAIT_OFFSETCAL_MS); 452*d935edddSTomislav Denis 453*d935edddSTomislav Denis return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP); 454*d935edddSTomislav Denis } 455*d935edddSTomislav Denis 456*d935edddSTomislav Denis static int ads131e08_pool_data(struct ads131e08_state *st) 457*d935edddSTomislav Denis { 458*d935edddSTomislav Denis unsigned long timeout; 459*d935edddSTomislav Denis int ret; 460*d935edddSTomislav Denis 461*d935edddSTomislav Denis reinit_completion(&st->completion); 462*d935edddSTomislav Denis 463*d935edddSTomislav Denis ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START); 464*d935edddSTomislav Denis if (ret) 465*d935edddSTomislav Denis return ret; 466*d935edddSTomislav Denis 467*d935edddSTomislav Denis timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS); 468*d935edddSTomislav Denis ret = wait_for_completion_timeout(&st->completion, timeout); 469*d935edddSTomislav Denis if (!ret) 470*d935edddSTomislav Denis return -ETIMEDOUT; 471*d935edddSTomislav Denis 472*d935edddSTomislav Denis ret = ads131e08_read_data(st, st->readback_len); 473*d935edddSTomislav Denis if (ret) 474*d935edddSTomislav Denis return ret; 475*d935edddSTomislav Denis 476*d935edddSTomislav Denis return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP); 477*d935edddSTomislav Denis } 478*d935edddSTomislav Denis 479*d935edddSTomislav Denis static int ads131e08_read_direct(struct iio_dev *indio_dev, 480*d935edddSTomislav Denis struct iio_chan_spec const *channel, int *value) 481*d935edddSTomislav Denis { 482*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 483*d935edddSTomislav Denis u8 num_bits, *src; 484*d935edddSTomislav Denis int ret; 485*d935edddSTomislav Denis 486*d935edddSTomislav Denis ret = ads131e08_pool_data(st); 487*d935edddSTomislav Denis if (ret) 488*d935edddSTomislav Denis return ret; 489*d935edddSTomislav Denis 490*d935edddSTomislav Denis src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + 491*d935edddSTomislav Denis channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate); 492*d935edddSTomislav Denis 493*d935edddSTomislav Denis num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate); 494*d935edddSTomislav Denis *value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1); 495*d935edddSTomislav Denis 496*d935edddSTomislav Denis return 0; 497*d935edddSTomislav Denis } 498*d935edddSTomislav Denis 499*d935edddSTomislav Denis static int ads131e08_read_raw(struct iio_dev *indio_dev, 500*d935edddSTomislav Denis struct iio_chan_spec const *channel, int *value, 501*d935edddSTomislav Denis int *value2, long mask) 502*d935edddSTomislav Denis { 503*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 504*d935edddSTomislav Denis int ret; 505*d935edddSTomislav Denis 506*d935edddSTomislav Denis switch (mask) { 507*d935edddSTomislav Denis case IIO_CHAN_INFO_RAW: 508*d935edddSTomislav Denis ret = iio_device_claim_direct_mode(indio_dev); 509*d935edddSTomislav Denis if (ret) 510*d935edddSTomislav Denis return ret; 511*d935edddSTomislav Denis 512*d935edddSTomislav Denis ret = ads131e08_read_direct(indio_dev, channel, value); 513*d935edddSTomislav Denis iio_device_release_direct_mode(indio_dev); 514*d935edddSTomislav Denis if (ret) 515*d935edddSTomislav Denis return ret; 516*d935edddSTomislav Denis 517*d935edddSTomislav Denis return IIO_VAL_INT; 518*d935edddSTomislav Denis 519*d935edddSTomislav Denis case IIO_CHAN_INFO_SCALE: 520*d935edddSTomislav Denis if (st->vref_reg) { 521*d935edddSTomislav Denis ret = regulator_get_voltage(st->vref_reg); 522*d935edddSTomislav Denis if (ret < 0) 523*d935edddSTomislav Denis return ret; 524*d935edddSTomislav Denis 525*d935edddSTomislav Denis *value = ret / 1000; 526*d935edddSTomislav Denis } else { 527*d935edddSTomislav Denis *value = st->vref_mv; 528*d935edddSTomislav Denis } 529*d935edddSTomislav Denis 530*d935edddSTomislav Denis *value /= st->channel_config[channel->address].pga_gain; 531*d935edddSTomislav Denis *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1; 532*d935edddSTomislav Denis 533*d935edddSTomislav Denis return IIO_VAL_FRACTIONAL_LOG2; 534*d935edddSTomislav Denis 535*d935edddSTomislav Denis case IIO_CHAN_INFO_SAMP_FREQ: 536*d935edddSTomislav Denis *value = st->data_rate; 537*d935edddSTomislav Denis 538*d935edddSTomislav Denis return IIO_VAL_INT; 539*d935edddSTomislav Denis 540*d935edddSTomislav Denis default: 541*d935edddSTomislav Denis return -EINVAL; 542*d935edddSTomislav Denis } 543*d935edddSTomislav Denis } 544*d935edddSTomislav Denis 545*d935edddSTomislav Denis static int ads131e08_write_raw(struct iio_dev *indio_dev, 546*d935edddSTomislav Denis struct iio_chan_spec const *channel, int value, 547*d935edddSTomislav Denis int value2, long mask) 548*d935edddSTomislav Denis { 549*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 550*d935edddSTomislav Denis int ret; 551*d935edddSTomislav Denis 552*d935edddSTomislav Denis switch (mask) { 553*d935edddSTomislav Denis case IIO_CHAN_INFO_SAMP_FREQ: 554*d935edddSTomislav Denis ret = iio_device_claim_direct_mode(indio_dev); 555*d935edddSTomislav Denis if (ret) 556*d935edddSTomislav Denis return ret; 557*d935edddSTomislav Denis 558*d935edddSTomislav Denis ret = ads131e08_set_data_rate(st, value); 559*d935edddSTomislav Denis iio_device_release_direct_mode(indio_dev); 560*d935edddSTomislav Denis return ret; 561*d935edddSTomislav Denis 562*d935edddSTomislav Denis default: 563*d935edddSTomislav Denis return -EINVAL; 564*d935edddSTomislav Denis } 565*d935edddSTomislav Denis } 566*d935edddSTomislav Denis 567*d935edddSTomislav Denis static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64"); 568*d935edddSTomislav Denis 569*d935edddSTomislav Denis static struct attribute *ads131e08_attributes[] = { 570*d935edddSTomislav Denis &iio_const_attr_sampling_frequency_available.dev_attr.attr, 571*d935edddSTomislav Denis NULL 572*d935edddSTomislav Denis }; 573*d935edddSTomislav Denis 574*d935edddSTomislav Denis static const struct attribute_group ads131e08_attribute_group = { 575*d935edddSTomislav Denis .attrs = ads131e08_attributes, 576*d935edddSTomislav Denis }; 577*d935edddSTomislav Denis 578*d935edddSTomislav Denis static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev, 579*d935edddSTomislav Denis unsigned int reg, unsigned int writeval, unsigned int *readval) 580*d935edddSTomislav Denis { 581*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 582*d935edddSTomislav Denis 583*d935edddSTomislav Denis if (readval) { 584*d935edddSTomislav Denis int ret = ads131e08_read_reg(st, reg); 585*d935edddSTomislav Denis *readval = ret; 586*d935edddSTomislav Denis return ret; 587*d935edddSTomislav Denis } 588*d935edddSTomislav Denis 589*d935edddSTomislav Denis return ads131e08_write_reg(st, reg, writeval); 590*d935edddSTomislav Denis } 591*d935edddSTomislav Denis 592*d935edddSTomislav Denis static const struct iio_info ads131e08_iio_info = { 593*d935edddSTomislav Denis .read_raw = ads131e08_read_raw, 594*d935edddSTomislav Denis .write_raw = ads131e08_write_raw, 595*d935edddSTomislav Denis .attrs = &ads131e08_attribute_group, 596*d935edddSTomislav Denis .debugfs_reg_access = &ads131e08_debugfs_reg_access, 597*d935edddSTomislav Denis }; 598*d935edddSTomislav Denis 599*d935edddSTomislav Denis static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state) 600*d935edddSTomislav Denis { 601*d935edddSTomislav Denis struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 602*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 603*d935edddSTomislav Denis u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP; 604*d935edddSTomislav Denis 605*d935edddSTomislav Denis return ads131e08_exec_cmd(st, cmd); 606*d935edddSTomislav Denis } 607*d935edddSTomislav Denis 608*d935edddSTomislav Denis static const struct iio_trigger_ops ads131e08_trigger_ops = { 609*d935edddSTomislav Denis .set_trigger_state = &ads131e08_set_trigger_state, 610*d935edddSTomislav Denis .validate_device = &iio_trigger_validate_own_device, 611*d935edddSTomislav Denis }; 612*d935edddSTomislav Denis 613*d935edddSTomislav Denis static irqreturn_t ads131e08_trigger_handler(int irq, void *private) 614*d935edddSTomislav Denis { 615*d935edddSTomislav Denis struct iio_poll_func *pf = private; 616*d935edddSTomislav Denis struct iio_dev *indio_dev = pf->indio_dev; 617*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 618*d935edddSTomislav Denis unsigned int chn, i = 0; 619*d935edddSTomislav Denis u8 *src, *dest; 620*d935edddSTomislav Denis int ret; 621*d935edddSTomislav Denis 622*d935edddSTomislav Denis /* 623*d935edddSTomislav Denis * The number of data bits per channel depends on the data rate. 624*d935edddSTomislav Denis * For 32 and 64 ksps data rates, number of data bits per channel 625*d935edddSTomislav Denis * is 16. This case is not compliant with used (fixed) scan element 626*d935edddSTomislav Denis * type (be:s24/32>>8). So we use a little tweak to pack properly 627*d935edddSTomislav Denis * 16 bits of data into the buffer. 628*d935edddSTomislav Denis */ 629*d935edddSTomislav Denis unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate); 630*d935edddSTomislav Denis u8 tweek_offset = num_bytes == 2 ? 1 : 0; 631*d935edddSTomislav Denis 632*d935edddSTomislav Denis if (iio_trigger_using_own(indio_dev)) 633*d935edddSTomislav Denis ret = ads131e08_read_data(st, st->readback_len); 634*d935edddSTomislav Denis else 635*d935edddSTomislav Denis ret = ads131e08_pool_data(st); 636*d935edddSTomislav Denis 637*d935edddSTomislav Denis if (ret) 638*d935edddSTomislav Denis goto out; 639*d935edddSTomislav Denis 640*d935edddSTomislav Denis for_each_set_bit(chn, indio_dev->active_scan_mask, indio_dev->masklength) { 641*d935edddSTomislav Denis src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes; 642*d935edddSTomislav Denis dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES; 643*d935edddSTomislav Denis 644*d935edddSTomislav Denis /* 645*d935edddSTomislav Denis * Tweek offset is 0: 646*d935edddSTomislav Denis * +---+---+---+---+ 647*d935edddSTomislav Denis * |D0 |D1 |D2 | X | (3 data bytes) 648*d935edddSTomislav Denis * +---+---+---+---+ 649*d935edddSTomislav Denis * a+0 a+1 a+2 a+3 650*d935edddSTomislav Denis * 651*d935edddSTomislav Denis * Tweek offset is 1: 652*d935edddSTomislav Denis * +---+---+---+---+ 653*d935edddSTomislav Denis * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes) 654*d935edddSTomislav Denis * +---+---+---+---+ 655*d935edddSTomislav Denis * a+0 a+1 a+2 a+3 656*d935edddSTomislav Denis */ 657*d935edddSTomislav Denis memcpy(dest + tweek_offset, src, num_bytes); 658*d935edddSTomislav Denis 659*d935edddSTomislav Denis /* 660*d935edddSTomislav Denis * Data conversion from 16 bits of data to 24 bits of data 661*d935edddSTomislav Denis * is done by sign extension (properly filling padding byte). 662*d935edddSTomislav Denis */ 663*d935edddSTomislav Denis if (tweek_offset) 664*d935edddSTomislav Denis *dest = *src & BIT(7) ? 0xff : 0x00; 665*d935edddSTomislav Denis 666*d935edddSTomislav Denis i++; 667*d935edddSTomislav Denis } 668*d935edddSTomislav Denis 669*d935edddSTomislav Denis iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data, 670*d935edddSTomislav Denis iio_get_time_ns(indio_dev)); 671*d935edddSTomislav Denis 672*d935edddSTomislav Denis out: 673*d935edddSTomislav Denis iio_trigger_notify_done(indio_dev->trig); 674*d935edddSTomislav Denis 675*d935edddSTomislav Denis return IRQ_HANDLED; 676*d935edddSTomislav Denis } 677*d935edddSTomislav Denis 678*d935edddSTomislav Denis static irqreturn_t ads131e08_interrupt(int irq, void *private) 679*d935edddSTomislav Denis { 680*d935edddSTomislav Denis struct iio_dev *indio_dev = private; 681*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 682*d935edddSTomislav Denis 683*d935edddSTomislav Denis if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) 684*d935edddSTomislav Denis iio_trigger_poll(st->trig); 685*d935edddSTomislav Denis else 686*d935edddSTomislav Denis complete(&st->completion); 687*d935edddSTomislav Denis 688*d935edddSTomislav Denis return IRQ_HANDLED; 689*d935edddSTomislav Denis } 690*d935edddSTomislav Denis 691*d935edddSTomislav Denis static int ads131e08_alloc_channels(struct iio_dev *indio_dev) 692*d935edddSTomislav Denis { 693*d935edddSTomislav Denis struct ads131e08_state *st = iio_priv(indio_dev); 694*d935edddSTomislav Denis struct ads131e08_channel_config *channel_config; 695*d935edddSTomislav Denis struct device *dev = &st->spi->dev; 696*d935edddSTomislav Denis struct iio_chan_spec *channels; 697*d935edddSTomislav Denis struct fwnode_handle *node; 698*d935edddSTomislav Denis unsigned int channel, tmp; 699*d935edddSTomislav Denis int num_channels, i, ret; 700*d935edddSTomislav Denis 701*d935edddSTomislav Denis ret = device_property_read_u32(dev, "ti,vref-internal", &tmp); 702*d935edddSTomislav Denis if (ret) 703*d935edddSTomislav Denis tmp = 0; 704*d935edddSTomislav Denis 705*d935edddSTomislav Denis switch (tmp) { 706*d935edddSTomislav Denis case 0: 707*d935edddSTomislav Denis st->vref_mv = ADS131E08_VREF_2V4_mV; 708*d935edddSTomislav Denis break; 709*d935edddSTomislav Denis case 1: 710*d935edddSTomislav Denis st->vref_mv = ADS131E08_VREF_4V_mV; 711*d935edddSTomislav Denis break; 712*d935edddSTomislav Denis default: 713*d935edddSTomislav Denis dev_err(&st->spi->dev, "invalid internal voltage reference\n"); 714*d935edddSTomislav Denis return -EINVAL; 715*d935edddSTomislav Denis } 716*d935edddSTomislav Denis 717*d935edddSTomislav Denis num_channels = device_get_child_node_count(dev); 718*d935edddSTomislav Denis if (num_channels == 0) { 719*d935edddSTomislav Denis dev_err(&st->spi->dev, "no channel children\n"); 720*d935edddSTomislav Denis return -ENODEV; 721*d935edddSTomislav Denis } 722*d935edddSTomislav Denis 723*d935edddSTomislav Denis if (num_channels > st->info->max_channels) { 724*d935edddSTomislav Denis dev_err(&st->spi->dev, "num of channel children out of range\n"); 725*d935edddSTomislav Denis return -EINVAL; 726*d935edddSTomislav Denis } 727*d935edddSTomislav Denis 728*d935edddSTomislav Denis channels = devm_kcalloc(&st->spi->dev, num_channels, 729*d935edddSTomislav Denis sizeof(*channels), GFP_KERNEL); 730*d935edddSTomislav Denis if (!channels) 731*d935edddSTomislav Denis return -ENOMEM; 732*d935edddSTomislav Denis 733*d935edddSTomislav Denis channel_config = devm_kcalloc(&st->spi->dev, num_channels, 734*d935edddSTomislav Denis sizeof(*channel_config), GFP_KERNEL); 735*d935edddSTomislav Denis if (!channel_config) 736*d935edddSTomislav Denis return -ENOMEM; 737*d935edddSTomislav Denis 738*d935edddSTomislav Denis i = 0; 739*d935edddSTomislav Denis device_for_each_child_node(dev, node) { 740*d935edddSTomislav Denis ret = fwnode_property_read_u32(node, "reg", &channel); 741*d935edddSTomislav Denis if (ret) 742*d935edddSTomislav Denis return ret; 743*d935edddSTomislav Denis 744*d935edddSTomislav Denis ret = fwnode_property_read_u32(node, "ti,gain", &tmp); 745*d935edddSTomislav Denis if (ret) { 746*d935edddSTomislav Denis channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN; 747*d935edddSTomislav Denis } else { 748*d935edddSTomislav Denis ret = ads131e08_pga_gain_to_field_value(st, tmp); 749*d935edddSTomislav Denis if (ret < 0) 750*d935edddSTomislav Denis return ret; 751*d935edddSTomislav Denis 752*d935edddSTomislav Denis channel_config[i].pga_gain = tmp; 753*d935edddSTomislav Denis } 754*d935edddSTomislav Denis 755*d935edddSTomislav Denis ret = fwnode_property_read_u32(node, "ti,mux", &tmp); 756*d935edddSTomislav Denis if (ret) { 757*d935edddSTomislav Denis channel_config[i].mux = ADS131E08_DEFAULT_MUX; 758*d935edddSTomislav Denis } else { 759*d935edddSTomislav Denis ret = ads131e08_validate_channel_mux(st, tmp); 760*d935edddSTomislav Denis if (ret) 761*d935edddSTomislav Denis return ret; 762*d935edddSTomislav Denis 763*d935edddSTomislav Denis channel_config[i].mux = tmp; 764*d935edddSTomislav Denis } 765*d935edddSTomislav Denis 766*d935edddSTomislav Denis channels[i].type = IIO_VOLTAGE; 767*d935edddSTomislav Denis channels[i].indexed = 1; 768*d935edddSTomislav Denis channels[i].channel = channel; 769*d935edddSTomislav Denis channels[i].address = i; 770*d935edddSTomislav Denis channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 771*d935edddSTomislav Denis BIT(IIO_CHAN_INFO_SCALE); 772*d935edddSTomislav Denis channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ); 773*d935edddSTomislav Denis channels[i].scan_index = channel; 774*d935edddSTomislav Denis channels[i].scan_type.sign = 's'; 775*d935edddSTomislav Denis channels[i].scan_type.realbits = 24; 776*d935edddSTomislav Denis channels[i].scan_type.storagebits = 32; 777*d935edddSTomislav Denis channels[i].scan_type.shift = 8; 778*d935edddSTomislav Denis channels[i].scan_type.endianness = IIO_BE; 779*d935edddSTomislav Denis i++; 780*d935edddSTomislav Denis } 781*d935edddSTomislav Denis 782*d935edddSTomislav Denis indio_dev->channels = channels; 783*d935edddSTomislav Denis indio_dev->num_channels = num_channels; 784*d935edddSTomislav Denis st->channel_config = channel_config; 785*d935edddSTomislav Denis 786*d935edddSTomislav Denis return 0; 787*d935edddSTomislav Denis } 788*d935edddSTomislav Denis 789*d935edddSTomislav Denis static void ads131e08_regulator_disable(void *data) 790*d935edddSTomislav Denis { 791*d935edddSTomislav Denis struct ads131e08_state *st = data; 792*d935edddSTomislav Denis 793*d935edddSTomislav Denis regulator_disable(st->vref_reg); 794*d935edddSTomislav Denis } 795*d935edddSTomislav Denis 796*d935edddSTomislav Denis static void ads131e08_clk_disable(void *data) 797*d935edddSTomislav Denis { 798*d935edddSTomislav Denis struct ads131e08_state *st = data; 799*d935edddSTomislav Denis 800*d935edddSTomislav Denis clk_disable_unprepare(st->adc_clk); 801*d935edddSTomislav Denis } 802*d935edddSTomislav Denis 803*d935edddSTomislav Denis static int ads131e08_probe(struct spi_device *spi) 804*d935edddSTomislav Denis { 805*d935edddSTomislav Denis const struct ads131e08_info *info; 806*d935edddSTomislav Denis struct ads131e08_state *st; 807*d935edddSTomislav Denis struct iio_dev *indio_dev; 808*d935edddSTomislav Denis unsigned long adc_clk_hz; 809*d935edddSTomislav Denis unsigned long adc_clk_ns; 810*d935edddSTomislav Denis int ret; 811*d935edddSTomislav Denis 812*d935edddSTomislav Denis info = device_get_match_data(&spi->dev); 813*d935edddSTomislav Denis if (!info) { 814*d935edddSTomislav Denis dev_err(&spi->dev, "failed to get match data\n"); 815*d935edddSTomislav Denis return -ENODEV; 816*d935edddSTomislav Denis } 817*d935edddSTomislav Denis 818*d935edddSTomislav Denis indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 819*d935edddSTomislav Denis if (!indio_dev) { 820*d935edddSTomislav Denis dev_err(&spi->dev, "failed to allocate IIO device\n"); 821*d935edddSTomislav Denis return -ENOMEM; 822*d935edddSTomislav Denis } 823*d935edddSTomislav Denis 824*d935edddSTomislav Denis st = iio_priv(indio_dev); 825*d935edddSTomislav Denis st->info = info; 826*d935edddSTomislav Denis st->spi = spi; 827*d935edddSTomislav Denis 828*d935edddSTomislav Denis ret = ads131e08_alloc_channels(indio_dev); 829*d935edddSTomislav Denis if (ret) 830*d935edddSTomislav Denis return ret; 831*d935edddSTomislav Denis 832*d935edddSTomislav Denis indio_dev->name = st->info->name; 833*d935edddSTomislav Denis indio_dev->dev.parent = &spi->dev; 834*d935edddSTomislav Denis indio_dev->info = &ads131e08_iio_info; 835*d935edddSTomislav Denis indio_dev->modes = INDIO_DIRECT_MODE; 836*d935edddSTomislav Denis 837*d935edddSTomislav Denis init_completion(&st->completion); 838*d935edddSTomislav Denis 839*d935edddSTomislav Denis if (spi->irq) { 840*d935edddSTomislav Denis ret = devm_request_irq(&spi->dev, spi->irq, 841*d935edddSTomislav Denis ads131e08_interrupt, 842*d935edddSTomislav Denis IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 843*d935edddSTomislav Denis spi->dev.driver->name, indio_dev); 844*d935edddSTomislav Denis if (ret) 845*d935edddSTomislav Denis return dev_err_probe(&spi->dev, ret, 846*d935edddSTomislav Denis "request irq failed\n"); 847*d935edddSTomislav Denis } else { 848*d935edddSTomislav Denis dev_err(&spi->dev, "data ready IRQ missing\n"); 849*d935edddSTomislav Denis return -ENODEV; 850*d935edddSTomislav Denis } 851*d935edddSTomislav Denis 852*d935edddSTomislav Denis st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 853*d935edddSTomislav Denis indio_dev->name, indio_dev->id); 854*d935edddSTomislav Denis if (!st->trig) { 855*d935edddSTomislav Denis dev_err(&spi->dev, "failed to allocate IIO trigger\n"); 856*d935edddSTomislav Denis return -ENOMEM; 857*d935edddSTomislav Denis } 858*d935edddSTomislav Denis 859*d935edddSTomislav Denis st->trig->ops = &ads131e08_trigger_ops; 860*d935edddSTomislav Denis st->trig->dev.parent = &spi->dev; 861*d935edddSTomislav Denis iio_trigger_set_drvdata(st->trig, indio_dev); 862*d935edddSTomislav Denis ret = devm_iio_trigger_register(&spi->dev, st->trig); 863*d935edddSTomislav Denis if (ret) { 864*d935edddSTomislav Denis dev_err(&spi->dev, "failed to register IIO trigger\n"); 865*d935edddSTomislav Denis return -ENOMEM; 866*d935edddSTomislav Denis } 867*d935edddSTomislav Denis 868*d935edddSTomislav Denis indio_dev->trig = iio_trigger_get(st->trig); 869*d935edddSTomislav Denis 870*d935edddSTomislav Denis ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 871*d935edddSTomislav Denis NULL, &ads131e08_trigger_handler, NULL); 872*d935edddSTomislav Denis if (ret) { 873*d935edddSTomislav Denis dev_err(&spi->dev, "failed to setup IIO buffer\n"); 874*d935edddSTomislav Denis return ret; 875*d935edddSTomislav Denis } 876*d935edddSTomislav Denis 877*d935edddSTomislav Denis st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref"); 878*d935edddSTomislav Denis if (!IS_ERR(st->vref_reg)) { 879*d935edddSTomislav Denis ret = regulator_enable(st->vref_reg); 880*d935edddSTomislav Denis if (ret) { 881*d935edddSTomislav Denis dev_err(&spi->dev, 882*d935edddSTomislav Denis "failed to enable external vref supply\n"); 883*d935edddSTomislav Denis return ret; 884*d935edddSTomislav Denis } 885*d935edddSTomislav Denis 886*d935edddSTomislav Denis ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st); 887*d935edddSTomislav Denis if (ret) 888*d935edddSTomislav Denis return ret; 889*d935edddSTomislav Denis } else { 890*d935edddSTomislav Denis if (PTR_ERR(st->vref_reg) != -ENODEV) 891*d935edddSTomislav Denis return PTR_ERR(st->vref_reg); 892*d935edddSTomislav Denis 893*d935edddSTomislav Denis st->vref_reg = NULL; 894*d935edddSTomislav Denis } 895*d935edddSTomislav Denis 896*d935edddSTomislav Denis st->adc_clk = devm_clk_get(&spi->dev, "adc-clk"); 897*d935edddSTomislav Denis if (IS_ERR(st->adc_clk)) 898*d935edddSTomislav Denis return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk), 899*d935edddSTomislav Denis "failed to get the ADC clock\n"); 900*d935edddSTomislav Denis 901*d935edddSTomislav Denis ret = clk_prepare_enable(st->adc_clk); 902*d935edddSTomislav Denis if (ret) { 903*d935edddSTomislav Denis dev_err(&spi->dev, "failed to prepare/enable the ADC clock\n"); 904*d935edddSTomislav Denis return ret; 905*d935edddSTomislav Denis } 906*d935edddSTomislav Denis 907*d935edddSTomislav Denis ret = devm_add_action_or_reset(&spi->dev, ads131e08_clk_disable, st); 908*d935edddSTomislav Denis if (ret) 909*d935edddSTomislav Denis return ret; 910*d935edddSTomislav Denis 911*d935edddSTomislav Denis adc_clk_hz = clk_get_rate(st->adc_clk); 912*d935edddSTomislav Denis if (!adc_clk_hz) { 913*d935edddSTomislav Denis dev_err(&spi->dev, "failed to get the ADC clock rate\n"); 914*d935edddSTomislav Denis return -EINVAL; 915*d935edddSTomislav Denis } 916*d935edddSTomislav Denis 917*d935edddSTomislav Denis adc_clk_ns = NSEC_PER_SEC / adc_clk_hz; 918*d935edddSTomislav Denis st->sdecode_delay_us = DIV_ROUND_UP( 919*d935edddSTomislav Denis ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC); 920*d935edddSTomislav Denis st->reset_delay_us = DIV_ROUND_UP( 921*d935edddSTomislav Denis ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC); 922*d935edddSTomislav Denis 923*d935edddSTomislav Denis ret = ads131e08_initial_config(indio_dev); 924*d935edddSTomislav Denis if (ret) { 925*d935edddSTomislav Denis dev_err(&spi->dev, "initial configuration failed\n"); 926*d935edddSTomislav Denis return ret; 927*d935edddSTomislav Denis } 928*d935edddSTomislav Denis 929*d935edddSTomislav Denis return devm_iio_device_register(&spi->dev, indio_dev); 930*d935edddSTomislav Denis } 931*d935edddSTomislav Denis 932*d935edddSTomislav Denis static const struct of_device_id ads131e08_of_match[] = { 933*d935edddSTomislav Denis { .compatible = "ti,ads131e04", 934*d935edddSTomislav Denis .data = &ads131e08_info_tbl[ads131e04], }, 935*d935edddSTomislav Denis { .compatible = "ti,ads131e06", 936*d935edddSTomislav Denis .data = &ads131e08_info_tbl[ads131e06], }, 937*d935edddSTomislav Denis { .compatible = "ti,ads131e08", 938*d935edddSTomislav Denis .data = &ads131e08_info_tbl[ads131e08], }, 939*d935edddSTomislav Denis {} 940*d935edddSTomislav Denis }; 941*d935edddSTomislav Denis MODULE_DEVICE_TABLE(of, ads131e08_of_match); 942*d935edddSTomislav Denis 943*d935edddSTomislav Denis static struct spi_driver ads131e08_driver = { 944*d935edddSTomislav Denis .driver = { 945*d935edddSTomislav Denis .name = "ads131e08", 946*d935edddSTomislav Denis .of_match_table = ads131e08_of_match, 947*d935edddSTomislav Denis }, 948*d935edddSTomislav Denis .probe = ads131e08_probe, 949*d935edddSTomislav Denis }; 950*d935edddSTomislav Denis module_spi_driver(ads131e08_driver); 951*d935edddSTomislav Denis 952*d935edddSTomislav Denis MODULE_AUTHOR("Tomislav Denis <tomislav.denis@avl.com>"); 953*d935edddSTomislav Denis MODULE_DESCRIPTION("Driver for ADS131E0x ADC family"); 954*d935edddSTomislav Denis MODULE_LICENSE("GPL v2"); 955