1 // SPDX-License-Identifier: GPL-2.0 2 /* TI ADS124S0X chip family driver 3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 4 */ 5 6 #include <linux/err.h> 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_gpio.h> 13 #include <linux/slab.h> 14 #include <linux/sysfs.h> 15 16 #include <linux/gpio/consumer.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/iio/sysfs.h> 24 25 #include <asm/unaligned.h> 26 27 /* Commands */ 28 #define ADS124S08_CMD_NOP 0x00 29 #define ADS124S08_CMD_WAKEUP 0x02 30 #define ADS124S08_CMD_PWRDWN 0x04 31 #define ADS124S08_CMD_RESET 0x06 32 #define ADS124S08_CMD_START 0x08 33 #define ADS124S08_CMD_STOP 0x0a 34 #define ADS124S08_CMD_SYOCAL 0x16 35 #define ADS124S08_CMD_SYGCAL 0x17 36 #define ADS124S08_CMD_SFOCAL 0x19 37 #define ADS124S08_CMD_RDATA 0x12 38 #define ADS124S08_CMD_RREG 0x20 39 #define ADS124S08_CMD_WREG 0x40 40 41 /* Registers */ 42 #define ADS124S08_ID_REG 0x00 43 #define ADS124S08_STATUS 0x01 44 #define ADS124S08_INPUT_MUX 0x02 45 #define ADS124S08_PGA 0x03 46 #define ADS124S08_DATA_RATE 0x04 47 #define ADS124S08_REF 0x05 48 #define ADS124S08_IDACMAG 0x06 49 #define ADS124S08_IDACMUX 0x07 50 #define ADS124S08_VBIAS 0x08 51 #define ADS124S08_SYS 0x09 52 #define ADS124S08_OFCAL0 0x0a 53 #define ADS124S08_OFCAL1 0x0b 54 #define ADS124S08_OFCAL2 0x0c 55 #define ADS124S08_FSCAL0 0x0d 56 #define ADS124S08_FSCAL1 0x0e 57 #define ADS124S08_FSCAL2 0x0f 58 #define ADS124S08_GPIODAT 0x10 59 #define ADS124S08_GPIOCON 0x11 60 61 /* ADS124S0x common channels */ 62 #define ADS124S08_AIN0 0x00 63 #define ADS124S08_AIN1 0x01 64 #define ADS124S08_AIN2 0x02 65 #define ADS124S08_AIN3 0x03 66 #define ADS124S08_AIN4 0x04 67 #define ADS124S08_AIN5 0x05 68 #define ADS124S08_AINCOM 0x0c 69 /* ADS124S08 only channels */ 70 #define ADS124S08_AIN6 0x06 71 #define ADS124S08_AIN7 0x07 72 #define ADS124S08_AIN8 0x08 73 #define ADS124S08_AIN9 0x09 74 #define ADS124S08_AIN10 0x0a 75 #define ADS124S08_AIN11 0x0b 76 #define ADS124S08_MAX_CHANNELS 12 77 78 #define ADS124S08_POS_MUX_SHIFT 0x04 79 #define ADS124S08_INT_REF 0x09 80 81 #define ADS124S08_START_REG_MASK 0x1f 82 #define ADS124S08_NUM_BYTES_MASK 0x1f 83 84 #define ADS124S08_START_CONV 0x01 85 #define ADS124S08_STOP_CONV 0x00 86 87 enum ads124s_id { 88 ADS124S08_ID, 89 ADS124S06_ID, 90 }; 91 92 struct ads124s_chip_info { 93 const struct iio_chan_spec *channels; 94 unsigned int num_channels; 95 }; 96 97 struct ads124s_private { 98 const struct ads124s_chip_info *chip_info; 99 struct gpio_desc *reset_gpio; 100 struct spi_device *spi; 101 struct mutex lock; 102 u8 data[5] ____cacheline_aligned; 103 }; 104 105 #define ADS124S08_CHAN(index) \ 106 { \ 107 .type = IIO_VOLTAGE, \ 108 .indexed = 1, \ 109 .channel = index, \ 110 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 111 .scan_index = index, \ 112 .scan_type = { \ 113 .sign = 'u', \ 114 .realbits = 32, \ 115 .storagebits = 32, \ 116 }, \ 117 } 118 119 static const struct iio_chan_spec ads124s06_channels[] = { 120 ADS124S08_CHAN(0), 121 ADS124S08_CHAN(1), 122 ADS124S08_CHAN(2), 123 ADS124S08_CHAN(3), 124 ADS124S08_CHAN(4), 125 ADS124S08_CHAN(5), 126 }; 127 128 static const struct iio_chan_spec ads124s08_channels[] = { 129 ADS124S08_CHAN(0), 130 ADS124S08_CHAN(1), 131 ADS124S08_CHAN(2), 132 ADS124S08_CHAN(3), 133 ADS124S08_CHAN(4), 134 ADS124S08_CHAN(5), 135 ADS124S08_CHAN(6), 136 ADS124S08_CHAN(7), 137 ADS124S08_CHAN(8), 138 ADS124S08_CHAN(9), 139 ADS124S08_CHAN(10), 140 ADS124S08_CHAN(11), 141 }; 142 143 static const struct ads124s_chip_info ads124s_chip_info_tbl[] = { 144 [ADS124S08_ID] = { 145 .channels = ads124s08_channels, 146 .num_channels = ARRAY_SIZE(ads124s08_channels), 147 }, 148 [ADS124S06_ID] = { 149 .channels = ads124s06_channels, 150 .num_channels = ARRAY_SIZE(ads124s06_channels), 151 }, 152 }; 153 154 static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command) 155 { 156 struct ads124s_private *priv = iio_priv(indio_dev); 157 158 priv->data[0] = command; 159 160 return spi_write(priv->spi, &priv->data[0], 1); 161 } 162 163 static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data) 164 { 165 struct ads124s_private *priv = iio_priv(indio_dev); 166 167 priv->data[0] = ADS124S08_CMD_WREG | reg; 168 priv->data[1] = 0x0; 169 priv->data[2] = data; 170 171 return spi_write(priv->spi, &priv->data[0], 3); 172 } 173 174 static int ads124s_reset(struct iio_dev *indio_dev) 175 { 176 struct ads124s_private *priv = iio_priv(indio_dev); 177 178 if (priv->reset_gpio) { 179 gpiod_set_value(priv->reset_gpio, 0); 180 udelay(200); 181 gpiod_set_value(priv->reset_gpio, 1); 182 } else { 183 return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET); 184 } 185 186 return 0; 187 }; 188 189 static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) 190 { 191 struct ads124s_private *priv = iio_priv(indio_dev); 192 int ret; 193 struct spi_transfer t[] = { 194 { 195 .tx_buf = &priv->data[0], 196 .len = 4, 197 .cs_change = 1, 198 }, { 199 .tx_buf = &priv->data[1], 200 .rx_buf = &priv->data[1], 201 .len = 4, 202 }, 203 }; 204 205 priv->data[0] = ADS124S08_CMD_RDATA; 206 memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1); 207 208 ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t)); 209 if (ret < 0) 210 return ret; 211 212 return get_unaligned_be24(&priv->data[2]); 213 } 214 215 static int ads124s_read_raw(struct iio_dev *indio_dev, 216 struct iio_chan_spec const *chan, 217 int *val, int *val2, long m) 218 { 219 struct ads124s_private *priv = iio_priv(indio_dev); 220 int ret; 221 222 mutex_lock(&priv->lock); 223 switch (m) { 224 case IIO_CHAN_INFO_RAW: 225 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, 226 chan->channel); 227 if (ret) { 228 dev_err(&priv->spi->dev, "Set ADC CH failed\n"); 229 goto out; 230 } 231 232 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); 233 if (ret) { 234 dev_err(&priv->spi->dev, "Start conversions failed\n"); 235 goto out; 236 } 237 238 ret = ads124s_read(indio_dev, chan->channel); 239 if (ret < 0) { 240 dev_err(&priv->spi->dev, "Read ADC failed\n"); 241 goto out; 242 } 243 244 *val = ret; 245 246 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); 247 if (ret) { 248 dev_err(&priv->spi->dev, "Stop conversions failed\n"); 249 goto out; 250 } 251 252 ret = IIO_VAL_INT; 253 break; 254 default: 255 ret = -EINVAL; 256 break; 257 } 258 out: 259 mutex_unlock(&priv->lock); 260 return ret; 261 } 262 263 static const struct iio_info ads124s_info = { 264 .read_raw = &ads124s_read_raw, 265 }; 266 267 static irqreturn_t ads124s_trigger_handler(int irq, void *p) 268 { 269 struct iio_poll_func *pf = p; 270 struct iio_dev *indio_dev = pf->indio_dev; 271 struct ads124s_private *priv = iio_priv(indio_dev); 272 u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u16)]; 273 int scan_index, j = 0; 274 int ret; 275 276 for_each_set_bit(scan_index, indio_dev->active_scan_mask, 277 indio_dev->masklength) { 278 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, 279 scan_index); 280 if (ret) 281 dev_err(&priv->spi->dev, "Set ADC CH failed\n"); 282 283 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); 284 if (ret) 285 dev_err(&priv->spi->dev, "Start ADC conversions failed\n"); 286 287 buffer[j] = ads124s_read(indio_dev, scan_index); 288 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); 289 if (ret) 290 dev_err(&priv->spi->dev, "Stop ADC conversions failed\n"); 291 292 j++; 293 } 294 295 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 296 pf->timestamp); 297 298 iio_trigger_notify_done(indio_dev->trig); 299 300 return IRQ_HANDLED; 301 } 302 303 static int ads124s_probe(struct spi_device *spi) 304 { 305 struct ads124s_private *ads124s_priv; 306 struct iio_dev *indio_dev; 307 const struct spi_device_id *spi_id = spi_get_device_id(spi); 308 int ret; 309 310 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv)); 311 if (indio_dev == NULL) 312 return -ENOMEM; 313 314 ads124s_priv = iio_priv(indio_dev); 315 316 ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev, 317 "reset", GPIOD_OUT_LOW); 318 if (IS_ERR(ads124s_priv->reset_gpio)) 319 dev_info(&spi->dev, "Reset GPIO not defined\n"); 320 321 ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data]; 322 323 spi_set_drvdata(spi, indio_dev); 324 325 ads124s_priv->spi = spi; 326 327 indio_dev->name = spi_id->name; 328 indio_dev->dev.parent = &spi->dev; 329 indio_dev->dev.of_node = spi->dev.of_node; 330 indio_dev->modes = INDIO_DIRECT_MODE; 331 indio_dev->channels = ads124s_priv->chip_info->channels; 332 indio_dev->num_channels = ads124s_priv->chip_info->num_channels; 333 indio_dev->info = &ads124s_info; 334 335 mutex_init(&ads124s_priv->lock); 336 337 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, 338 ads124s_trigger_handler, NULL); 339 if (ret) { 340 dev_err(&spi->dev, "iio triggered buffer setup failed\n"); 341 return ret; 342 } 343 344 ads124s_reset(indio_dev); 345 346 return devm_iio_device_register(&spi->dev, indio_dev); 347 } 348 349 static const struct spi_device_id ads124s_id[] = { 350 { "ads124s06", ADS124S06_ID }, 351 { "ads124s08", ADS124S08_ID }, 352 { } 353 }; 354 MODULE_DEVICE_TABLE(spi, ads124s_id); 355 356 static const struct of_device_id ads124s_of_table[] = { 357 { .compatible = "ti,ads124s06" }, 358 { .compatible = "ti,ads124s08" }, 359 { }, 360 }; 361 MODULE_DEVICE_TABLE(of, ads124s_of_table); 362 363 static struct spi_driver ads124s_driver = { 364 .driver = { 365 .name = "ads124s08", 366 .of_match_table = ads124s_of_table, 367 }, 368 .probe = ads124s_probe, 369 .id_table = ads124s_id, 370 }; 371 module_spi_driver(ads124s_driver); 372 373 MODULE_AUTHOR("Dan Murphy <dmuprhy@ti.com>"); 374 MODULE_DESCRIPTION("TI TI_ADS12S0X ADC"); 375 MODULE_LICENSE("GPL v2"); 376