1 /* 2 * ADS1015 - Texas Instruments Analog-to-Digital Converter 3 * 4 * Copyright (c) 2016, Intel Corporation. 5 * 6 * This file is subject to the terms and conditions of version 2 of 7 * the GNU General Public License. See the file COPYING in the main 8 * directory of this archive for more details. 9 * 10 * IIO driver for ADS1015 ADC 7-bit I2C slave address: 11 * * 0x48 - ADDR connected to Ground 12 * * 0x49 - ADDR connected to Vdd 13 * * 0x4A - ADDR connected to SDA 14 * * 0x4B - ADDR connected to SCL 15 */ 16 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/init.h> 20 #include <linux/i2c.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/mutex.h> 24 #include <linux/delay.h> 25 26 #include <linux/platform_data/ads1015.h> 27 28 #include <linux/iio/iio.h> 29 #include <linux/iio/types.h> 30 #include <linux/iio/sysfs.h> 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/triggered_buffer.h> 33 #include <linux/iio/trigger_consumer.h> 34 35 #define ADS1015_DRV_NAME "ads1015" 36 37 #define ADS1015_CONV_REG 0x00 38 #define ADS1015_CFG_REG 0x01 39 40 #define ADS1015_CFG_DR_SHIFT 5 41 #define ADS1015_CFG_MOD_SHIFT 8 42 #define ADS1015_CFG_PGA_SHIFT 9 43 #define ADS1015_CFG_MUX_SHIFT 12 44 45 #define ADS1015_CFG_DR_MASK GENMASK(7, 5) 46 #define ADS1015_CFG_MOD_MASK BIT(8) 47 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9) 48 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12) 49 50 /* device operating modes */ 51 #define ADS1015_CONTINUOUS 0 52 #define ADS1015_SINGLESHOT 1 53 54 #define ADS1015_SLEEP_DELAY_MS 2000 55 #define ADS1015_DEFAULT_PGA 2 56 #define ADS1015_DEFAULT_DATA_RATE 4 57 #define ADS1015_DEFAULT_CHAN 0 58 59 enum chip_ids { 60 ADS1015, 61 ADS1115, 62 }; 63 64 enum ads1015_channels { 65 ADS1015_AIN0_AIN1 = 0, 66 ADS1015_AIN0_AIN3, 67 ADS1015_AIN1_AIN3, 68 ADS1015_AIN2_AIN3, 69 ADS1015_AIN0, 70 ADS1015_AIN1, 71 ADS1015_AIN2, 72 ADS1015_AIN3, 73 ADS1015_TIMESTAMP, 74 }; 75 76 static const unsigned int ads1015_data_rate[] = { 77 128, 250, 490, 920, 1600, 2400, 3300, 3300 78 }; 79 80 static const unsigned int ads1115_data_rate[] = { 81 8, 16, 32, 64, 128, 250, 475, 860 82 }; 83 84 static const struct { 85 int scale; 86 int uscale; 87 } ads1015_scale[] = { 88 {3, 0}, 89 {2, 0}, 90 {1, 0}, 91 {0, 500000}, 92 {0, 250000}, 93 {0, 125000}, 94 {0, 125000}, 95 {0, 125000}, 96 }; 97 98 #define ADS1015_V_CHAN(_chan, _addr) { \ 99 .type = IIO_VOLTAGE, \ 100 .indexed = 1, \ 101 .address = _addr, \ 102 .channel = _chan, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 104 BIT(IIO_CHAN_INFO_SCALE) | \ 105 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 106 .scan_index = _addr, \ 107 .scan_type = { \ 108 .sign = 's', \ 109 .realbits = 12, \ 110 .storagebits = 16, \ 111 .shift = 4, \ 112 .endianness = IIO_CPU, \ 113 }, \ 114 .datasheet_name = "AIN"#_chan, \ 115 } 116 117 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \ 118 .type = IIO_VOLTAGE, \ 119 .differential = 1, \ 120 .indexed = 1, \ 121 .address = _addr, \ 122 .channel = _chan, \ 123 .channel2 = _chan2, \ 124 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 125 BIT(IIO_CHAN_INFO_SCALE) | \ 126 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 127 .scan_index = _addr, \ 128 .scan_type = { \ 129 .sign = 's', \ 130 .realbits = 12, \ 131 .storagebits = 16, \ 132 .shift = 4, \ 133 .endianness = IIO_CPU, \ 134 }, \ 135 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 136 } 137 138 #define ADS1115_V_CHAN(_chan, _addr) { \ 139 .type = IIO_VOLTAGE, \ 140 .indexed = 1, \ 141 .address = _addr, \ 142 .channel = _chan, \ 143 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 144 BIT(IIO_CHAN_INFO_SCALE) | \ 145 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 146 .scan_index = _addr, \ 147 .scan_type = { \ 148 .sign = 's', \ 149 .realbits = 16, \ 150 .storagebits = 16, \ 151 .endianness = IIO_CPU, \ 152 }, \ 153 .datasheet_name = "AIN"#_chan, \ 154 } 155 156 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \ 157 .type = IIO_VOLTAGE, \ 158 .differential = 1, \ 159 .indexed = 1, \ 160 .address = _addr, \ 161 .channel = _chan, \ 162 .channel2 = _chan2, \ 163 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 164 BIT(IIO_CHAN_INFO_SCALE) | \ 165 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 166 .scan_index = _addr, \ 167 .scan_type = { \ 168 .sign = 's', \ 169 .realbits = 16, \ 170 .storagebits = 16, \ 171 .endianness = IIO_CPU, \ 172 }, \ 173 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 174 } 175 176 struct ads1015_data { 177 struct regmap *regmap; 178 /* 179 * Protects ADC ops, e.g: concurrent sysfs/buffered 180 * data reads, configuration updates 181 */ 182 struct mutex lock; 183 struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; 184 185 unsigned int *data_rate; 186 }; 187 188 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg) 189 { 190 return (reg == ADS1015_CFG_REG); 191 } 192 193 static const struct regmap_config ads1015_regmap_config = { 194 .reg_bits = 8, 195 .val_bits = 16, 196 .max_register = ADS1015_CFG_REG, 197 .writeable_reg = ads1015_is_writeable_reg, 198 }; 199 200 static const struct iio_chan_spec ads1015_channels[] = { 201 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1), 202 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3), 203 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3), 204 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3), 205 ADS1015_V_CHAN(0, ADS1015_AIN0), 206 ADS1015_V_CHAN(1, ADS1015_AIN1), 207 ADS1015_V_CHAN(2, ADS1015_AIN2), 208 ADS1015_V_CHAN(3, ADS1015_AIN3), 209 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 210 }; 211 212 static const struct iio_chan_spec ads1115_channels[] = { 213 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1), 214 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3), 215 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3), 216 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3), 217 ADS1115_V_CHAN(0, ADS1015_AIN0), 218 ADS1115_V_CHAN(1, ADS1015_AIN1), 219 ADS1115_V_CHAN(2, ADS1015_AIN2), 220 ADS1115_V_CHAN(3, ADS1015_AIN3), 221 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 222 }; 223 224 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 225 { 226 int ret; 227 struct device *dev = regmap_get_device(data->regmap); 228 229 if (on) { 230 ret = pm_runtime_get_sync(dev); 231 if (ret < 0) 232 pm_runtime_put_noidle(dev); 233 } else { 234 pm_runtime_mark_last_busy(dev); 235 ret = pm_runtime_put_autosuspend(dev); 236 } 237 238 return ret; 239 } 240 241 static 242 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) 243 { 244 int ret, pga, dr, conv_time; 245 bool change; 246 247 if (chan < 0 || chan >= ADS1015_CHANNELS) 248 return -EINVAL; 249 250 pga = data->channel_data[chan].pga; 251 dr = data->channel_data[chan].data_rate; 252 253 ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG, 254 ADS1015_CFG_MUX_MASK | 255 ADS1015_CFG_PGA_MASK, 256 chan << ADS1015_CFG_MUX_SHIFT | 257 pga << ADS1015_CFG_PGA_SHIFT, 258 &change); 259 if (ret < 0) 260 return ret; 261 262 if (change) { 263 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]); 264 usleep_range(conv_time, conv_time + 1); 265 } 266 267 return regmap_read(data->regmap, ADS1015_CONV_REG, val); 268 } 269 270 static irqreturn_t ads1015_trigger_handler(int irq, void *p) 271 { 272 struct iio_poll_func *pf = p; 273 struct iio_dev *indio_dev = pf->indio_dev; 274 struct ads1015_data *data = iio_priv(indio_dev); 275 s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */ 276 int chan, ret, res; 277 278 memset(buf, 0, sizeof(buf)); 279 280 mutex_lock(&data->lock); 281 chan = find_first_bit(indio_dev->active_scan_mask, 282 indio_dev->masklength); 283 ret = ads1015_get_adc_result(data, chan, &res); 284 if (ret < 0) { 285 mutex_unlock(&data->lock); 286 goto err; 287 } 288 289 buf[0] = res; 290 mutex_unlock(&data->lock); 291 292 iio_push_to_buffers_with_timestamp(indio_dev, buf, 293 iio_get_time_ns(indio_dev)); 294 295 err: 296 iio_trigger_notify_done(indio_dev->trig); 297 298 return IRQ_HANDLED; 299 } 300 301 static int ads1015_set_scale(struct ads1015_data *data, int chan, 302 int scale, int uscale) 303 { 304 int i, ret, rindex = -1; 305 306 for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++) 307 if (ads1015_scale[i].scale == scale && 308 ads1015_scale[i].uscale == uscale) { 309 rindex = i; 310 break; 311 } 312 if (rindex < 0) 313 return -EINVAL; 314 315 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 316 ADS1015_CFG_PGA_MASK, 317 rindex << ADS1015_CFG_PGA_SHIFT); 318 if (ret < 0) 319 return ret; 320 321 data->channel_data[chan].pga = rindex; 322 323 return 0; 324 } 325 326 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate) 327 { 328 int i, ret, rindex = -1; 329 330 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) 331 if (data->data_rate[i] == rate) { 332 rindex = i; 333 break; 334 } 335 if (rindex < 0) 336 return -EINVAL; 337 338 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 339 ADS1015_CFG_DR_MASK, 340 rindex << ADS1015_CFG_DR_SHIFT); 341 if (ret < 0) 342 return ret; 343 344 data->channel_data[chan].data_rate = rindex; 345 346 return 0; 347 } 348 349 static int ads1015_read_raw(struct iio_dev *indio_dev, 350 struct iio_chan_spec const *chan, int *val, 351 int *val2, long mask) 352 { 353 int ret, idx; 354 struct ads1015_data *data = iio_priv(indio_dev); 355 356 mutex_lock(&indio_dev->mlock); 357 mutex_lock(&data->lock); 358 switch (mask) { 359 case IIO_CHAN_INFO_RAW: { 360 int shift = chan->scan_type.shift; 361 362 if (iio_buffer_enabled(indio_dev)) { 363 ret = -EBUSY; 364 break; 365 } 366 367 ret = ads1015_set_power_state(data, true); 368 if (ret < 0) 369 break; 370 371 ret = ads1015_get_adc_result(data, chan->address, val); 372 if (ret < 0) { 373 ads1015_set_power_state(data, false); 374 break; 375 } 376 377 *val = sign_extend32(*val >> shift, 15 - shift); 378 379 ret = ads1015_set_power_state(data, false); 380 if (ret < 0) 381 break; 382 383 ret = IIO_VAL_INT; 384 break; 385 } 386 case IIO_CHAN_INFO_SCALE: 387 idx = data->channel_data[chan->address].pga; 388 *val = ads1015_scale[idx].scale; 389 *val2 = ads1015_scale[idx].uscale; 390 ret = IIO_VAL_INT_PLUS_MICRO; 391 break; 392 case IIO_CHAN_INFO_SAMP_FREQ: 393 idx = data->channel_data[chan->address].data_rate; 394 *val = data->data_rate[idx]; 395 ret = IIO_VAL_INT; 396 break; 397 default: 398 ret = -EINVAL; 399 break; 400 } 401 mutex_unlock(&data->lock); 402 mutex_unlock(&indio_dev->mlock); 403 404 return ret; 405 } 406 407 static int ads1015_write_raw(struct iio_dev *indio_dev, 408 struct iio_chan_spec const *chan, int val, 409 int val2, long mask) 410 { 411 struct ads1015_data *data = iio_priv(indio_dev); 412 int ret; 413 414 mutex_lock(&data->lock); 415 switch (mask) { 416 case IIO_CHAN_INFO_SCALE: 417 ret = ads1015_set_scale(data, chan->address, val, val2); 418 break; 419 case IIO_CHAN_INFO_SAMP_FREQ: 420 ret = ads1015_set_data_rate(data, chan->address, val); 421 break; 422 default: 423 ret = -EINVAL; 424 break; 425 } 426 mutex_unlock(&data->lock); 427 428 return ret; 429 } 430 431 static int ads1015_buffer_preenable(struct iio_dev *indio_dev) 432 { 433 return ads1015_set_power_state(iio_priv(indio_dev), true); 434 } 435 436 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev) 437 { 438 return ads1015_set_power_state(iio_priv(indio_dev), false); 439 } 440 441 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = { 442 .preenable = ads1015_buffer_preenable, 443 .postenable = iio_triggered_buffer_postenable, 444 .predisable = iio_triggered_buffer_predisable, 445 .postdisable = ads1015_buffer_postdisable, 446 .validate_scan_mask = &iio_validate_scan_mask_onehot, 447 }; 448 449 static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125"); 450 451 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available, 452 sampling_frequency_available, "128 250 490 920 1600 2400 3300"); 453 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available, 454 sampling_frequency_available, "8 16 32 64 128 250 475 860"); 455 456 static struct attribute *ads1015_attributes[] = { 457 &iio_const_attr_scale_available.dev_attr.attr, 458 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr, 459 NULL, 460 }; 461 462 static const struct attribute_group ads1015_attribute_group = { 463 .attrs = ads1015_attributes, 464 }; 465 466 static struct attribute *ads1115_attributes[] = { 467 &iio_const_attr_scale_available.dev_attr.attr, 468 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr, 469 NULL, 470 }; 471 472 static const struct attribute_group ads1115_attribute_group = { 473 .attrs = ads1115_attributes, 474 }; 475 476 static const struct iio_info ads1015_info = { 477 .driver_module = THIS_MODULE, 478 .read_raw = ads1015_read_raw, 479 .write_raw = ads1015_write_raw, 480 .attrs = &ads1015_attribute_group, 481 }; 482 483 static const struct iio_info ads1115_info = { 484 .driver_module = THIS_MODULE, 485 .read_raw = ads1015_read_raw, 486 .write_raw = ads1015_write_raw, 487 .attrs = &ads1115_attribute_group, 488 }; 489 490 #ifdef CONFIG_OF 491 static int ads1015_get_channels_config_of(struct i2c_client *client) 492 { 493 struct iio_dev *indio_dev = i2c_get_clientdata(client); 494 struct ads1015_data *data = iio_priv(indio_dev); 495 struct device_node *node; 496 497 if (!client->dev.of_node || 498 !of_get_next_child(client->dev.of_node, NULL)) 499 return -EINVAL; 500 501 for_each_child_of_node(client->dev.of_node, node) { 502 u32 pval; 503 unsigned int channel; 504 unsigned int pga = ADS1015_DEFAULT_PGA; 505 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE; 506 507 if (of_property_read_u32(node, "reg", &pval)) { 508 dev_err(&client->dev, "invalid reg on %s\n", 509 node->full_name); 510 continue; 511 } 512 513 channel = pval; 514 if (channel >= ADS1015_CHANNELS) { 515 dev_err(&client->dev, 516 "invalid channel index %d on %s\n", 517 channel, node->full_name); 518 continue; 519 } 520 521 if (!of_property_read_u32(node, "ti,gain", &pval)) { 522 pga = pval; 523 if (pga > 6) { 524 dev_err(&client->dev, "invalid gain on %s\n", 525 node->full_name); 526 of_node_put(node); 527 return -EINVAL; 528 } 529 } 530 531 if (!of_property_read_u32(node, "ti,datarate", &pval)) { 532 data_rate = pval; 533 if (data_rate > 7) { 534 dev_err(&client->dev, 535 "invalid data_rate on %s\n", 536 node->full_name); 537 of_node_put(node); 538 return -EINVAL; 539 } 540 } 541 542 data->channel_data[channel].pga = pga; 543 data->channel_data[channel].data_rate = data_rate; 544 } 545 546 return 0; 547 } 548 #endif 549 550 static void ads1015_get_channels_config(struct i2c_client *client) 551 { 552 unsigned int k; 553 554 struct iio_dev *indio_dev = i2c_get_clientdata(client); 555 struct ads1015_data *data = iio_priv(indio_dev); 556 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev); 557 558 /* prefer platform data */ 559 if (pdata) { 560 memcpy(data->channel_data, pdata->channel_data, 561 sizeof(data->channel_data)); 562 return; 563 } 564 565 #ifdef CONFIG_OF 566 if (!ads1015_get_channels_config_of(client)) 567 return; 568 #endif 569 /* fallback on default configuration */ 570 for (k = 0; k < ADS1015_CHANNELS; ++k) { 571 data->channel_data[k].pga = ADS1015_DEFAULT_PGA; 572 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE; 573 } 574 } 575 576 static int ads1015_probe(struct i2c_client *client, 577 const struct i2c_device_id *id) 578 { 579 struct iio_dev *indio_dev; 580 struct ads1015_data *data; 581 int ret; 582 enum chip_ids chip; 583 584 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 585 if (!indio_dev) 586 return -ENOMEM; 587 588 data = iio_priv(indio_dev); 589 i2c_set_clientdata(client, indio_dev); 590 591 mutex_init(&data->lock); 592 593 indio_dev->dev.parent = &client->dev; 594 indio_dev->dev.of_node = client->dev.of_node; 595 indio_dev->name = ADS1015_DRV_NAME; 596 indio_dev->modes = INDIO_DIRECT_MODE; 597 598 if (client->dev.of_node) 599 chip = (enum chip_ids)of_device_get_match_data(&client->dev); 600 else 601 chip = id->driver_data; 602 switch (chip) { 603 case ADS1015: 604 indio_dev->channels = ads1015_channels; 605 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels); 606 indio_dev->info = &ads1015_info; 607 data->data_rate = (unsigned int *) &ads1015_data_rate; 608 break; 609 case ADS1115: 610 indio_dev->channels = ads1115_channels; 611 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels); 612 indio_dev->info = &ads1115_info; 613 data->data_rate = (unsigned int *) &ads1115_data_rate; 614 break; 615 } 616 617 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */ 618 ads1015_get_channels_config(client); 619 620 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config); 621 if (IS_ERR(data->regmap)) { 622 dev_err(&client->dev, "Failed to allocate register map\n"); 623 return PTR_ERR(data->regmap); 624 } 625 626 ret = iio_triggered_buffer_setup(indio_dev, NULL, 627 ads1015_trigger_handler, 628 &ads1015_buffer_setup_ops); 629 if (ret < 0) { 630 dev_err(&client->dev, "iio triggered buffer setup failed\n"); 631 return ret; 632 } 633 ret = pm_runtime_set_active(&client->dev); 634 if (ret) 635 goto err_buffer_cleanup; 636 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS); 637 pm_runtime_use_autosuspend(&client->dev); 638 pm_runtime_enable(&client->dev); 639 640 ret = iio_device_register(indio_dev); 641 if (ret < 0) { 642 dev_err(&client->dev, "Failed to register IIO device\n"); 643 goto err_buffer_cleanup; 644 } 645 646 return 0; 647 648 err_buffer_cleanup: 649 iio_triggered_buffer_cleanup(indio_dev); 650 651 return ret; 652 } 653 654 static int ads1015_remove(struct i2c_client *client) 655 { 656 struct iio_dev *indio_dev = i2c_get_clientdata(client); 657 struct ads1015_data *data = iio_priv(indio_dev); 658 659 iio_device_unregister(indio_dev); 660 661 pm_runtime_disable(&client->dev); 662 pm_runtime_set_suspended(&client->dev); 663 pm_runtime_put_noidle(&client->dev); 664 665 iio_triggered_buffer_cleanup(indio_dev); 666 667 /* power down single shot mode */ 668 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 669 ADS1015_CFG_MOD_MASK, 670 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT); 671 } 672 673 #ifdef CONFIG_PM 674 static int ads1015_runtime_suspend(struct device *dev) 675 { 676 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 677 struct ads1015_data *data = iio_priv(indio_dev); 678 679 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 680 ADS1015_CFG_MOD_MASK, 681 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT); 682 } 683 684 static int ads1015_runtime_resume(struct device *dev) 685 { 686 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 687 struct ads1015_data *data = iio_priv(indio_dev); 688 689 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 690 ADS1015_CFG_MOD_MASK, 691 ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT); 692 } 693 #endif 694 695 static const struct dev_pm_ops ads1015_pm_ops = { 696 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend, 697 ads1015_runtime_resume, NULL) 698 }; 699 700 static const struct i2c_device_id ads1015_id[] = { 701 {"ads1015", ADS1015}, 702 {"ads1115", ADS1115}, 703 {} 704 }; 705 MODULE_DEVICE_TABLE(i2c, ads1015_id); 706 707 static const struct of_device_id ads1015_of_match[] = { 708 { 709 .compatible = "ti,ads1015", 710 .data = (void *)ADS1015 711 }, 712 { 713 .compatible = "ti,ads1115", 714 .data = (void *)ADS1115 715 }, 716 {} 717 }; 718 MODULE_DEVICE_TABLE(of, ads1015_of_match); 719 720 static struct i2c_driver ads1015_driver = { 721 .driver = { 722 .name = ADS1015_DRV_NAME, 723 .of_match_table = ads1015_of_match, 724 .pm = &ads1015_pm_ops, 725 }, 726 .probe = ads1015_probe, 727 .remove = ads1015_remove, 728 .id_table = ads1015_id, 729 }; 730 731 module_i2c_driver(ads1015_driver); 732 733 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 734 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver"); 735 MODULE_LICENSE("GPL v2"); 736