xref: /openbmc/linux/drivers/iio/adc/ti-ads1015.c (revision 0edbfea5)
1 /*
2  * ADS1015 - Texas Instruments Analog-to-Digital Converter
3  *
4  * Copyright (c) 2016, Intel Corporation.
5  *
6  * This file is subject to the terms and conditions of version 2 of
7  * the GNU General Public License.  See the file COPYING in the main
8  * directory of this archive for more details.
9  *
10  * IIO driver for ADS1015 ADC 7-bit I2C slave address:
11  *	* 0x48 - ADDR connected to Ground
12  *	* 0x49 - ADDR connected to Vdd
13  *	* 0x4A - ADDR connected to SDA
14  *	* 0x4B - ADDR connected to SCL
15  */
16 
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
24 
25 #include <linux/i2c/ads1015.h>
26 
27 #include <linux/iio/iio.h>
28 #include <linux/iio/types.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33 
34 #define ADS1015_DRV_NAME "ads1015"
35 
36 #define ADS1015_CONV_REG	0x00
37 #define ADS1015_CFG_REG		0x01
38 
39 #define ADS1015_CFG_DR_SHIFT	5
40 #define ADS1015_CFG_MOD_SHIFT	8
41 #define ADS1015_CFG_PGA_SHIFT	9
42 #define ADS1015_CFG_MUX_SHIFT	12
43 
44 #define ADS1015_CFG_DR_MASK	GENMASK(7, 5)
45 #define ADS1015_CFG_MOD_MASK	BIT(8)
46 #define ADS1015_CFG_PGA_MASK	GENMASK(11, 9)
47 #define ADS1015_CFG_MUX_MASK	GENMASK(14, 12)
48 
49 /* device operating modes */
50 #define ADS1015_CONTINUOUS	0
51 #define ADS1015_SINGLESHOT	1
52 
53 #define ADS1015_SLEEP_DELAY_MS		2000
54 #define ADS1015_DEFAULT_PGA		2
55 #define ADS1015_DEFAULT_DATA_RATE	4
56 #define ADS1015_DEFAULT_CHAN		0
57 
58 enum ads1015_channels {
59 	ADS1015_AIN0_AIN1 = 0,
60 	ADS1015_AIN0_AIN3,
61 	ADS1015_AIN1_AIN3,
62 	ADS1015_AIN2_AIN3,
63 	ADS1015_AIN0,
64 	ADS1015_AIN1,
65 	ADS1015_AIN2,
66 	ADS1015_AIN3,
67 	ADS1015_TIMESTAMP,
68 };
69 
70 static const unsigned int ads1015_data_rate[] = {
71 	128, 250, 490, 920, 1600, 2400, 3300, 3300
72 };
73 
74 static const struct {
75 	int scale;
76 	int uscale;
77 } ads1015_scale[] = {
78 	{3, 0},
79 	{2, 0},
80 	{1, 0},
81 	{0, 500000},
82 	{0, 250000},
83 	{0, 125000},
84 	{0, 125000},
85 	{0, 125000},
86 };
87 
88 #define ADS1015_V_CHAN(_chan, _addr) {				\
89 	.type = IIO_VOLTAGE,					\
90 	.indexed = 1,						\
91 	.address = _addr,					\
92 	.channel = _chan,					\
93 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
94 				BIT(IIO_CHAN_INFO_SCALE) |	\
95 				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
96 	.scan_index = _addr,					\
97 	.scan_type = {						\
98 		.sign = 's',					\
99 		.realbits = 12,					\
100 		.storagebits = 16,				\
101 		.shift = 4,					\
102 		.endianness = IIO_CPU,				\
103 	},							\
104 }
105 
106 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) {		\
107 	.type = IIO_VOLTAGE,					\
108 	.differential = 1,					\
109 	.indexed = 1,						\
110 	.address = _addr,					\
111 	.channel = _chan,					\
112 	.channel2 = _chan2,					\
113 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
114 				BIT(IIO_CHAN_INFO_SCALE) |	\
115 				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
116 	.scan_index = _addr,					\
117 	.scan_type = {						\
118 		.sign = 's',					\
119 		.realbits = 12,					\
120 		.storagebits = 16,				\
121 		.shift = 4,					\
122 		.endianness = IIO_CPU,				\
123 	},							\
124 }
125 
126 struct ads1015_data {
127 	struct regmap *regmap;
128 	/*
129 	 * Protects ADC ops, e.g: concurrent sysfs/buffered
130 	 * data reads, configuration updates
131 	 */
132 	struct mutex lock;
133 	struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
134 };
135 
136 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
137 {
138 	return (reg == ADS1015_CFG_REG);
139 }
140 
141 static const struct regmap_config ads1015_regmap_config = {
142 	.reg_bits = 8,
143 	.val_bits = 16,
144 	.max_register = ADS1015_CFG_REG,
145 	.writeable_reg = ads1015_is_writeable_reg,
146 };
147 
148 static const struct iio_chan_spec ads1015_channels[] = {
149 	ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
150 	ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
151 	ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
152 	ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
153 	ADS1015_V_CHAN(0, ADS1015_AIN0),
154 	ADS1015_V_CHAN(1, ADS1015_AIN1),
155 	ADS1015_V_CHAN(2, ADS1015_AIN2),
156 	ADS1015_V_CHAN(3, ADS1015_AIN3),
157 	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
158 };
159 
160 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
161 {
162 	int ret;
163 	struct device *dev = regmap_get_device(data->regmap);
164 
165 	if (on) {
166 		ret = pm_runtime_get_sync(dev);
167 		if (ret < 0)
168 			pm_runtime_put_noidle(dev);
169 	} else {
170 		pm_runtime_mark_last_busy(dev);
171 		ret = pm_runtime_put_autosuspend(dev);
172 	}
173 
174 	return ret;
175 }
176 
177 static
178 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
179 {
180 	int ret, pga, dr, conv_time;
181 	bool change;
182 
183 	if (chan < 0 || chan >= ADS1015_CHANNELS)
184 		return -EINVAL;
185 
186 	pga = data->channel_data[chan].pga;
187 	dr = data->channel_data[chan].data_rate;
188 
189 	ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
190 				       ADS1015_CFG_MUX_MASK |
191 				       ADS1015_CFG_PGA_MASK,
192 				       chan << ADS1015_CFG_MUX_SHIFT |
193 				       pga << ADS1015_CFG_PGA_SHIFT,
194 				       &change);
195 	if (ret < 0)
196 		return ret;
197 
198 	if (change) {
199 		conv_time = DIV_ROUND_UP(USEC_PER_SEC, ads1015_data_rate[dr]);
200 		usleep_range(conv_time, conv_time + 1);
201 	}
202 
203 	return regmap_read(data->regmap, ADS1015_CONV_REG, val);
204 }
205 
206 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
207 {
208 	struct iio_poll_func *pf = p;
209 	struct iio_dev *indio_dev = pf->indio_dev;
210 	struct ads1015_data *data = iio_priv(indio_dev);
211 	s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding +  4x s16 timestamp */
212 	int chan, ret, res;
213 
214 	memset(buf, 0, sizeof(buf));
215 
216 	mutex_lock(&data->lock);
217 	chan = find_first_bit(indio_dev->active_scan_mask,
218 			      indio_dev->masklength);
219 	ret = ads1015_get_adc_result(data, chan, &res);
220 	if (ret < 0) {
221 		mutex_unlock(&data->lock);
222 		goto err;
223 	}
224 
225 	buf[0] = res;
226 	mutex_unlock(&data->lock);
227 
228 	iio_push_to_buffers_with_timestamp(indio_dev, buf, iio_get_time_ns());
229 
230 err:
231 	iio_trigger_notify_done(indio_dev->trig);
232 
233 	return IRQ_HANDLED;
234 }
235 
236 static int ads1015_set_scale(struct ads1015_data *data, int chan,
237 			     int scale, int uscale)
238 {
239 	int i, ret, rindex = -1;
240 
241 	for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++)
242 		if (ads1015_scale[i].scale == scale &&
243 		    ads1015_scale[i].uscale == uscale) {
244 			rindex = i;
245 			break;
246 		}
247 	if (rindex < 0)
248 		return -EINVAL;
249 
250 	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
251 				 ADS1015_CFG_PGA_MASK,
252 				 rindex << ADS1015_CFG_PGA_SHIFT);
253 	if (ret < 0)
254 		return ret;
255 
256 	data->channel_data[chan].pga = rindex;
257 
258 	return 0;
259 }
260 
261 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
262 {
263 	int i, ret, rindex = -1;
264 
265 	for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++)
266 		if (ads1015_data_rate[i] == rate) {
267 			rindex = i;
268 			break;
269 		}
270 	if (rindex < 0)
271 		return -EINVAL;
272 
273 	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
274 				 ADS1015_CFG_DR_MASK,
275 				 rindex << ADS1015_CFG_DR_SHIFT);
276 	if (ret < 0)
277 		return ret;
278 
279 	data->channel_data[chan].data_rate = rindex;
280 
281 	return 0;
282 }
283 
284 static int ads1015_read_raw(struct iio_dev *indio_dev,
285 			    struct iio_chan_spec const *chan, int *val,
286 			    int *val2, long mask)
287 {
288 	int ret, idx;
289 	struct ads1015_data *data = iio_priv(indio_dev);
290 
291 	mutex_lock(&indio_dev->mlock);
292 	mutex_lock(&data->lock);
293 	switch (mask) {
294 	case IIO_CHAN_INFO_RAW:
295 		if (iio_buffer_enabled(indio_dev)) {
296 			ret = -EBUSY;
297 			break;
298 		}
299 
300 		ret = ads1015_set_power_state(data, true);
301 		if (ret < 0)
302 			break;
303 
304 		ret = ads1015_get_adc_result(data, chan->address, val);
305 		if (ret < 0) {
306 			ads1015_set_power_state(data, false);
307 			break;
308 		}
309 
310 		/* 12 bit res, D0 is bit 4 in conversion register */
311 		*val = sign_extend32(*val >> 4, 11);
312 
313 		ret = ads1015_set_power_state(data, false);
314 		if (ret < 0)
315 			break;
316 
317 		ret = IIO_VAL_INT;
318 		break;
319 	case IIO_CHAN_INFO_SCALE:
320 		idx = data->channel_data[chan->address].pga;
321 		*val = ads1015_scale[idx].scale;
322 		*val2 = ads1015_scale[idx].uscale;
323 		ret = IIO_VAL_INT_PLUS_MICRO;
324 		break;
325 	case IIO_CHAN_INFO_SAMP_FREQ:
326 		idx = data->channel_data[chan->address].data_rate;
327 		*val = ads1015_data_rate[idx];
328 		ret = IIO_VAL_INT;
329 		break;
330 	default:
331 		ret = -EINVAL;
332 		break;
333 	}
334 	mutex_unlock(&data->lock);
335 	mutex_unlock(&indio_dev->mlock);
336 
337 	return ret;
338 }
339 
340 static int ads1015_write_raw(struct iio_dev *indio_dev,
341 			     struct iio_chan_spec const *chan, int val,
342 			     int val2, long mask)
343 {
344 	struct ads1015_data *data = iio_priv(indio_dev);
345 	int ret;
346 
347 	mutex_lock(&data->lock);
348 	switch (mask) {
349 	case IIO_CHAN_INFO_SCALE:
350 		ret = ads1015_set_scale(data, chan->address, val, val2);
351 		break;
352 	case IIO_CHAN_INFO_SAMP_FREQ:
353 		ret = ads1015_set_data_rate(data, chan->address, val);
354 		break;
355 	default:
356 		ret = -EINVAL;
357 		break;
358 	}
359 	mutex_unlock(&data->lock);
360 
361 	return ret;
362 }
363 
364 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
365 {
366 	return ads1015_set_power_state(iio_priv(indio_dev), true);
367 }
368 
369 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
370 {
371 	return ads1015_set_power_state(iio_priv(indio_dev), false);
372 }
373 
374 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
375 	.preenable	= ads1015_buffer_preenable,
376 	.postenable	= iio_triggered_buffer_postenable,
377 	.predisable	= iio_triggered_buffer_predisable,
378 	.postdisable	= ads1015_buffer_postdisable,
379 	.validate_scan_mask = &iio_validate_scan_mask_onehot,
380 };
381 
382 static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125");
383 static IIO_CONST_ATTR(sampling_frequency_available,
384 		      "128 250 490 920 1600 2400 3300");
385 
386 static struct attribute *ads1015_attributes[] = {
387 	&iio_const_attr_scale_available.dev_attr.attr,
388 	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
389 	NULL,
390 };
391 
392 static const struct attribute_group ads1015_attribute_group = {
393 	.attrs = ads1015_attributes,
394 };
395 
396 static const struct iio_info ads1015_info = {
397 	.driver_module	= THIS_MODULE,
398 	.read_raw	= ads1015_read_raw,
399 	.write_raw	= ads1015_write_raw,
400 	.attrs		= &ads1015_attribute_group,
401 };
402 
403 #ifdef CONFIG_OF
404 static int ads1015_get_channels_config_of(struct i2c_client *client)
405 {
406 	struct ads1015_data *data = i2c_get_clientdata(client);
407 	struct device_node *node;
408 
409 	if (!client->dev.of_node ||
410 	    !of_get_next_child(client->dev.of_node, NULL))
411 		return -EINVAL;
412 
413 	for_each_child_of_node(client->dev.of_node, node) {
414 		u32 pval;
415 		unsigned int channel;
416 		unsigned int pga = ADS1015_DEFAULT_PGA;
417 		unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
418 
419 		if (of_property_read_u32(node, "reg", &pval)) {
420 			dev_err(&client->dev, "invalid reg on %s\n",
421 				node->full_name);
422 			continue;
423 		}
424 
425 		channel = pval;
426 		if (channel >= ADS1015_CHANNELS) {
427 			dev_err(&client->dev,
428 				"invalid channel index %d on %s\n",
429 				channel, node->full_name);
430 			continue;
431 		}
432 
433 		if (!of_property_read_u32(node, "ti,gain", &pval)) {
434 			pga = pval;
435 			if (pga > 6) {
436 				dev_err(&client->dev, "invalid gain on %s\n",
437 					node->full_name);
438 				return -EINVAL;
439 			}
440 		}
441 
442 		if (!of_property_read_u32(node, "ti,datarate", &pval)) {
443 			data_rate = pval;
444 			if (data_rate > 7) {
445 				dev_err(&client->dev,
446 					"invalid data_rate on %s\n",
447 					node->full_name);
448 				return -EINVAL;
449 			}
450 		}
451 
452 		data->channel_data[channel].pga = pga;
453 		data->channel_data[channel].data_rate = data_rate;
454 	}
455 
456 	return 0;
457 }
458 #endif
459 
460 static void ads1015_get_channels_config(struct i2c_client *client)
461 {
462 	unsigned int k;
463 
464 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
465 	struct ads1015_data *data = iio_priv(indio_dev);
466 	struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
467 
468 	/* prefer platform data */
469 	if (pdata) {
470 		memcpy(data->channel_data, pdata->channel_data,
471 		       sizeof(data->channel_data));
472 		return;
473 	}
474 
475 #ifdef CONFIG_OF
476 	if (!ads1015_get_channels_config_of(client))
477 		return;
478 #endif
479 	/* fallback on default configuration */
480 	for (k = 0; k < ADS1015_CHANNELS; ++k) {
481 		data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
482 		data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
483 	}
484 }
485 
486 static int ads1015_probe(struct i2c_client *client,
487 			 const struct i2c_device_id *id)
488 {
489 	struct iio_dev *indio_dev;
490 	struct ads1015_data *data;
491 	int ret;
492 
493 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
494 	if (!indio_dev)
495 		return -ENOMEM;
496 
497 	data = iio_priv(indio_dev);
498 	i2c_set_clientdata(client, indio_dev);
499 
500 	mutex_init(&data->lock);
501 
502 	indio_dev->dev.parent = &client->dev;
503 	indio_dev->info = &ads1015_info;
504 	indio_dev->name = ADS1015_DRV_NAME;
505 	indio_dev->channels = ads1015_channels;
506 	indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
507 	indio_dev->modes = INDIO_DIRECT_MODE;
508 
509 	/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
510 	ads1015_get_channels_config(client);
511 
512 	data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
513 	if (IS_ERR(data->regmap)) {
514 		dev_err(&client->dev, "Failed to allocate register map\n");
515 		return PTR_ERR(data->regmap);
516 	}
517 
518 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
519 					 ads1015_trigger_handler,
520 					 &ads1015_buffer_setup_ops);
521 	if (ret < 0) {
522 		dev_err(&client->dev, "iio triggered buffer setup failed\n");
523 		return ret;
524 	}
525 	ret = pm_runtime_set_active(&client->dev);
526 	if (ret)
527 		goto err_buffer_cleanup;
528 	pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
529 	pm_runtime_use_autosuspend(&client->dev);
530 	pm_runtime_enable(&client->dev);
531 
532 	ret = iio_device_register(indio_dev);
533 	if (ret < 0) {
534 		dev_err(&client->dev, "Failed to register IIO device\n");
535 		goto err_buffer_cleanup;
536 	}
537 
538 	return 0;
539 
540 err_buffer_cleanup:
541 	iio_triggered_buffer_cleanup(indio_dev);
542 
543 	return ret;
544 }
545 
546 static int ads1015_remove(struct i2c_client *client)
547 {
548 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
549 	struct ads1015_data *data = iio_priv(indio_dev);
550 
551 	iio_device_unregister(indio_dev);
552 
553 	pm_runtime_disable(&client->dev);
554 	pm_runtime_set_suspended(&client->dev);
555 	pm_runtime_put_noidle(&client->dev);
556 
557 	iio_triggered_buffer_cleanup(indio_dev);
558 
559 	/* power down single shot mode */
560 	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
561 				  ADS1015_CFG_MOD_MASK,
562 				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
563 }
564 
565 #ifdef CONFIG_PM
566 static int ads1015_runtime_suspend(struct device *dev)
567 {
568 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
569 	struct ads1015_data *data = iio_priv(indio_dev);
570 
571 	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
572 				  ADS1015_CFG_MOD_MASK,
573 				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
574 }
575 
576 static int ads1015_runtime_resume(struct device *dev)
577 {
578 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
579 	struct ads1015_data *data = iio_priv(indio_dev);
580 
581 	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
582 				  ADS1015_CFG_MOD_MASK,
583 				  ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
584 }
585 #endif
586 
587 static const struct dev_pm_ops ads1015_pm_ops = {
588 	SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
589 			   ads1015_runtime_resume, NULL)
590 };
591 
592 static const struct i2c_device_id ads1015_id[] = {
593 	{"ads1015", 0},
594 	{}
595 };
596 MODULE_DEVICE_TABLE(i2c, ads1015_id);
597 
598 static struct i2c_driver ads1015_driver = {
599 	.driver = {
600 		.name = ADS1015_DRV_NAME,
601 		.pm = &ads1015_pm_ops,
602 	},
603 	.probe		= ads1015_probe,
604 	.remove		= ads1015_remove,
605 	.id_table	= ads1015_id,
606 };
607 
608 module_i2c_driver(ads1015_driver);
609 
610 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
611 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
612 MODULE_LICENSE("GPL v2");
613